Signed-off-by: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- Makefile | 2 +- board/ap325rxa/Makefile | 51 ------- board/ap325rxa/ap325rxa.c | 162 --------------------- board/ap325rxa/config.mk | 26 ---- board/ap325rxa/cpld-ap325rxa.c | 206 --------------------------- board/ap325rxa/lowlevel_init.S | 243 -------------------------------- board/ap325rxa/u-boot.lds | 105 -------------- board/renesas/ap325rxa/Makefile | 51 +++++++ board/renesas/ap325rxa/ap325rxa.c | 162 +++++++++++++++++++++ board/renesas/ap325rxa/config.mk | 26 ++++ board/renesas/ap325rxa/cpld-ap325rxa.c | 206 +++++++++++++++++++++++++++ board/renesas/ap325rxa/lowlevel_init.S | 243 ++++++++++++++++++++++++++++++++ board/renesas/ap325rxa/u-boot.lds | 105 ++++++++++++++ 13 files changed, 794 insertions(+), 794 deletions(-) delete mode 100644 board/ap325rxa/Makefile delete mode 100644 board/ap325rxa/ap325rxa.c delete mode 100644 board/ap325rxa/config.mk delete mode 100644 board/ap325rxa/cpld-ap325rxa.c delete mode 100644 board/ap325rxa/lowlevel_init.S delete mode 100644 board/ap325rxa/u-boot.lds create mode 100644 board/renesas/ap325rxa/Makefile create mode 100644 board/renesas/ap325rxa/ap325rxa.c create mode 100644 board/renesas/ap325rxa/config.mk create mode 100644 board/renesas/ap325rxa/cpld-ap325rxa.c create mode 100644 board/renesas/ap325rxa/lowlevel_init.S create mode 100644 board/renesas/ap325rxa/u-boot.lds

diff --git a/Makefile b/Makefile index fceb8a2..6da4bff 100644 --- a/Makefile +++ b/Makefile @@ -3145,7 +3145,7 @@ sh7785lcr_config : unconfig ap325rxa_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa + @$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa renesas

#======================================================================== # SPARC diff --git a/board/ap325rxa/Makefile b/board/ap325rxa/Makefile deleted file mode 100644 index 21f3e6e..0000000 --- a/board/ap325rxa/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -######################################################################### -# -# Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com -# -# board/ap325rxa/Makefile -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := ap325rxa.o cpld-ap325rxa.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ap325rxa/ap325rxa.c b/board/ap325rxa/ap325rxa.c deleted file mode 100644 index 9f1112a..0000000 --- a/board/ap325rxa/ap325rxa.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> - -/* PRI control register */ -#define PRPRICR5 0xFF800048 /* LMB */ -#define PRPRICR5_D 0x2a - -/* FPGA control */ -#define FPGA_NAND_CTL 0xB410020C -#define FPGA_NAND_RST 0x0008 -#define FPGA_NAND_INIT 0x0000 -#define FPGA_NAND_RST_WAIT 10000 - -/* I/O port data */ -#define PACR_D 0x0000 -#define PBCR_D 0x0000 -#define PCCR_D 0x1000 -#define PDCR_D 0x0000 -#define PECR_D 0x0410 -#define PFCR_D 0xffff -#define PGCR_D 0x0000 -#define PHCR_D 0x5011 -#define PJCR_D 0x4400 -#define PKCR_D 0x7c00 -#define PLCR_D 0x0000 -#define PMCR_D 0x0000 -#define PNCR_D 0x0000 -#define PQCR_D 0x0000 -#define PRCR_D 0x0000 -#define PSCR_D 0x0000 -#define PTCR_D 0x0010 -#define PUCR_D 0x0fff -#define PVCR_D 0xffff -#define PWCR_D 0x0000 -#define PXCR_D 0x7500 -#define PYCR_D 0x0000 -#define PZCR_D 0x5540 - -/* Pin Function Controler data */ -#define PSELA_D 0x1410 -#define PSELB_D 0x0140 -#define PSELC_D 0x0000 -#define PSELD_D 0x0400 - -/* I/O Buffer Hi-Z data */ -#define HIZCRA_D 0x0000 -#define HIZCRB_D 0x1000 -#define HIZCRC_D 0x0000 -#define HIZCRD_D 0x0000 - -/* Module select reg data */ -#define MSELCRA_D 0x0014 -#define MSELCRB_D 0x0018 - -/* Module Stop reg Data */ -#define MSTPCR2_D 0xFFD9F280 - -/* CPLD loader */ -extern void init_cpld(void); - -int checkboard(void) -{ - puts("BOARD: AP325RXA\n"); - return 0; -} - -int board_init(void) -{ - /* Pin Function Controler Init */ - outw(PSELA_D, PSELA); - outw(PSELB_D, PSELB); - outw(PSELC_D, PSELC); - outw(PSELD_D, PSELD); - - /* I/O Buffer Hi-Z Init */ - outw(HIZCRA_D, HIZCRA); - outw(HIZCRB_D, HIZCRB); - outw(HIZCRC_D, HIZCRC); - outw(HIZCRD_D, HIZCRD); - - /* Module select reg Init */ - outw(MSELCRA_D, MSELCRA); - outw(MSELCRB_D, MSELCRB); - - /* Module Stop reg Init */ - outl(MSTPCR2_D, MSTPCR2); - - /* I/O ports */ - outw(PACR_D, PACR); - outw(PBCR_D, PBCR); - outw(PCCR_D, PCCR); - outw(PDCR_D, PDCR); - outw(PECR_D, PECR); - outw(PFCR_D, PFCR); - outw(PGCR_D, PGCR); - outw(PHCR_D, PHCR); - outw(PJCR_D, PJCR); - outw(PKCR_D, PKCR); - outw(PLCR_D, PLCR); - outw(PMCR_D, PMCR); - outw(PNCR_D, PNCR); - outw(PQCR_D, PQCR); - outw(PRCR_D, PRCR); - outw(PSCR_D, PSCR); - outw(PTCR_D, PTCR); - outw(PUCR_D, PUCR); - outw(PVCR_D, PVCR); - outw(PWCR_D, PWCR); - outw(PXCR_D, PXCR); - outw(PYCR_D, PYCR); - outw(PZCR_D, PZCR); - - /* PRI control register Init */ - outl(PRPRICR5_D, PRPRICR5); - - /* cpld init */ - init_cpld(); - - return 0; -} - -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -void ide_set_reset(int idereset) -{ - outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ - udelay(FPGA_NAND_RST_WAIT); - outw(FPGA_NAND_INIT, FPGA_NAND_CTL); -} diff --git a/board/ap325rxa/config.mk b/board/ap325rxa/config.mk deleted file mode 100644 index b52a5e5..0000000 --- a/board/ap325rxa/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu iwamatsu@nigauri.org -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -# -# TEXT_BASE refers to image _after_ relocation. -# -# NOTE: Must match value used in u-boot.lds (in this directory). -# - -TEXT_BASE = 0x8FFC0000 diff --git a/board/ap325rxa/cpld-ap325rxa.c b/board/ap325rxa/cpld-ap325rxa.c deleted file mode 100644 index 16fadcb..0000000 --- a/board/ap325rxa/cpld-ap325rxa.c +++ /dev/null @@ -1,206 +0,0 @@ -/*************************************************************** - * Project: - * CPLD SlaveSerial Configuration via embedded microprocessor. - * - * Copyright info: - * - * This is free software; you can redistribute it and/or modify - * it as you like. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Description: - * - * This is the main source file that will allow a microprocessor - * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II, - * and Spartan-II devices via the SlaveSerial Configuration Mode. - * This code is discussed in Xilinx Application Note, XAPP502. - * - * History: - * 3-October-2001 MN/MP - Created - * 20-August-2008 Renesas Solutions - Modified to SH7723 - ****************************************************************/ - -#include <common.h> - -/* Serial */ -#define SCIF_BASE 0xffe00000 /* SCIF0 */ -#define SCSMR (vu_short *)(SCIF_BASE + 0x00) -#define SCBRR (vu_char *)(SCIF_BASE + 0x04) -#define SCSCR (vu_short *)(SCIF_BASE + 0x08) -#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C) -#define SC_SR (vu_short *)(SCIF_BASE + 0x10) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define RFCR (vu_long *)0xFE400020 - -#define SCSCR_INIT 0x0038 -#define SCSCR_CLR 0x0000 -#define SCFCR_INIT 0x0006 -#define SCSMR_INIT 0x0080 -#define RFCR_CLR 0xA400 -#define SCI_TD_E 0x0020 -#define SCI_TDRE_CLEAR 0x00df - -#define BPS_SETTING_VALUE 1 /* 12.5MHz */ -#define WAIT_RFCR_COUNTER 500 - -/* CPLD data size */ -#define CPLD_DATA_SIZE 169216 - -/* out */ -#define CPLD_PFC_ADR ((vu_short *)0xA4050112) - -#define CPLD_PROG_ADR ((vu_char *)0xA4050132) -#define CPLD_PROG_DAT 0x80 - -/* in */ -#define CPLD_INIT_ADR ((vu_char *)0xA4050132) -#define CPLD_INIT_DAT 0x40 -#define CPLD_DONE_ADR ((vu_char *)0xA4050132) -#define CPLD_DONE_DAT 0x20 - -#define HIZCRB ((vu_short *)0xA405015A) - -/* data */ -#define CPLD_NOMAL_START 0xA0A80000 -#define CPLD_SAFE_START 0xA0AC0000 -#define MODE_SW (vu_char *)0xA405012A - -static void init_cpld_loader(void) -{ - - *SCSCR = SCSCR_CLR; - *SCFCR = SCFCR_INIT; - *SCSMR = SCSMR_INIT; - - *SCBRR = BPS_SETTING_VALUE; - - *RFCR = RFCR_CLR; /* Refresh counter clear */ - - while (*RFCR < WAIT_RFCR_COUNTER) - ; - - *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ - /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ - *SCSCR = SCSCR_INIT; -} - -static int check_write_ready(void) -{ - u16 status = *SC_SR; - return status & SCI_TD_E; -} - -static void write_cpld_data(char ch) -{ - while (!check_write_ready()) - ; - - *SC_TDR = ch; - *SC_SR; - *SC_SR = SCI_TDRE_CLEAR; -} - -static int delay(void) -{ - int i; - int c = 0; - for (i = 0; i < 200; i++) { - c = *(volatile int *)0xa0000000; - } - return c; -} - -/*********************************************************************** - * - * Function: slave_serial - * - * Description: Initiates SlaveSerial Configuration. - * Calls ShiftDataOut() to output serial data - * - ***********************************************************************/ -static void slave_serial(void) -{ - int i; - unsigned char *flash; - - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - delay(); - - /* - * Toggle Program Pin by Toggling Program_OE bit - * This is accomplished by writing to the Program Register in the CPLD - * - * NOTE: The Program_OE bit should be driven high to bring the Virtex - * Program Pin low. Likewise, it should be driven low - * to bring the Virtex Program Pin to High-Z - */ - - *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */ - delay(); - - /* - * Bring Program High-Z - * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z - */ - - /* Program_OE bit Low brings the Virtex Program Pin to High Z: */ - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - - while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) - delay(); - - /* Begin Slave-Serial Configuration */ - flash = (unsigned char *)CPLD_NOMAL_START; - - for (i = 0; i < CPLD_DATA_SIZE; i++) - write_cpld_data(*flash++); -} - -/*********************************************************************** - * - * Function: check_done_bit - * - * Description: This function takes monitors the CPLD Input Register - * by checking the status of the DONE bit in that Register. - * By doing so, it monitors the Xilinx Virtex device's DONE - * Pin to see if configuration bitstream has been properly - * loaded - * - ***********************************************************************/ -static void check_done_bit(void) -{ - while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT)) - ; -} - -/*********************************************************************** - * - * Function: init_cpld - * - * Description: Begins Slave Serial configuration of Xilinx FPGA - * - ***********************************************************************/ -void init_cpld(void) -{ - /* Init serial device */ - init_cpld_loader(); - - if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */ - return; - - *HIZCRB = 0x0000; - *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ - - /* write CPLD data from NOR flash to device */ - slave_serial(); - - /* - * Monitor the DONE bit in the CPLD Input Register to see if - * configuration successful - */ - - check_done_bit(); -} diff --git a/board/ap325rxa/lowlevel_init.S b/board/ap325rxa/lowlevel_init.S deleted file mode 100644 index 4f66588..0000000 --- a/board/ap325rxa/lowlevel_init.S +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com - * - * board/ap325rxa/lowlevel_init.S - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/processor.h> - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - mov.l DRVCRA_A, r1 - mov.l DRVCRA_D, r0 - mov.w r0, @r1 - - mov.l DRVCRB_A, r1 - mov.l DRVCRB_D, r0 - mov.w r0, @r1 - - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D1, r0 - mov.w r0, @r1 - - mov.l RWTCNT_A, r1 - mov.l RWTCNT_D, r0 - mov.w r0, @r1 - - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D2, r0 - mov.w r0, @r1 - - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.l r0, @r1 - - mov.l CMNCR_A, r1 - mov.l CMNCR_D, r0 - mov.l r0, @r1 - - mov.l CS0BCR_A ,r1 - mov.l CS0BCR_D ,r0 - mov.l r0, @r1 - - mov.l CS4BCR_A ,r1 - mov.l CS4BCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5ABCR_A ,r1 - mov.l CS5ABCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5BBCR_A ,r1 - mov.l CS5BBCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6ABCR_A ,r1 - mov.l CS6ABCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6BBCR_A ,r1 - mov.l CS6BBCR_D ,r0 - mov.l r0, @r1 - - mov.l CS0WCR_A ,r1 - mov.l CS0WCR_D ,r0 - mov.l r0, @r1 - - mov.l CS4WCR_A ,r1 - mov.l CS4WCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5AWCR_A ,r1 - mov.l CS5AWCR_D ,r0 - mov.l r0, @r1 - - mov.l CS5BWCR_A ,r1 - mov.l CS5BWCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6AWCR_A ,r1 - mov.l CS6AWCR_D ,r0 - mov.l r0, @r1 - - mov.l CS6BWCR_A ,r1 - mov.l CS6BWCR_D ,r0 - mov.l r0, @r1 - - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D1, r0 - mov.l r0, @r1 - - mov.l SBSC_SDWCR_A, r1 - mov.l SBSC_SDWCR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_SDPCR_A, r1 - mov.l SBSC_SDPCR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_RTCSR_A, r1 - mov.l SBSC_RTCSR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_RTCNT_A, r1 - mov.l SBSC_RTCNT_D, r0 - mov.l r0, @r1 - - mov.l SBSC_RTCOR_A, r1 - mov.l SBSC_RTCOR_D, r0 - mov.l r0, @r1 - - mov.l SBSC_SDMR3_A1, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 - - mov.l SBSC_SDMR3_A2, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 - - mov.l SLEEP_CNT, r1 -2: tst r1, r1 - nop - bf/s 2b - dt r1 - - mov.l SBSC_SDMR3_A3, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 - - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D2, r0 - mov.l r0, @r1 - - mov.l CCR_A, r1 - mov.l CCR_D, r0 - mov.l r0, @r1 - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 2 - -DRVCRA_A: .long DRVCRA -DRVCRB_A: .long DRVCRB -DRVCRA_D: .long 0x4555 -DRVCRB_D: .long 0x0005 - -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -RWTCSR_D1: .long 0xa507 -RWTCSR_D2: .long 0xa504 -RWTCNT_D: .long 0x5a00 -FRQCR_D: .long 0x0b04474a - -SBSC_SDCR_A: .long SBSC_SDCR -SBSC_SDWCR_A: .long SBSC_SDWCR -SBSC_SDPCR_A: .long SBSC_SDPCR -SBSC_RTCSR_A: .long SBSC_RTCSR -SBSC_RTCNT_A: .long SBSC_RTCNT -SBSC_RTCOR_A: .long SBSC_RTCOR -SBSC_SDMR3_A1: .long 0xfe510000 -SBSC_SDMR3_A2: .long 0xfe500242 -SBSC_SDMR3_A3: .long 0xfe5c0042 - -SBSC_SDCR_D1: .long 0x92810112 -SBSC_SDCR_D2: .long 0x92810912 -SBSC_SDWCR_D: .long 0x05162482 -SBSC_SDPCR_D: .long 0x00300087 -SBSC_RTCSR_D: .long 0xa55a0212 -SBSC_RTCNT_D: .long 0xa55a0000 -SBSC_RTCOR_D: .long 0xa55a0040 -SBSC_SDMR3_D: .long 0x00 - -CMNCR_A: .long CMNCR -CS0BCR_A: .long CS0BCR -CS4BCR_A: .long CS4BCR -CS5ABCR_A: .long CS5ABCR -CS5BBCR_A: .long CS5BBCR -CS6ABCR_A: .long CS6ABCR -CS6BBCR_A: .long CS6BBCR -CS0WCR_A: .long CS0WCR -CS4WCR_A: .long CS4WCR -CS5AWCR_A: .long CS5AWCR -CS5BWCR_A: .long CS5BWCR -CS6AWCR_A: .long CS6AWCR -CS6BWCR_A: .long CS6BWCR - -CMNCR_D: .long 0x00000013 -CS0BCR_D: .long 0x24920400 -CS4BCR_D: .long 0x24920400 -CS5ABCR_D: .long 0x24920400 -CS5BBCR_D: .long 0x7fff0600 -CS6ABCR_D: .long 0x24920400 -CS6BBCR_D: .long 0x24920600 -CS0WCR_D: .long 0x00000480 -CS4WCR_D: .long 0x00000480 -CS5AWCR_D: .long 0x00000380 -CS5BWCR_D: .long 0x00000600 -CS6AWCR_D: .long 0x00000300 -CS6BWCR_D: .long 0x00000540 - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090d - -SLEEP_CNT: .long 0x00000800 -SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/ap325rxa/u-boot.lds b/board/ap325rxa/u-boot.lds deleted file mode 100644 index e9f8dc0..0000000 --- a/board/ap325rxa/u-boot.lds +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyrigth (c) 2007 - * Nobuhiro Iwamatsu iwamatsu@nigauri.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") -OUTPUT_ARCH(sh) -ENTRY(_start) - -SECTIONS -{ - /* - Base address of internal SDRAM is 0x88000000. - Although size of SDRAM can be either 16 or 32 MBytes, - we assume 16 MBytes (ie ignore upper half if the full - 32 MBytes is present). - - NOTE: This address must match with the definition of - TEXT_BASE in config.mk (in this directory). - - */ - . = 0x88000000 + (128*1024*1024) - (256*1024); - - PROVIDE (reloc_dst = .); - - PROVIDE (_ftext = .); - PROVIDE (_fcode = .); - PROVIDE (_start = .); - - .text : - { - cpu/sh4/start.o (.text) - . = ALIGN(8192); - common/env_embedded.o (.ppcenv) - . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) - . = ALIGN(8192); - *(.text) - . = ALIGN(4); - } =0xFF - PROVIDE (_ecode = .); - .rodata : - { - *(.rodata) - . = ALIGN(4); - } - PROVIDE (_etext = .); - - - PROVIDE (_fdata = .); - .data : - { - *(.data) - . = ALIGN(4); - } - PROVIDE (_edata = .); - - PROVIDE (_fgot = .); - .got : - { - *(.got) - . = ALIGN(4); - } - PROVIDE (_egot = .); - - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); - - PROVIDE (reloc_dst_end = .); - /* _reloc_dst_end = .; */ - - PROVIDE (bss_start = .); - PROVIDE (__bss_start = .); - .bss : - { - *(.bss) - . = ALIGN(4); - } - PROVIDE (bss_end = .); - - PROVIDE (_end = .); -} diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile new file mode 100644 index 0000000..21f3e6e --- /dev/null +++ b/board/renesas/ap325rxa/Makefile @@ -0,0 +1,51 @@ +######################################################################### +# +# Copyright (C) 2008 Renesas Solutions Corp. +# Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com +# +# board/ap325rxa/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := ap325rxa.o cpld-ap325rxa.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c new file mode 100644 index 0000000..9f1112a --- /dev/null +++ b/board/renesas/ap325rxa/ap325rxa.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +/* PRI control register */ +#define PRPRICR5 0xFF800048 /* LMB */ +#define PRPRICR5_D 0x2a + +/* FPGA control */ +#define FPGA_NAND_CTL 0xB410020C +#define FPGA_NAND_RST 0x0008 +#define FPGA_NAND_INIT 0x0000 +#define FPGA_NAND_RST_WAIT 10000 + +/* I/O port data */ +#define PACR_D 0x0000 +#define PBCR_D 0x0000 +#define PCCR_D 0x1000 +#define PDCR_D 0x0000 +#define PECR_D 0x0410 +#define PFCR_D 0xffff +#define PGCR_D 0x0000 +#define PHCR_D 0x5011 +#define PJCR_D 0x4400 +#define PKCR_D 0x7c00 +#define PLCR_D 0x0000 +#define PMCR_D 0x0000 +#define PNCR_D 0x0000 +#define PQCR_D 0x0000 +#define PRCR_D 0x0000 +#define PSCR_D 0x0000 +#define PTCR_D 0x0010 +#define PUCR_D 0x0fff +#define PVCR_D 0xffff +#define PWCR_D 0x0000 +#define PXCR_D 0x7500 +#define PYCR_D 0x0000 +#define PZCR_D 0x5540 + +/* Pin Function Controler data */ +#define PSELA_D 0x1410 +#define PSELB_D 0x0140 +#define PSELC_D 0x0000 +#define PSELD_D 0x0400 + +/* I/O Buffer Hi-Z data */ +#define HIZCRA_D 0x0000 +#define HIZCRB_D 0x1000 +#define HIZCRC_D 0x0000 +#define HIZCRD_D 0x0000 + +/* Module select reg data */ +#define MSELCRA_D 0x0014 +#define MSELCRB_D 0x0018 + +/* Module Stop reg Data */ +#define MSTPCR2_D 0xFFD9F280 + +/* CPLD loader */ +extern void init_cpld(void); + +int checkboard(void) +{ + puts("BOARD: AP325RXA\n"); + return 0; +} + +int board_init(void) +{ + /* Pin Function Controler Init */ + outw(PSELA_D, PSELA); + outw(PSELB_D, PSELB); + outw(PSELC_D, PSELC); + outw(PSELD_D, PSELD); + + /* I/O Buffer Hi-Z Init */ + outw(HIZCRA_D, HIZCRA); + outw(HIZCRB_D, HIZCRB); + outw(HIZCRC_D, HIZCRC); + outw(HIZCRD_D, HIZCRD); + + /* Module select reg Init */ + outw(MSELCRA_D, MSELCRA); + outw(MSELCRB_D, MSELCRB); + + /* Module Stop reg Init */ + outl(MSTPCR2_D, MSTPCR2); + + /* I/O ports */ + outw(PACR_D, PACR); + outw(PBCR_D, PBCR); + outw(PCCR_D, PCCR); + outw(PDCR_D, PDCR); + outw(PECR_D, PECR); + outw(PFCR_D, PFCR); + outw(PGCR_D, PGCR); + outw(PHCR_D, PHCR); + outw(PJCR_D, PJCR); + outw(PKCR_D, PKCR); + outw(PLCR_D, PLCR); + outw(PMCR_D, PMCR); + outw(PNCR_D, PNCR); + outw(PQCR_D, PQCR); + outw(PRCR_D, PRCR); + outw(PSCR_D, PSCR); + outw(PTCR_D, PTCR); + outw(PUCR_D, PUCR); + outw(PVCR_D, PVCR); + outw(PWCR_D, PWCR); + outw(PXCR_D, PXCR); + outw(PYCR_D, PYCR); + outw(PZCR_D, PZCR); + + /* PRI control register Init */ + outl(PRPRICR5_D, PRPRICR5); + + /* cpld init */ + init_cpld(); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} + +void ide_set_reset(int idereset) +{ + outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ + udelay(FPGA_NAND_RST_WAIT); + outw(FPGA_NAND_INIT, FPGA_NAND_CTL); +} diff --git a/board/renesas/ap325rxa/config.mk b/board/renesas/ap325rxa/config.mk new file mode 100644 index 0000000..b52a5e5 --- /dev/null +++ b/board/renesas/ap325rxa/config.mk @@ -0,0 +1,26 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu iwamatsu@nigauri.org +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +# +# TEXT_BASE refers to image _after_ relocation. +# +# NOTE: Must match value used in u-boot.lds (in this directory). +# + +TEXT_BASE = 0x8FFC0000 diff --git a/board/renesas/ap325rxa/cpld-ap325rxa.c b/board/renesas/ap325rxa/cpld-ap325rxa.c new file mode 100644 index 0000000..16fadcb --- /dev/null +++ b/board/renesas/ap325rxa/cpld-ap325rxa.c @@ -0,0 +1,206 @@ +/*************************************************************** + * Project: + * CPLD SlaveSerial Configuration via embedded microprocessor. + * + * Copyright info: + * + * This is free software; you can redistribute it and/or modify + * it as you like. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Description: + * + * This is the main source file that will allow a microprocessor + * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II, + * and Spartan-II devices via the SlaveSerial Configuration Mode. + * This code is discussed in Xilinx Application Note, XAPP502. + * + * History: + * 3-October-2001 MN/MP - Created + * 20-August-2008 Renesas Solutions - Modified to SH7723 + ****************************************************************/ + +#include <common.h> + +/* Serial */ +#define SCIF_BASE 0xffe00000 /* SCIF0 */ +#define SCSMR (vu_short *)(SCIF_BASE + 0x00) +#define SCBRR (vu_char *)(SCIF_BASE + 0x04) +#define SCSCR (vu_short *)(SCIF_BASE + 0x08) +#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C) +#define SC_SR (vu_short *)(SCIF_BASE + 0x10) +#define SCFCR (vu_short *)(SCIF_BASE + 0x18) +#define RFCR (vu_long *)0xFE400020 + +#define SCSCR_INIT 0x0038 +#define SCSCR_CLR 0x0000 +#define SCFCR_INIT 0x0006 +#define SCSMR_INIT 0x0080 +#define RFCR_CLR 0xA400 +#define SCI_TD_E 0x0020 +#define SCI_TDRE_CLEAR 0x00df + +#define BPS_SETTING_VALUE 1 /* 12.5MHz */ +#define WAIT_RFCR_COUNTER 500 + +/* CPLD data size */ +#define CPLD_DATA_SIZE 169216 + +/* out */ +#define CPLD_PFC_ADR ((vu_short *)0xA4050112) + +#define CPLD_PROG_ADR ((vu_char *)0xA4050132) +#define CPLD_PROG_DAT 0x80 + +/* in */ +#define CPLD_INIT_ADR ((vu_char *)0xA4050132) +#define CPLD_INIT_DAT 0x40 +#define CPLD_DONE_ADR ((vu_char *)0xA4050132) +#define CPLD_DONE_DAT 0x20 + +#define HIZCRB ((vu_short *)0xA405015A) + +/* data */ +#define CPLD_NOMAL_START 0xA0A80000 +#define CPLD_SAFE_START 0xA0AC0000 +#define MODE_SW (vu_char *)0xA405012A + +static void init_cpld_loader(void) +{ + + *SCSCR = SCSCR_CLR; + *SCFCR = SCFCR_INIT; + *SCSMR = SCSMR_INIT; + + *SCBRR = BPS_SETTING_VALUE; + + *RFCR = RFCR_CLR; /* Refresh counter clear */ + + while (*RFCR < WAIT_RFCR_COUNTER) + ; + + *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ + /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ + *SCSCR = SCSCR_INIT; +} + +static int check_write_ready(void) +{ + u16 status = *SC_SR; + return status & SCI_TD_E; +} + +static void write_cpld_data(char ch) +{ + while (!check_write_ready()) + ; + + *SC_TDR = ch; + *SC_SR; + *SC_SR = SCI_TDRE_CLEAR; +} + +static int delay(void) +{ + int i; + int c = 0; + for (i = 0; i < 200; i++) { + c = *(volatile int *)0xa0000000; + } + return c; +} + +/*********************************************************************** + * + * Function: slave_serial + * + * Description: Initiates SlaveSerial Configuration. + * Calls ShiftDataOut() to output serial data + * + ***********************************************************************/ +static void slave_serial(void) +{ + int i; + unsigned char *flash; + + *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ + delay(); + + /* + * Toggle Program Pin by Toggling Program_OE bit + * This is accomplished by writing to the Program Register in the CPLD + * + * NOTE: The Program_OE bit should be driven high to bring the Virtex + * Program Pin low. Likewise, it should be driven low + * to bring the Virtex Program Pin to High-Z + */ + + *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */ + delay(); + + /* + * Bring Program High-Z + * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z + */ + + /* Program_OE bit Low brings the Virtex Program Pin to High Z: */ + *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ + + while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) + delay(); + + /* Begin Slave-Serial Configuration */ + flash = (unsigned char *)CPLD_NOMAL_START; + + for (i = 0; i < CPLD_DATA_SIZE; i++) + write_cpld_data(*flash++); +} + +/*********************************************************************** + * + * Function: check_done_bit + * + * Description: This function takes monitors the CPLD Input Register + * by checking the status of the DONE bit in that Register. + * By doing so, it monitors the Xilinx Virtex device's DONE + * Pin to see if configuration bitstream has been properly + * loaded + * + ***********************************************************************/ +static void check_done_bit(void) +{ + while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT)) + ; +} + +/*********************************************************************** + * + * Function: init_cpld + * + * Description: Begins Slave Serial configuration of Xilinx FPGA + * + ***********************************************************************/ +void init_cpld(void) +{ + /* Init serial device */ + init_cpld_loader(); + + if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */ + return; + + *HIZCRB = 0x0000; + *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ + + /* write CPLD data from NOR flash to device */ + slave_serial(); + + /* + * Monitor the DONE bit in the CPLD Input Register to see if + * configuration successful + */ + + check_done_bit(); +} diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S new file mode 100644 index 0000000..4f66588 --- /dev/null +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu iwamatsu.nobuhiro@renesas.com + * + * board/ap325rxa/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + mov.l DRVCRA_A, r1 + mov.l DRVCRA_D, r0 + mov.w r0, @r1 + + mov.l DRVCRB_A, r1 + mov.l DRVCRB_D, r0 + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 + mov.l RWTCSR_D1, r0 + mov.w r0, @r1 + + mov.l RWTCNT_A, r1 + mov.l RWTCNT_D, r0 + mov.w r0, @r1 + + mov.l RWTCSR_A, r1 + mov.l RWTCSR_D2, r0 + mov.w r0, @r1 + + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.l r0, @r1 + + mov.l CMNCR_A, r1 + mov.l CMNCR_D, r0 + mov.l r0, @r1 + + mov.l CS0BCR_A ,r1 + mov.l CS0BCR_D ,r0 + mov.l r0, @r1 + + mov.l CS4BCR_A ,r1 + mov.l CS4BCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5ABCR_A ,r1 + mov.l CS5ABCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5BBCR_A ,r1 + mov.l CS5BBCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6ABCR_A ,r1 + mov.l CS6ABCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6BBCR_A ,r1 + mov.l CS6BBCR_D ,r0 + mov.l r0, @r1 + + mov.l CS0WCR_A ,r1 + mov.l CS0WCR_D ,r0 + mov.l r0, @r1 + + mov.l CS4WCR_A ,r1 + mov.l CS4WCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5AWCR_A ,r1 + mov.l CS5AWCR_D ,r0 + mov.l r0, @r1 + + mov.l CS5BWCR_A ,r1 + mov.l CS5BWCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6AWCR_A ,r1 + mov.l CS6AWCR_D ,r0 + mov.l r0, @r1 + + mov.l CS6BWCR_A ,r1 + mov.l CS6BWCR_D ,r0 + mov.l r0, @r1 + + mov.l SBSC_SDCR_A, r1 + mov.l SBSC_SDCR_D1, r0 + mov.l r0, @r1 + + mov.l SBSC_SDWCR_A, r1 + mov.l SBSC_SDWCR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_SDPCR_A, r1 + mov.l SBSC_SDPCR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_RTCSR_A, r1 + mov.l SBSC_RTCSR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_RTCNT_A, r1 + mov.l SBSC_RTCNT_D, r0 + mov.l r0, @r1 + + mov.l SBSC_RTCOR_A, r1 + mov.l SBSC_RTCOR_D, r0 + mov.l r0, @r1 + + mov.l SBSC_SDMR3_A1, r1 + mov.l SBSC_SDMR3_D, r0 + mov.b r0, @r1 + + mov.l SBSC_SDMR3_A2, r1 + mov.l SBSC_SDMR3_D, r0 + mov.b r0, @r1 + + mov.l SLEEP_CNT, r1 +2: tst r1, r1 + nop + bf/s 2b + dt r1 + + mov.l SBSC_SDMR3_A3, r1 + mov.l SBSC_SDMR3_D, r0 + mov.b r0, @r1 + + mov.l SBSC_SDCR_A, r1 + mov.l SBSC_SDCR_D2, r0 + mov.l r0, @r1 + + mov.l CCR_A, r1 + mov.l CCR_D, r0 + mov.l r0, @r1 + + ! BL bit off (init = ON) (?!?) + + stc sr, r0 ! BL bit off(init=ON) + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + mov #0, r0 + + .align 2 + +DRVCRA_A: .long DRVCRA +DRVCRB_A: .long DRVCRB +DRVCRA_D: .long 0x4555 +DRVCRB_D: .long 0x0005 + +RWTCSR_A: .long RWTCSR +RWTCNT_A: .long RWTCNT +FRQCR_A: .long FRQCR +RWTCSR_D1: .long 0xa507 +RWTCSR_D2: .long 0xa504 +RWTCNT_D: .long 0x5a00 +FRQCR_D: .long 0x0b04474a + +SBSC_SDCR_A: .long SBSC_SDCR +SBSC_SDWCR_A: .long SBSC_SDWCR +SBSC_SDPCR_A: .long SBSC_SDPCR +SBSC_RTCSR_A: .long SBSC_RTCSR +SBSC_RTCNT_A: .long SBSC_RTCNT +SBSC_RTCOR_A: .long SBSC_RTCOR +SBSC_SDMR3_A1: .long 0xfe510000 +SBSC_SDMR3_A2: .long 0xfe500242 +SBSC_SDMR3_A3: .long 0xfe5c0042 + +SBSC_SDCR_D1: .long 0x92810112 +SBSC_SDCR_D2: .long 0x92810912 +SBSC_SDWCR_D: .long 0x05162482 +SBSC_SDPCR_D: .long 0x00300087 +SBSC_RTCSR_D: .long 0xa55a0212 +SBSC_RTCNT_D: .long 0xa55a0000 +SBSC_RTCOR_D: .long 0xa55a0040 +SBSC_SDMR3_D: .long 0x00 + +CMNCR_A: .long CMNCR +CS0BCR_A: .long CS0BCR +CS4BCR_A: .long CS4BCR +CS5ABCR_A: .long CS5ABCR +CS5BBCR_A: .long CS5BBCR +CS6ABCR_A: .long CS6ABCR +CS6BBCR_A: .long CS6BBCR +CS0WCR_A: .long CS0WCR +CS4WCR_A: .long CS4WCR +CS5AWCR_A: .long CS5AWCR +CS5BWCR_A: .long CS5BWCR +CS6AWCR_A: .long CS6AWCR +CS6BWCR_A: .long CS6BWCR + +CMNCR_D: .long 0x00000013 +CS0BCR_D: .long 0x24920400 +CS4BCR_D: .long 0x24920400 +CS5ABCR_D: .long 0x24920400 +CS5BBCR_D: .long 0x7fff0600 +CS6ABCR_D: .long 0x24920400 +CS6BBCR_D: .long 0x24920600 +CS0WCR_D: .long 0x00000480 +CS4WCR_D: .long 0x00000480 +CS5AWCR_D: .long 0x00000380 +CS5BWCR_D: .long 0x00000600 +CS6AWCR_D: .long 0x00000300 +CS6BWCR_D: .long 0x00000540 + +CCR_A: .long 0xff00001c +CCR_D: .long 0x0000090d + +SLEEP_CNT: .long 0x00000800 +SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/ap325rxa/u-boot.lds b/board/renesas/ap325rxa/u-boot.lds new file mode 100644 index 0000000..e9f8dc0 --- /dev/null +++ b/board/renesas/ap325rxa/u-boot.lds @@ -0,0 +1,105 @@ +/* + * Copyrigth (c) 2007 + * Nobuhiro Iwamatsu iwamatsu@nigauri.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + Base address of internal SDRAM is 0x88000000. + Although size of SDRAM can be either 16 or 32 MBytes, + we assume 16 MBytes (ie ignore upper half if the full + 32 MBytes is present). + + NOTE: This address must match with the definition of + TEXT_BASE in config.mk (in this directory). + + */ + . = 0x88000000 + (128*1024*1024) - (256*1024); + + PROVIDE (reloc_dst = .); + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + cpu/sh4/start.o (.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(.rodata) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +}