[U-Boot] [PATCH 01/11] arm: omap5: don't enable misc_init_r by default
Out of all OMAP5-like boards, only one of them needs CONFIG_MISC_INIT_R, so it's best to enable that for that particular board only, instead of enabling for all boards unconditionally.
Signed-off-by: Felipe Balbi balbi@ti.com --- board/ti/dra7xx/evm.c | 12 ------------ include/configs/cm_t54.h | 1 - include/configs/omap5_uevm.h | 1 + include/configs/ti_omap5_common.h | 1 - 4 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 37df7b2..6522241 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -96,18 +96,6 @@ int board_late_init(void) return 0; }
-/** - * @brief misc_init_r - Configure EVM board specific configurations - * such as power configurations, ethernet initialization as phase2 of - * boot sequence - * - * @return 0 - */ -int misc_init_r(void) -{ - return 0; -} - static void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) { diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 641ab48..92ce1e1 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -16,7 +16,6 @@
#include <configs/ti_omap5_common.h>
-#undef CONFIG_MISC_INIT_R #undef CONFIG_SPL_OS_BOOT
/* Enable Generic board */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index e8dc462..e07795f 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -23,6 +23,7 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200
+#define CONFIG_MISC_INIT_R /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 3166392..5b03fb1 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -19,7 +19,6 @@
#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_MISC_INIT_R #define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody.
Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 10 +++++----- arch/arm/include/asm/arch-omap5/clock.h | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 0257383..8b4d53a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -365,31 +365,31 @@ struct vcores_data dra752_volts = { .mpu.value = VDD_MPU_DRA752, .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038,
.eve.value = VDD_EVE_DRA752, .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038,
.gpu.value = VDD_GPU_DRA752, .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, .gpu.pmic = &tps659038,
.core.value = VDD_CORE_DRA752, .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.addr = TPS659038_REG_ADDR_SMPS7, .core.pmic = &tps659038,
.iva.value = VDD_IVA_DRA752, .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.addr = TPS659038_REG_ADDR_SMPS8, .iva.pmic = &tps659038, };
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 30d9de2..7eacba2 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -278,11 +278,11 @@
/* TPS659038 */ #define TPS659038_I2C_SLAVE_ADDR 0x58 -#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 -#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B -#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F -#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 -#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 +#define TPS659038_REG_ADDR_SMPS12 0x23 +#define TPS659038_REG_ADDR_SMPS45 0x2B +#define TPS659038_REG_ADDR_SMPS6 0x2F +#define TPS659038_REG_ADDR_SMPS7 0x33 +#define TPS659038_REG_ADDR_SMPS8 0x37
/* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60
On Thu, Nov 06, 2014 at 08:28:43AM -0600, Felipe Balbi wrote:
Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:43AM -0600, Felipe Balbi wrote:
Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
some boards might want to use USB1 for host, without fiddling those registers it'll be impossible.
Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index ff08ef4..0745d42 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_phy_power_usb = 0x4A002370, .control_phy_power_sata = 0x4A002374, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, @@ -800,6 +801,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, .cm_clkmode_dpll_gmac = 0x4a0052a8, + .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640, .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
/* cm1.mpu */ @@ -906,6 +908,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, + .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0,
/* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700,
On Thu, Nov 06, 2014 at 08:28:44AM -0600, Felipe Balbi wrote:
some boards might want to use USB1 for host, without fiddling those registers it'll be impossible.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:44AM -0600, Felipe Balbi wrote:
some boards might want to use USB1 for host, without fiddling those registers it'll be impossible.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
there's no such function usb3_phy_power(), it's likely that author meant to call, usb_phy_power() instead, but that's already called properly from xhci-omap.c.
Signed-off-by: Felipe Balbi balbi@ti.com --- drivers/usb/phy/omap_usb_phy.c | 2 -- 1 file changed, 2 deletions(-)
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c index f78d532..52a3664 100644 --- a/drivers/usb/phy/omap_usb_phy.c +++ b/drivers/usb/phy/omap_usb_phy.c @@ -118,7 +118,6 @@ void usb_phy_power(int on) void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) { omap_usb_dpll_lock(phy_regs); - usb3_phy_partial_powerup(phy_regs); /* * Give enough time for the PHY to partially power-up before @@ -126,7 +125,6 @@ void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) * team. */ mdelay(100); - usb3_phy_power(1); }
static void omap_enable_usb3_phy(struct omap_xhci *omap)
On Thu, Nov 06, 2014 at 08:28:45AM -0600, Felipe Balbi wrote:
there's no such function usb3_phy_power(), it's likely that author meant to call, usb_phy_power() instead, but that's already called properly from xhci-omap.c.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:45AM -0600, Felipe Balbi wrote:
there's no such function usb3_phy_power(), it's likely that author meant to call, usb_phy_power() instead, but that's already called properly from xhci-omap.c.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
If we want to have two sections, one on each EMIF, without interleaving, current code wouldn't enable emif2. Fix that problem.
Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/cpu/armv7/omap-common/emif-common.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index c8e9bc8..e601ba1 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1226,13 +1226,14 @@ void dmm_init(u32 base) emif1_enabled = 1; emif2_enabled = 1; break; - } else if (valid == 1) { + } + + if (valid == 1) emif1_enabled = 1; - } else if (valid == 2) { + + if (valid == 2) emif2_enabled = 1; - } } - }
static void do_bug0039_workaround(u32 base)
On Thu, Nov 06, 2014 at 08:28:46AM -0600, Felipe Balbi wrote:
If we want to have two sections, one on each EMIF, without interleaving, current code wouldn't enable emif2. Fix that problem.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:46AM -0600, Felipe Balbi wrote:
If we want to have two sections, one on each EMIF, without interleaving, current code wouldn't enable emif2. Fix that problem.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
From: Franklin S Cooper Jr fcooper@ti.com
* Since the emmc isn't always programed trying to load the fs from the emmc causes boot failures/kernel panic.
* The current bootcmd is set to: bootcmd=run findfdt; run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; \ setenv mmcroot /dev/mmcblk0p2 rw; run mmcboot;
My guess is the env variables should be set so that sd card boot (dt,kernel,fs) is the default and then fallback to emmc if it fails (no sd card detected)
The current bootcmd attempts to set mmcroot to the sd card rootfs but that code doesn't run due to mmcboot being ran early on.
Signed-off-by: Franklin Cooper Jr. fcooper@ti.com Signed-off-by: Felipe Balbi balbi@ti.com --- include/configs/ti_omap5_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 5b03fb1..de96d7d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -78,7 +78,7 @@ "partitions=" PARTS_DEFAULT "\0" \ "optargs=\0" \ "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk1p2 rw\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcrootfstype=ext4 rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \
On Thu, Nov 06, 2014 at 08:28:47AM -0600, Felipe Balbi wrote:
From: Franklin S Cooper Jr fcooper@ti.com
Since the emmc isn't always programed trying to load the fs from the emmc causes boot failures/kernel panic.
The current bootcmd is set to: bootcmd=run findfdt; run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; \ setenv mmcroot /dev/mmcblk0p2 rw; run mmcboot;
My guess is the env variables should be set so that sd card boot (dt,kernel,fs) is the default and then fallback to emmc if it fails (no sd card detected)
The current bootcmd attempts to set mmcroot to the sd card rootfs but that code doesn't run due to mmcboot being ran early on.
Signed-off-by: Franklin Cooper Jr. fcooper@ti.com Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:47AM -0600, Felipe Balbi wrote:
From: Franklin S Cooper Jr fcooper@ti.com
Since the emmc isn't always programed trying to load the fs from the emmc causes boot failures/kernel panic.
The current bootcmd is set to: bootcmd=run findfdt; run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; \ setenv mmcroot /dev/mmcblk0p2 rw; run mmcboot;
My guess is the env variables should be set so that sd card boot (dt,kernel,fs) is the default and then fallback to emmc if it fails (no sd card detected)
The current bootcmd attempts to set mmcroot to the sd card rootfs but that code doesn't run due to mmcboot being ran early on.
Signed-off-by: Franklin Cooper Jr. fcooper@ti.com Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
this way we can let boards overwrite based on what they need.
Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 8b4d53a..95f1686 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -593,7 +593,7 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = { .ctrl_ddr_ctrl_ext_0 = 0xA2000000, };
-void hw_data_init(void) +void __weak hw_data_init(void) { u32 omap_rev = omap_revision();
On Thu, Nov 06, 2014 at 08:28:48AM -0600, Felipe Balbi wrote:
this way we can let boards overwrite based on what they need.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:48AM -0600, Felipe Balbi wrote:
this way we can let boards overwrite based on what they need.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
this will allow for boards to overwrite those in case memory setup is different.
Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/cpu/armv7/omap5/sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 065199b..7d8cec0 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -513,7 +513,7 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY };
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, +void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) {
On Thu, Nov 06, 2014 at 08:28:49AM -0600, Felipe Balbi wrote:
this will allow for boards to overwrite those in case memory setup is different.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:49AM -0600, Felipe Balbi wrote:
this will allow for boards to overwrite those in case memory setup is different.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
expose those two definitions so they can be used by another board which we're adding in upcoming patches.
Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/include/asm/omap_common.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 1838234..323952f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -540,6 +540,7 @@ extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; extern struct prcm_regs const dra7xx_prcm; extern struct dplls const **dplls_data; +extern struct dplls dra7xx_dplls; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; @@ -547,6 +548,8 @@ extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+extern struct pmic_data tps659038; + void hw_data_init(void);
const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
On Thu, Nov 06, 2014 at 08:28:50AM -0600, Felipe Balbi wrote:
expose those two definitions so they can be used by another board which we're adding in upcoming patches.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:50AM -0600, Felipe Balbi wrote:
expose those two definitions so they can be used by another board which we're adding in upcoming patches.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
just add a few ifdefs around because this device is very similar to dra7xxx.
Signed-off-by: Felipe Balbi balbi@ti.com --- arch/arm/cpu/armv7/omap-common/boot-common.c | 2 +- arch/arm/include/asm/arch-omap5/clock.h | 2 +- arch/arm/include/asm/arch-omap5/omap.h | 4 ++-- drivers/mmc/omap_hsmmc.c | 5 +++-- drivers/power/palmas.c | 2 +- drivers/spi/ti_qspi.c | 8 ++++---- include/linux/usb/xhci-omap.h | 4 ++++ 7 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index fb535eb..b819fe2 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -57,7 +57,7 @@ void save_omap_boot_params(void) } }
-#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) /* * We get different values for QSPI_1 and QSPI_4 being used, but * don't actually care about this difference. Rather than diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 7eacba2..0dc584b 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -314,7 +314,7 @@ */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define V_OSCK 20000000 /* Clock output from T2 */ #else #define V_OSCK 19200000 /* Clock output from T2 */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index b9600cf..e218159 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -27,7 +27,7 @@ #define CONTROL_CORE_ID_CODE 0x4A002204 #define CONTROL_WKUP_ID_CODE 0x4AE0C204
-#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE #else #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE @@ -163,7 +163,7 @@ struct s32ktimer { * much larger) and do not, at this time, make use of the additional * space. */ -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ #else diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index ef2cbf9..1bfbe2a 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -661,7 +661,8 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, case 1: priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ - defined(CONFIG_DRA7XX)) && defined(CONFIG_HSMMC2_8BIT) + defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && \ + defined(CONFIG_HSMMC2_8BIT) /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ host_caps_val |= MMC_MODE_8BIT; #endif @@ -670,7 +671,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, #ifdef OMAP_HSMMC3_BASE case 2: priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; -#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) +#if (defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)) && defined(CONFIG_HSMMC3_8BIT) /* Enable 8-bit interface for eMMC on DRA7XX */ host_caps_val |= MMC_MODE_8BIT; #endif diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index cfbc9dc..6430fe0 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -27,7 +27,7 @@ int palmas_mmc1_poweron_ldo(void) { u8 val = 0;
-#if defined(CONFIG_DRA7XX) +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) /* * Currently valid for the dra7xx_evm board: * Set TPS659038 LDO1 to 3.0 V diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index fd7fea8..857b604 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -102,7 +102,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) struct spi_slave *slave = &qslave->slave; u32 memval = 0;
-#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) slave->memory_map = (void *)MMAP_START_ADDR_DRA; #else slave->memory_map = (void *)MMAP_START_ADDR_AM43x; @@ -244,7 +244,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, uint status; int timeout;
-#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) int val; #endif
@@ -254,7 +254,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { writel(MM_SWITCH, &qslave->base->memswitch); -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO); val |= MEM_CS; writel(val, CORE_CTRL_IO); @@ -262,7 +262,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, return 0; } else if (flags & SPI_XFER_MMAP_END) { writel(~MM_SWITCH, &qslave->base->memswitch); -#ifdef CONFIG_DRA7XX +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO); val &= MEM_CS_UNSELECT; writel(val, CORE_CTRL_IO); diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h index 82630ad..cb166e6 100644 --- a/include/linux/usb/xhci-omap.h +++ b/include/linux/usb/xhci-omap.h @@ -14,6 +14,10 @@ #define OMAP_XHCI_BASE 0x488d0000 #define OMAP_OCP1_SCP_BASE 0x4A081000 #define OMAP_OTG_WRAPPER_BASE 0x488c0000 +#elif defined CONFIG_AM57XX +#define OMAP_XHCI_BASE 0x48890000 +#define OMAP_OCP1_SCP_BASE 0x4A084c00 +#define OMAP_OTG_WRAPPER_BASE 0x48880000 #elif defined CONFIG_AM43XX #define OMAP_XHCI_BASE 0x483d0000 #define OMAP_OCP1_SCP_BASE 0x483E8000
On Thu, Nov 06, 2014 at 08:28:51AM -0600, Felipe Balbi wrote:
just add a few ifdefs around because this device is very similar to dra7xxx.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:51AM -0600, Felipe Balbi wrote:
just add a few ifdefs around because this device is very similar to dra7xxx.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
This is the bare minimum support for Beagle x15 into u-boot. There is still quite some work in order to get this in good shape, but it's a start.
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/Kconfig | 4 + board/ti/beagle_x15/Kconfig | 12 ++ board/ti/beagle_x15/Makefile | 8 + board/ti/beagle_x15/board.c | 328 ++++++++++++++++++++++++++++++++++++++ board/ti/beagle_x15/mux_data.h | 55 +++++++ configs/beagle_x15_defconfig | 5 + include/configs/beagle_x15.h | 89 +++++++++++ include/configs/ti_omap5_common.h | 2 + 8 files changed, 503 insertions(+) create mode 100644 board/ti/beagle_x15/Kconfig create mode 100644 board/ti/beagle_x15/Makefile create mode 100644 board/ti/beagle_x15/board.c create mode 100644 board/ti/beagle_x15/mux_data.h create mode 100644 configs/beagle_x15_defconfig create mode 100644 include/configs/beagle_x15.h
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 129982c..aca862d 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX"
+config TARGET_BEAGLE_X15 + bool "BeagleBoard X15" + endchoice
config SYS_SOC @@ -20,5 +23,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig"
endif diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000..a305ff1 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15 + +config SYS_BOARD + default "beagle_x15" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "beagle_x15" + +endif diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000..5cd6873 --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000..5cafc87 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi balbi@ti.com + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <palmas.h> +#include <sata.h> +#include <usb.h> +#include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sata.h> +#include <asm/arch/gpio.h> +#include <environment.h> + +#include "mux_data.h" + +#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: BeagleBoard x15\n" +}; + +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { + .dmm_lisa_map_3 = 0x80740300, + .is_ma_present = 0x1 +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &beagle_x15_lisa_regs; +} + +static const struct emif_regs beagle_x15_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851B32, /* dont know what to do about this */ + .sdram_config = 0x61851B32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCEEF266B, + .sdram_tim2 = 0x328F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050001, /* not sure where in gel file */ + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0E24400A, /* not sure what to do about this */ + .emif_ddr_phy_ctlr_1 = 0x0E24400A, /* based on non hw level enabled */ + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, /* not sure wherein gel file */ + .emif_ddr_ext_phy_ctrl_2 = 0x00740074, + .emif_ddr_ext_phy_ctrl_3 = 0x00780078, + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, /* based on non hw level enabled */ + .emif_rd_wr_lvl_ctl = 0x00000000, /* not sure where based in gel file */ + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + *regs = &beagle_x15_ddr3_532mhz_emif_regs; +} + +static const u32 beagle_x15_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, // 6 + + + 0x00360036, // 7 + 0x00340034, // 8 + 0x00360036, // 9 + 0x00350035, // 10 + 0x00350035, // 11 + + 0x01ff01ff, // 12 + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + + 0x00430043, + 0x003e003e, + 0x004a004a, + 0x00470047, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{ + *regs = beagle_x15_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_ddr3_ext_phy_ctrl_const_regs); +} + +struct vcores_data beagle_x15_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS45, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS6, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, +}; + +void hw_data_init(void) +{ + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &beagle_x15_volts; + *ctrl = &dra7xx_ctrl; +} + +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int board_late_init(void) +{ + init_sata(0); + /* + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds + * This is the POWERHOLD-in-Low behavior. + */ + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif + +#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, + OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M); + + return 0; +} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000..2294abe --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi balbi@ti.com + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_ + +#include <asm/arch/mux_dra7xx.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, + {USB1_DRVVBUS, (M0 | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ +}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000..872ab63 --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000..2009f5a --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated. + * Felipe Balbi balbi@ti.com + * + * Configuration settings for the TI Beagle x15 board. + * See ti_omap5_common.h for omap5 common settings. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H + +#define CONFIG_AM57XX + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" + +#define CONFIG_CMD_SAVEENV + +#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include <configs/ti_omap5_common.h> + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB + +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index de96d7d..c47651d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -117,6 +117,8 @@ "setenv fdtfile dra7-evm.dtb; fi;" \ "if test $board_name = dra72x; then " \ "setenv fdtfile dra72-evm.dtb; fi;" \ + "if test $board_name = beagle_x15; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
On Thu, Nov 6, 2014 at 8:28 AM, Felipe Balbi balbi@ti.com wrote:
This is the bare minimum support for Beagle x15 into u-boot. There is still quite some work in order to get this in good shape, but it's a start.
Sorry, I should have commented earlier :)
we could expand this a little more here? How about: BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
ofcourse - the wiki is yet to be built up..
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com
arch/arm/cpu/armv7/omap5/Kconfig | 4 + board/ti/beagle_x15/Kconfig | 12 ++ board/ti/beagle_x15/Makefile | 8 + board/ti/beagle_x15/board.c | 328 ++++++++++++++++++++++++++++++++++++++ board/ti/beagle_x15/mux_data.h | 55 +++++++ configs/beagle_x15_defconfig | 5 + include/configs/beagle_x15.h | 89 +++++++++++ include/configs/ti_omap5_common.h | 2 + 8 files changed, 503 insertions(+) create mode 100644 board/ti/beagle_x15/Kconfig create mode 100644 board/ti/beagle_x15/Makefile create mode 100644 board/ti/beagle_x15/board.c create mode 100644 board/ti/beagle_x15/mux_data.h create mode 100644 configs/beagle_x15_defconfig create mode 100644 include/configs/beagle_x15.h
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 129982c..aca862d 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX"
+config TARGET_BEAGLE_X15
bool "BeagleBoard X15"endchoice
config SYS_SOC @@ -20,5 +23,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig"
endif diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000..a305ff1 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15
+config SYS_BOARD
default "beagle_x15"+config SYS_VENDOR
default "ti"+config SYS_CONFIG_NAME
default "beagle_x15"+endif diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000..5cd6873 --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000..5cafc87 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,328 @@ +/*
- Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
- Author: Felipe Balbi balbi@ti.com
- Based on board/ti/dra7xx/evm.c
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <palmas.h> +#include <sata.h> +#include <usb.h> +#include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sata.h> +#include <asm/arch/gpio.h> +#include <environment.h>
+#include "mux_data.h"
+#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif
+DECLARE_GLOBAL_DATA_PTR;
+const struct omap_sysinfo sysinfo = {
"Board: BeagleBoard x15\n"+};
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
.dmm_lisa_map_3 = 0x80740300,.is_ma_present = 0x1+};
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{
*dmm_lisa_regs = &beagle_x15_lisa_regs;+}
+static const struct emif_regs beagle_x15_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851B32, /* dont know what to do about this */.sdram_config = 0x61851B32,.sdram_config2 = 0x00000000,.ref_ctrl = 0x00001035,.sdram_tim1 = 0xCEEF266B,.sdram_tim2 = 0x328F7FDA,.sdram_tim3 = 0x027F88A8,.read_idle_ctrl = 0x00050001, /* not sure where in gel file */.zq_config = 0x0007190B,.temp_alert_config = 0x00000000,.emif_ddr_phy_ctlr_1_init = 0x0E24400A, /* not sure what to do about this */.emif_ddr_phy_ctlr_1 = 0x0E24400A, /* based on non hw level enabled */.emif_ddr_ext_phy_ctrl_1 = 0x10040100, /* not sure wherein gel file */.emif_ddr_ext_phy_ctrl_2 = 0x00740074,.emif_ddr_ext_phy_ctrl_3 = 0x00780078,.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,.emif_rd_wr_lvl_rmp_win = 0x00000000,.emif_rd_wr_lvl_rmp_ctl = 0x00000000, /* based on non hw level enabled */.emif_rd_wr_lvl_ctl = 0x00000000, /* not sure where based in gel file */.emif_rd_wr_exec_thresh = 0x00000305+};
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{
*regs = &beagle_x15_ddr3_532mhz_emif_regs;+}
+static const u32 beagle_x15_ddr3_ext_phy_ctrl_const_regs[] = {
0x00800080, // 60x00360036, // 70x00340034, // 80x00360036, // 90x00350035, // 100x00350035, // 110x01ff01ff, // 120x01ff01ff,0x01ff01ff,0x01ff01ff,0x01ff01ff,0x00430043,0x003e003e,0x004a004a,0x00470047,0x00400040,0x00000000,0x00600020,0x40010080,0x08102040,0x00400040,0x00400040,0x00400040,0x00400040,0x00400040+};
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{
*regs = beagle_x15_ddr3_ext_phy_ctrl_const_regs;*size = ARRAY_SIZE(beagle_x15_ddr3_ext_phy_ctrl_const_regs);+}
+struct vcores_data beagle_x15_volts = {
.mpu.value = VDD_MPU_DRA752,.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,.mpu.addr = TPS659038_REG_ADDR_SMPS12,.mpu.pmic = &tps659038,.eve.value = VDD_EVE_DRA752,.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,.eve.addr = TPS659038_REG_ADDR_SMPS45,.eve.pmic = &tps659038,.gpu.value = VDD_GPU_DRA752,.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,.gpu.addr = TPS659038_REG_ADDR_SMPS45,.gpu.pmic = &tps659038,.core.value = VDD_CORE_DRA752,.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,.core.addr = TPS659038_REG_ADDR_SMPS6,.core.pmic = &tps659038,.iva.value = VDD_IVA_DRA752,.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,.iva.addr = TPS659038_REG_ADDR_SMPS45,.iva.pmic = &tps659038,+};
+void hw_data_init(void) +{
*prcm = &dra7xx_prcm;*dplls_data = &dra7xx_dplls;*omap_vcores = &beagle_x15_volts;*ctrl = &dra7xx_ctrl;+}
+int board_init(void) +{
gpmc_init();gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);return 0;+}
+int board_late_init(void) +{
init_sata(0);/** DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds* This is the POWERHOLD-in-Low behavior.*/palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);return 0;+}
+static void do_set_mux32(u32 base,
struct pad_conf_entry const *array, int size)+{
int i;struct pad_conf_entry *pad = (struct pad_conf_entry *)array;for (i = 0; i < size; i++, pad++)writel(pad->val, base + pad->offset);+}
+void set_muxconf_regs_essential(void) +{
do_set_mux32((*ctrl)->control_padconf_core_base,core_padconf_array_essential,sizeof(core_padconf_array_essential) /sizeof(struct pad_conf_entry));+}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{
omap_mmc_init(0, 0, 0, -1, -1);omap_mmc_init(1, 0, 0, -1, -1);return 0;+} +#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{
/* break into full u-boot on 'c' */if (serial_tstc() && serial_getc() == 'c')return 1;+#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();env_relocate_spec();if (getenv_yesno("boot_os") != 1)return 1;+#endif
return 0;+} +#endif
+#ifdef CONFIG_DRIVER_TI_CPSW
+/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+static void cpsw_control(int enabled) +{
/* VTP can be added here */+}
+static struct cpsw_slave_data cpsw_slaves[] = {
{.slave_reg_ofs = 0x208,.sliver_reg_ofs = 0xd80,.phy_addr = 1,},{.slave_reg_ofs = 0x308,.sliver_reg_ofs = 0xdc0,.phy_addr = 2,},+};
+static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,.cpsw_base = CPSW_BASE,.mdio_div = 0xff,.channels = 8,.cpdma_reg_ofs = 0x800,.slaves = 1,.slave_data = cpsw_slaves,.ale_reg_ofs = 0xd00,.ale_entries = 1024,.host_port_reg_ofs = 0x108,.hw_stats_reg_ofs = 0x900,.bd_ram_ofs = 0x2000,.mac_control = (1 << 5),.control = cpsw_control,.host_port_num = 0,.version = CPSW_CTRL_VERSION_2,+};
+int board_eth_init(bd_t *bis) +{
int ret;uint8_t mac_addr[6];uint32_t mac_hi, mac_lo;uint32_t ctrl_val;/* try reading mac address from efuse */mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);mac_addr[0] = (mac_hi & 0xFF0000) >> 16;mac_addr[1] = (mac_hi & 0xFF00) >> 8;mac_addr[2] = mac_hi & 0xFF;mac_addr[3] = (mac_lo & 0xFF0000) >> 16;mac_addr[4] = (mac_lo & 0xFF00) >> 8;mac_addr[5] = mac_lo & 0xFF;if (!getenv("ethaddr")) {printf("<ethaddr> not set. Validating first E-fuse MAC\n");if (is_valid_ether_addr(mac_addr))eth_setenv_enetaddr("ethaddr", mac_addr);}mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);mac_addr[0] = (mac_hi & 0xFF0000) >> 16;mac_addr[1] = (mac_hi & 0xFF00) >> 8;mac_addr[2] = mac_hi & 0xFF;mac_addr[3] = (mac_lo & 0xFF0000) >> 16;mac_addr[4] = (mac_lo & 0xFF00) >> 8;mac_addr[5] = mac_lo & 0xFF;if (!getenv("eth1addr")) {if (is_valid_ether_addr(mac_addr))eth_setenv_enetaddr("eth1addr", mac_addr);}ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);ctrl_val |= 0x22;writel(ctrl_val, (*ctrl)->control_core_control_io1);ret = cpsw_register(&cpsw_data);if (ret < 0)printf("Error %d registering CPSW switch\n", ret);return ret;+} +#endif
+#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{
setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);return 0;+} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000..2294abe --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/*
- Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
- Author: Felipe Balbi balbi@ti.com
- Based on board/ti/dra7xx/evm.c
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_
+#include <asm/arch/mux_dra7xx.h>
+const struct pad_conf_entry core_padconf_array_essential[] = {
{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */{RGMII0_TXC, (M0) },{RGMII0_TXCTL, (M0) },{RGMII0_TXD3, (M0) },{RGMII0_TXD2, (M0) },{RGMII0_TXD1, (M0) },{RGMII0_TXD0, (M0) },{RGMII0_RXC, (IEN | M0) },{RGMII0_RXCTL, (IEN | M0) },{RGMII0_RXD3, (IEN | M0) },{RGMII0_RXD2, (IEN | M0) },{RGMII0_RXD1, (IEN | M0) },{RGMII0_RXD0, (IEN | M0) },{USB1_DRVVBUS, (M0 | FSC) },{SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */+}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000..872ab63 --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000..2009f5a --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,89 @@ +/*
- (C) Copyright 2014
- Texas Instruments Incorporated.
- Felipe Balbi balbi@ti.com
- Configuration settings for the TI Beagle x15 board.
- See ti_omap5_common.h for omap5 common settings.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H
+#define CONFIG_AM57XX
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_CMD_SAVEENV
+#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"+#include <configs/ti_omap5_common.h>
+/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART
+/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST
+/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)+#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index de96d7d..c47651d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -117,6 +117,8 @@ "setenv fdtfile dra7-evm.dtb; fi;" \ "if test $board_name = dra72x; then " \ "setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \-- 2.1.0.GIT
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Thu, Nov 06, 2014 at 08:35:41AM -0600, menon.nishanth@gmail.com wrote:
On Thu, Nov 6, 2014 at 8:28 AM, Felipe Balbi balbi@ti.com wrote:
This is the bare minimum support for Beagle x15 into u-boot. There is still quite some work in order to get this in good shape, but it's a start.
Sorry, I should have commented earlier :)
we could expand this a little more here? How about: BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to:http://www.elinux.org/Beagleboard:BeagleBoard-X15
ofcourse - the wiki is yet to be built up..
will do, it has been a while since this stopped being "bare minimum" anyway. It's actually pretty complete from u-boot's point of view.
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com ---
changes since v1: new commit log
arch/arm/cpu/armv7/omap5/Kconfig | 4 + board/ti/beagle_x15/Kconfig | 12 ++ board/ti/beagle_x15/Makefile | 8 + board/ti/beagle_x15/board.c | 328 ++++++++++++++++++++++++++++++++++++++ board/ti/beagle_x15/mux_data.h | 55 +++++++ configs/beagle_x15_defconfig | 5 + include/configs/beagle_x15.h | 89 +++++++++++ include/configs/ti_omap5_common.h | 2 + 8 files changed, 503 insertions(+) create mode 100644 board/ti/beagle_x15/Kconfig create mode 100644 board/ti/beagle_x15/Makefile create mode 100644 board/ti/beagle_x15/board.c create mode 100644 board/ti/beagle_x15/mux_data.h create mode 100644 configs/beagle_x15_defconfig create mode 100644 include/configs/beagle_x15.h
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 129982c..aca862d 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX"
+config TARGET_BEAGLE_X15 + bool "BeagleBoard X15" + endchoice
config SYS_SOC @@ -20,5 +23,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig"
endif diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000..a305ff1 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15 + +config SYS_BOARD + default "beagle_x15" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "beagle_x15" + +endif diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000..5cd6873 --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000..5cafc87 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi balbi@ti.com + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <palmas.h> +#include <sata.h> +#include <usb.h> +#include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sata.h> +#include <asm/arch/gpio.h> +#include <environment.h> + +#include "mux_data.h" + +#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: BeagleBoard x15\n" +}; + +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { + .dmm_lisa_map_3 = 0x80740300, + .is_ma_present = 0x1 +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &beagle_x15_lisa_regs; +} + +static const struct emif_regs beagle_x15_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851B32, /* dont know what to do about this */ + .sdram_config = 0x61851B32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCEEF266B, + .sdram_tim2 = 0x328F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050001, /* not sure where in gel file */ + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0E24400A, /* not sure what to do about this */ + .emif_ddr_phy_ctlr_1 = 0x0E24400A, /* based on non hw level enabled */ + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, /* not sure wherein gel file */ + .emif_ddr_ext_phy_ctrl_2 = 0x00740074, + .emif_ddr_ext_phy_ctrl_3 = 0x00780078, + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, /* based on non hw level enabled */ + .emif_rd_wr_lvl_ctl = 0x00000000, /* not sure where based in gel file */ + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + *regs = &beagle_x15_ddr3_532mhz_emif_regs; +} + +static const u32 beagle_x15_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, // 6 + + + 0x00360036, // 7 + 0x00340034, // 8 + 0x00360036, // 9 + 0x00350035, // 10 + 0x00350035, // 11 + + 0x01ff01ff, // 12 + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + + 0x00430043, + 0x003e003e, + 0x004a004a, + 0x00470047, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{ + *regs = beagle_x15_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_ddr3_ext_phy_ctrl_const_regs); +} + +struct vcores_data beagle_x15_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS45, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS6, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, +}; + +void hw_data_init(void) +{ + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &beagle_x15_volts; + *ctrl = &dra7xx_ctrl; +} + +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int board_late_init(void) +{ + init_sata(0); + /* + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds + * This is the POWERHOLD-in-Low behavior. + */ + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif + +#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, + OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M); + + return 0; +} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000..2294abe --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi balbi@ti.com + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_ + +#include <asm/arch/mux_dra7xx.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, + {USB1_DRVVBUS, (M0 | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ +}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000..872ab63 --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000..2009f5a --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated. + * Felipe Balbi balbi@ti.com + * + * Configuration settings for the TI Beagle x15 board. + * See ti_omap5_common.h for omap5 common settings. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H + +#define CONFIG_AM57XX + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" + +#define CONFIG_CMD_SAVEENV + +#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include <configs/ti_omap5_common.h> + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB + +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index de96d7d..c47651d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -117,6 +117,8 @@ "setenv fdtfile dra7-evm.dtb; fi;" \ "if test $board_name = dra72x; then " \ "setenv fdtfile dra72-evm.dtb; fi;" \ + "if test $board_name = beagle_x15; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
On Thu, Nov 6, 2014 at 8:44 AM, Felipe Balbi balbi@ti.com wrote:
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com
awesome - looks good to me. Thanks for doing this.
changes since v1: new commit log
arch/arm/cpu/armv7/omap5/Kconfig | 4 + board/ti/beagle_x15/Kconfig | 12 ++ board/ti/beagle_x15/Makefile | 8 + board/ti/beagle_x15/board.c | 328 ++++++++++++++++++++++++++++++++++++++ board/ti/beagle_x15/mux_data.h | 55 +++++++ configs/beagle_x15_defconfig | 5 + include/configs/beagle_x15.h | 89 +++++++++++ include/configs/ti_omap5_common.h | 2 + 8 files changed, 503 insertions(+) create mode 100644 board/ti/beagle_x15/Kconfig create mode 100644 board/ti/beagle_x15/Makefile create mode 100644 board/ti/beagle_x15/board.c create mode 100644 board/ti/beagle_x15/mux_data.h create mode 100644 configs/beagle_x15_defconfig create mode 100644 include/configs/beagle_x15.h
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 129982c..aca862d 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX"
+config TARGET_BEAGLE_X15
bool "BeagleBoard X15"endchoice
config SYS_SOC @@ -20,5 +23,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig"
endif diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000..a305ff1 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15
+config SYS_BOARD
default "beagle_x15"+config SYS_VENDOR
default "ti"+config SYS_CONFIG_NAME
default "beagle_x15"+endif diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000..5cd6873 --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000..5cafc87 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,328 @@ +/*
- Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
- Author: Felipe Balbi balbi@ti.com
- Based on board/ti/dra7xx/evm.c
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <palmas.h> +#include <sata.h> +#include <usb.h> +#include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sata.h> +#include <asm/arch/gpio.h> +#include <environment.h>
+#include "mux_data.h"
+#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif
+DECLARE_GLOBAL_DATA_PTR;
+const struct omap_sysinfo sysinfo = {
"Board: BeagleBoard x15\n"+};
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
.dmm_lisa_map_3 = 0x80740300,.is_ma_present = 0x1+};
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{
*dmm_lisa_regs = &beagle_x15_lisa_regs;+}
+static const struct emif_regs beagle_x15_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851B32, /* dont know what to do about this */.sdram_config = 0x61851B32,.sdram_config2 = 0x00000000,.ref_ctrl = 0x00001035,.sdram_tim1 = 0xCEEF266B,.sdram_tim2 = 0x328F7FDA,.sdram_tim3 = 0x027F88A8,.read_idle_ctrl = 0x00050001, /* not sure where in gel file */.zq_config = 0x0007190B,.temp_alert_config = 0x00000000,.emif_ddr_phy_ctlr_1_init = 0x0E24400A, /* not sure what to do about this */.emif_ddr_phy_ctlr_1 = 0x0E24400A, /* based on non hw level enabled */.emif_ddr_ext_phy_ctrl_1 = 0x10040100, /* not sure wherein gel file */.emif_ddr_ext_phy_ctrl_2 = 0x00740074,.emif_ddr_ext_phy_ctrl_3 = 0x00780078,.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,.emif_rd_wr_lvl_rmp_win = 0x00000000,.emif_rd_wr_lvl_rmp_ctl = 0x00000000, /* based on non hw level enabled */.emif_rd_wr_lvl_ctl = 0x00000000, /* not sure where based in gel file */.emif_rd_wr_exec_thresh = 0x00000305+};
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{
*regs = &beagle_x15_ddr3_532mhz_emif_regs;+}
+static const u32 beagle_x15_ddr3_ext_phy_ctrl_const_regs[] = {
0x00800080, // 60x00360036, // 70x00340034, // 80x00360036, // 90x00350035, // 100x00350035, // 110x01ff01ff, // 120x01ff01ff,0x01ff01ff,0x01ff01ff,0x01ff01ff,0x00430043,0x003e003e,0x004a004a,0x00470047,0x00400040,0x00000000,0x00600020,0x40010080,0x08102040,0x00400040,0x00400040,0x00400040,0x00400040,0x00400040+};
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{
*regs = beagle_x15_ddr3_ext_phy_ctrl_const_regs;*size = ARRAY_SIZE(beagle_x15_ddr3_ext_phy_ctrl_const_regs);+}
+struct vcores_data beagle_x15_volts = {
.mpu.value = VDD_MPU_DRA752,.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,.mpu.addr = TPS659038_REG_ADDR_SMPS12,.mpu.pmic = &tps659038,.eve.value = VDD_EVE_DRA752,.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,.eve.addr = TPS659038_REG_ADDR_SMPS45,.eve.pmic = &tps659038,.gpu.value = VDD_GPU_DRA752,.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,.gpu.addr = TPS659038_REG_ADDR_SMPS45,.gpu.pmic = &tps659038,.core.value = VDD_CORE_DRA752,.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,.core.addr = TPS659038_REG_ADDR_SMPS6,.core.pmic = &tps659038,.iva.value = VDD_IVA_DRA752,.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,.iva.addr = TPS659038_REG_ADDR_SMPS45,.iva.pmic = &tps659038,+};
+void hw_data_init(void) +{
*prcm = &dra7xx_prcm;*dplls_data = &dra7xx_dplls;*omap_vcores = &beagle_x15_volts;*ctrl = &dra7xx_ctrl;+}
+int board_init(void) +{
gpmc_init();gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);return 0;+}
+int board_late_init(void) +{
init_sata(0);/** DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds* This is the POWERHOLD-in-Low behavior.*/palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);return 0;+}
+static void do_set_mux32(u32 base,
struct pad_conf_entry const *array, int size)+{
int i;struct pad_conf_entry *pad = (struct pad_conf_entry *)array;for (i = 0; i < size; i++, pad++)writel(pad->val, base + pad->offset);+}
+void set_muxconf_regs_essential(void) +{
do_set_mux32((*ctrl)->control_padconf_core_base,core_padconf_array_essential,sizeof(core_padconf_array_essential) /sizeof(struct pad_conf_entry));+}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{
omap_mmc_init(0, 0, 0, -1, -1);omap_mmc_init(1, 0, 0, -1, -1);return 0;+} +#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{
/* break into full u-boot on 'c' */if (serial_tstc() && serial_getc() == 'c')return 1;+#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();env_relocate_spec();if (getenv_yesno("boot_os") != 1)return 1;+#endif
return 0;+} +#endif
+#ifdef CONFIG_DRIVER_TI_CPSW
+/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+static void cpsw_control(int enabled) +{
/* VTP can be added here */+}
+static struct cpsw_slave_data cpsw_slaves[] = {
{.slave_reg_ofs = 0x208,.sliver_reg_ofs = 0xd80,.phy_addr = 1,},{.slave_reg_ofs = 0x308,.sliver_reg_ofs = 0xdc0,.phy_addr = 2,},+};
+static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,.cpsw_base = CPSW_BASE,.mdio_div = 0xff,.channels = 8,.cpdma_reg_ofs = 0x800,.slaves = 1,.slave_data = cpsw_slaves,.ale_reg_ofs = 0xd00,.ale_entries = 1024,.host_port_reg_ofs = 0x108,.hw_stats_reg_ofs = 0x900,.bd_ram_ofs = 0x2000,.mac_control = (1 << 5),.control = cpsw_control,.host_port_num = 0,.version = CPSW_CTRL_VERSION_2,+};
+int board_eth_init(bd_t *bis) +{
int ret;uint8_t mac_addr[6];uint32_t mac_hi, mac_lo;uint32_t ctrl_val;/* try reading mac address from efuse */mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);mac_addr[0] = (mac_hi & 0xFF0000) >> 16;mac_addr[1] = (mac_hi & 0xFF00) >> 8;mac_addr[2] = mac_hi & 0xFF;mac_addr[3] = (mac_lo & 0xFF0000) >> 16;mac_addr[4] = (mac_lo & 0xFF00) >> 8;mac_addr[5] = mac_lo & 0xFF;if (!getenv("ethaddr")) {printf("<ethaddr> not set. Validating first E-fuse MAC\n");if (is_valid_ether_addr(mac_addr))eth_setenv_enetaddr("ethaddr", mac_addr);}mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);mac_addr[0] = (mac_hi & 0xFF0000) >> 16;mac_addr[1] = (mac_hi & 0xFF00) >> 8;mac_addr[2] = mac_hi & 0xFF;mac_addr[3] = (mac_lo & 0xFF0000) >> 16;mac_addr[4] = (mac_lo & 0xFF00) >> 8;mac_addr[5] = mac_lo & 0xFF;if (!getenv("eth1addr")) {if (is_valid_ether_addr(mac_addr))eth_setenv_enetaddr("eth1addr", mac_addr);}ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);ctrl_val |= 0x22;writel(ctrl_val, (*ctrl)->control_core_control_io1);ret = cpsw_register(&cpsw_data);if (ret < 0)printf("Error %d registering CPSW switch\n", ret);return ret;+} +#endif
+#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{
setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);return 0;+} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000..2294abe --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/*
- Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
- Author: Felipe Balbi balbi@ti.com
- Based on board/ti/dra7xx/evm.c
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_
+#include <asm/arch/mux_dra7xx.h>
+const struct pad_conf_entry core_padconf_array_essential[] = {
{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */{RGMII0_TXC, (M0) },{RGMII0_TXCTL, (M0) },{RGMII0_TXD3, (M0) },{RGMII0_TXD2, (M0) },{RGMII0_TXD1, (M0) },{RGMII0_TXD0, (M0) },{RGMII0_RXC, (IEN | M0) },{RGMII0_RXCTL, (IEN | M0) },{RGMII0_RXD3, (IEN | M0) },{RGMII0_RXD2, (IEN | M0) },{RGMII0_RXD1, (IEN | M0) },{RGMII0_RXD0, (IEN | M0) },{USB1_DRVVBUS, (M0 | FSC) },{SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */+}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000..872ab63 --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000..2009f5a --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,89 @@ +/*
- (C) Copyright 2014
- Texas Instruments Incorporated.
- Felipe Balbi balbi@ti.com
- Configuration settings for the TI Beagle x15 board.
- See ti_omap5_common.h for omap5 common settings.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H
+#define CONFIG_AM57XX
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_CMD_SAVEENV
+#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"+#include <configs/ti_omap5_common.h>
+/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART
+/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST
+/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)+#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index de96d7d..c47651d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -117,6 +117,8 @@ "setenv fdtfile dra7-evm.dtb; fi;" \ "if test $board_name = dra72x; then " \ "setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \-- 2.1.0.GIT
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Thu, Nov 06, 2014 at 08:44:27AM -0600, Felipe Balbi wrote:
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com
[snip]
+static const struct emif_regs beagle_x15_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851B32, /* dont know what to do about this */
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCEEF266B,
- .sdram_tim2 = 0x328F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001, /* not sure where in gel file */
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A, /* not sure what to do about this */
- .emif_ddr_phy_ctlr_1 = 0x0E24400A, /* based on non hw level enabled */
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100, /* not sure wherein gel file */
- .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
- .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
- .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
- .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000, /* based on non hw level enabled */
- .emif_rd_wr_lvl_ctl = 0x00000000, /* not sure where based in gel file */
- .emif_rd_wr_exec_thresh = 0x00000305
Lets either get the timing info right or comment that we expect to need to tweak these values again later based on production HW or something.
+static const u32 beagle_x15_ddr3_ext_phy_ctrl_const_regs[] = {
- 0x00800080, // 6
- 0x00360036, // 7
- 0x00340034, // 8
- 0x00360036, // 9
- 0x00350035, // 10
- 0x00350035, // 11
- 0x01ff01ff, // 12
// isn't allowed and what're you counting? :)
[snip]
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
Shouldn't be needed, should be set by a common header already.
Hi,
On Mon, Nov 10, 2014 at 01:47:48PM -0500, Tom Rini wrote:
On Thu, Nov 06, 2014 at 08:44:27AM -0600, Felipe Balbi wrote:
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com
[snip]
+static const struct emif_regs beagle_x15_ddr3_532mhz_emif_regs = {
- .sdram_config_init = 0x61851B32, /* dont know what to do about this */
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCEEF266B,
- .sdram_tim2 = 0x328F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050001, /* not sure where in gel file */
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0E24400A, /* not sure what to do about this */
- .emif_ddr_phy_ctlr_1 = 0x0E24400A, /* based on non hw level enabled */
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100, /* not sure wherein gel file */
- .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
- .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
- .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
- .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000, /* based on non hw level enabled */
- .emif_rd_wr_lvl_ctl = 0x00000000, /* not sure where based in gel file */
- .emif_rd_wr_exec_thresh = 0x00000305
Lets either get the timing info right or comment that we expect to need to tweak these values again later based on production HW or something.
alright, I'll fix that. Apparently we have final timings now which I got over the weekend, I'll try those out.
+static const u32 beagle_x15_ddr3_ext_phy_ctrl_const_regs[] = {
- 0x00800080, // 6
- 0x00360036, // 7
- 0x00340034, // 8
- 0x00360036, // 9
- 0x00350035, // 10
- 0x00350035, // 11
- 0x01ff01ff, // 12
// isn't allowed and what're you counting? :)
heh, forgot to drop those. Now dropped.
[snip]
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
Shouldn't be needed, should be set by a common header already.
dropped.
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com ---
Changes since v2: - new DDR timings for EMIF2 - removed some pointless comments - dropped CONFIG_SYS_SDRAM_BASE define
Changes since v1: - new commit log
arch/arm/cpu/armv7/omap5/Kconfig | 4 + board/ti/beagle_x15/Kconfig | 12 ++ board/ti/beagle_x15/Makefile | 8 + board/ti/beagle_x15/board.c | 395 ++++++++++++++++++++++++++++++++++++++ board/ti/beagle_x15/mux_data.h | 55 ++++++ configs/beagle_x15_defconfig | 5 + include/configs/beagle_x15.h | 88 +++++++++ include/configs/ti_omap5_common.h | 2 + 8 files changed, 569 insertions(+) create mode 100644 board/ti/beagle_x15/Kconfig create mode 100644 board/ti/beagle_x15/Makefile create mode 100644 board/ti/beagle_x15/board.c create mode 100644 board/ti/beagle_x15/mux_data.h create mode 100644 configs/beagle_x15_defconfig create mode 100644 include/configs/beagle_x15.h
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 129982c..aca862d 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX"
+config TARGET_BEAGLE_X15 + bool "BeagleBoard X15" + endchoice
config SYS_SOC @@ -20,5 +23,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig"
endif diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000..a305ff1 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15 + +config SYS_BOARD + default "beagle_x15" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "beagle_x15" + +endif diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000..5cd6873 --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000..db96e34 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi balbi@ti.com + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <palmas.h> +#include <sata.h> +#include <usb.h> +#include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sata.h> +#include <asm/arch/gpio.h> +#include <environment.h> + +#include "mux_data.h" + +#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: BeagleBoard x15\n" +}; + +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { + .dmm_lisa_map_3 = 0x80740300, + .is_ma_present = 0x1 +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &beagle_x15_lisa_regs; +} + +static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050001, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0e24400a, + .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00740074, + .emif_ddr_ext_phy_ctrl_3 = 0x00780078, + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, + 0x00360036, + 0x00340034, + 0x00360036, + 0x00350035, + 0x00350035, + + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + + 0x00430043, + 0x003e003e, + 0x004a004a, + 0x00470047, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050001, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0e24400a, + .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00820082, + .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, + .emif_ddr_ext_phy_ctrl_4 = 0x00800080, + .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x00800080, + 0x00370037, + 0x00390039, + 0x00360036, + 0x00370037, + 0x00350035, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x00540054, + 0x00540054, + 0x004e004e, + 0x004c004c, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40010080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + switch (emif_nr) { + case 1: + *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; + break; + case 2: + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; + break; + } +} + +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{ + switch (emif_nr) { + case 1: + *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); + break; + case 2: + *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); + break; + } +} + +struct vcores_data beagle_x15_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS45, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS6, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, +}; + +void hw_data_init(void) +{ + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &beagle_x15_volts; + *ctrl = &dra7xx_ctrl; +} + +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int board_late_init(void) +{ + init_sata(0); + /* + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds + * This is the POWERHOLD-in-Low behavior. + */ + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); + return 0; +} + +static void do_set_mux32(u32 base, + struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif + +#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, + OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M); + + return 0; +} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000..2294abe --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi balbi@ti.com + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_ + +#include <asm/arch/mux_dra7xx.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ + {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ + {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ + {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ + {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ + {RGMII0_TXC, (M0) }, + {RGMII0_TXCTL, (M0) }, + {RGMII0_TXD3, (M0) }, + {RGMII0_TXD2, (M0) }, + {RGMII0_TXD1, (M0) }, + {RGMII0_TXD0, (M0) }, + {RGMII0_RXC, (IEN | M0) }, + {RGMII0_RXCTL, (IEN | M0) }, + {RGMII0_RXD3, (IEN | M0) }, + {RGMII0_RXD2, (IEN | M0) }, + {RGMII0_RXD1, (IEN | M0) }, + {RGMII0_RXD0, (IEN | M0) }, + {USB1_DRVVBUS, (M0 | FSC) }, + {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ +}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000..872ab63 --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000..cc36330 --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated. + * Felipe Balbi balbi@ti.com + * + * Configuration settings for the TI Beagle x15 board. + * See ti_omap5_common.h for omap5 common settings. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H + +#define CONFIG_AM57XX + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" + +#define CONFIG_CMD_SAVEENV + +#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include <configs/ti_omap5_common.h> + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB + +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index de96d7d..c47651d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -117,6 +117,8 @@ "setenv fdtfile dra7-evm.dtb; fi;" \ "if test $board_name = dra72x; then " \ "setenv fdtfile dra72-evm.dtb; fi;" \ + "if test $board_name = beagle_x15; then " \ + "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
On Mon, Nov 10, 2014 at 02:02:44PM -0600, Felipe Balbi wrote:
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Mon, Nov 10, 2014 at 02:02:44PM -0600, Felipe Balbi wrote:
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
On Thu, Nov 06, 2014 at 08:28:42AM -0600, Felipe Balbi wrote:
Out of all OMAP5-like boards, only one of them needs CONFIG_MISC_INIT_R, so it's best to enable that for that particular board only, instead of enabling for all boards unconditionally.
Signed-off-by: Felipe Balbi balbi@ti.com
Reviewed-by: Tom Rini trini@ti.com
On Thu, Nov 06, 2014 at 08:28:42AM -0600, Felipe Balbi wrote:
Out of all OMAP5-like boards, only one of them needs CONFIG_MISC_INIT_R, so it's best to enable that for that particular board only, instead of enabling for all boards unconditionally.
Signed-off-by: Felipe Balbi balbi@ti.com Reviewed-by: Tom Rini trini@ti.com
Applied to u-boot-ti/master, thanks!
participants (3)
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Felipe Balbi -
menon.nishanth＠gmail.com -
Tom Rini