The following commit removed the code that set odt_rd_cfg and odt_wr_cfg. With out this code P2020DS board will not boot:

commit 712cf7ab0b58e51a69e339397457d3591b6b650e Author: York Sun yorksun@freescale.com Date: Mon Oct 3 09:19:53 2011 -0700

powerpc/mpc8xxx: Merge entries in DDR speed table

Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/p2020ds/ddr.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index c43f874..59034f9 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -57,6 +57,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; + int i;

if (ctrl_num) { printf("Wrong parameter for controller number %d", ctrl_num); @@ -65,6 +66,17 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (!pdimm->n_ranks) return;

+ /* + * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + pbsp = dimm0;

/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr