Add the latest version of the DT files from the Linux kernel.

Signed-off-by: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/dts/armada-8020.dtsi | 56 ++++++++ arch/arm/dts/armada-8040-db.dts | 150 +++++++++++++++++++++ arch/arm/dts/armada-8040.dtsi | 56 ++++++++ arch/arm/dts/armada-cp110-slave.dtsi | 249 +++++++++++++++++++++++++++++++++++ 4 files changed, 511 insertions(+) create mode 100644 arch/arm/dts/armada-8020.dtsi create mode 100644 arch/arm/dts/armada-8040-db.dts create mode 100644 arch/arm/dts/armada-8040.dtsi create mode 100644 arch/arm/dts/armada-cp110-slave.dtsi

diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi new file mode 100644 index 0000000..048e5cf --- /dev/null +++ b/arch/arm/dts/armada-8020.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and + * two CP110. + */ + +#include "armada-ap806-dual.dtsi" +#include "armada-cp110-master.dtsi" +#include "armada-cp110-slave.dtsi" + +/ { + model = "Marvell Armada 8020"; + compatible = "marvell,armada8020", "marvell,armada-ap806-dual", + "marvell,armada-ap806"; +}; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts new file mode 100644 index 0000000..6e6f182 --- /dev/null +++ b/arch/arm/dts/armada-8040-db.dts @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for Marvell Armada 8040 Development board platform + */ + +#include "armada-8040.dtsi" + +/ { + model = "Marvell Armada 8040 DB board"; + compatible = "marvell,armada8040-db", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x200000 0xce0000>; + }; + }; + }; +}; + +/* Accessible over the mini-USB CON9 connector on the main board */ +&uart0 { + status = "okay"; +}; + + +/* CON5 on CP0 expansion */ +&cpm_pcie2 { + status = "okay"; +}; + +&cpm_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +/* CON4 on CP0 expansion */ +&cpm_sata0 { + status = "okay"; +}; + +/* CON9 on CP0 expansion */ +&cpm_usb3_0 { + status = "okay"; +}; + +/* CON10 on CP0 expansion */ +&cpm_usb3_1 { + status = "okay"; +}; + +/* CON5 on CP1 expansion */ +&cps_pcie2 { + status = "okay"; +}; + +&cps_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +/* CON4 on CP1 expansion */ +&cps_sata0 { + status = "okay"; +}; + +/* CON9 on CP1 expansion */ +&cps_usb3_0 { + status = "okay"; +}; + +/* CON10 on CP1 expansion */ +&cps_usb3_1 { + status = "okay"; +}; diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi new file mode 100644 index 0000000..9c1b28c --- /dev/null +++ b/arch/arm/dts/armada-8040.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and + * two CP110. + */ + +#include "armada-ap806-quad.dtsi" +#include "armada-cp110-master.dtsi" +#include "armada-cp110-slave.dtsi" + +/ { + model = "Marvell Armada 8040"; + compatible = "marvell,armada8040", "marvell,armada-ap806-quad", + "marvell,armada-ap806"; +}; diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi new file mode 100644 index 0000000..842fb33 --- /dev/null +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for Marvell Armada CP110 Slave. + */ + +/ { + cp110-slave { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + config-space { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0xf4000000 0x2000000>; + + cps_syscon0: system-controller@440000 { + compatible = "marvell,cp110-system-controller0", + "syscon"; + reg = <0x440000 0x1000>; + #clock-cells = <2>; + core-clock-output-names = + "cps-apll", "cps-ppv2-core", "cps-eip", + "cps-core", "cps-nand-core"; + gate-clock-output-names = + "cps-audio", "cps-communit", "cps-nand", + "cps-ppv2", "cps-sdio", "cps-mg-domain", + "cps-mg-core", "cps-xor1", "cps-xor0", + "cps-gop-dp", "none", "cps-pcie_x10", + "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", + "cps-sata", "cps-sata-usb", "cps-main", + "cps-sd-mmc", "none", "none", + "cps-slow-io", "cps-usb3h0", "cps-usb3h1", + "cps-usb3dev", "cps-eip150", "cps-eip197"; + }; + + cps_sata0: sata@540000 { + compatible = "marvell,armada-8k-ahci"; + reg = <0x540000 0x30000>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 15>; + status = "disabled"; + }; + + cps_usb3_0: usb3@500000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x500000 0x4000>; + dma-coherent; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 22>; + status = "disabled"; + }; + + cps_usb3_1: usb3@510000 { + compatible = "marvell,armada-8k-xhci", + "generic-xhci"; + reg = <0x510000 0x4000>; + dma-coherent; + interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 23>; + status = "disabled"; + }; + + cps_xor0: xor@6a0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6a0000 0x1000>, + <0x6b0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clocks = <&cps_syscon0 1 8>; + }; + + cps_xor1: xor@6c0000 { + compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; + reg = <0x6c0000 0x1000>, + <0x6d0000 0x1000>; + dma-coherent; + msi-parent = <&gic_v2m0>; + clocks = <&cps_syscon0 1 7>; + }; + + cps_spi0: spi@700600 { + compatible = "marvell,armada-380-spi"; + reg = <0x700600 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + cell-index = <1>; + clocks = <&cps_syscon0 0 3>; + status = "disabled"; + }; + + cps_spi1: spi@700680 { + compatible = "marvell,armada-380-spi"; + reg = <0x700680 0x50>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <2>; + clocks = <&cps_syscon0 1 21>; + status = "disabled"; + }; + + cps_i2c0: i2c@701000 { + compatible = "marvell,mv78230-i2c"; + reg = <0x701000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 21>; + status = "disabled"; + }; + + cps_i2c1: i2c@701100 { + compatible = "marvell,mv78230-i2c"; + reg = <0x701100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cps_syscon0 1 21>; + status = "disabled"; + }; + }; + + cps_pcie0: pcie@f4600000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf4600000 0 0x10000>, + <0 0xfaf00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + num-lanes = <1>; + clocks = <&cps_syscon0 1 13>; + status = "disabled"; + }; + + cps_pcie1: pcie@f4620000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf4620000 0 0x10000>, + <0 0xfbf00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes = <1>; + clocks = <&cps_syscon0 1 11>; + status = "disabled"; + }; + + cps_pcie2: pcie@f4640000 { + compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; + reg = <0 0xf4640000 0 0x10000>, + <0 0xfcf00000 0 0x80000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + msi-parent = <&gic_v2m0>; + + bus-range = <0 0xff>; + ranges = + /* downstream I/O */ + <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 + /* non-prefetchable memory */ + 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; + + num-lanes = <1>; + clocks = <&cps_syscon0 1 12>; + status = "disabled"; + }; + }; +};

To enable access to the slave CP its memory needs to be added to the MMU memory map.

Signed-off-by: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/mach-mvebu/armada8k/cpu.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 036430c..f8e69d6 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -39,7 +39,7 @@ static struct mm_region mvebu_mem_map[] = { PTE_BLOCK_NON_SHARE }, { - /* SRAM, MMIO regions - CP110 region */ + /* SRAM, MMIO regions - CP110 master region */ .phys = 0xf2000000UL, .virt = 0xf2000000UL, .size = 0x02000000UL, /* 32MiB internal registers */ @@ -47,6 +47,14 @@ static struct mm_region mvebu_mem_map[] = { PTE_BLOCK_NON_SHARE }, { + /* SRAM, MMIO regions - CP110 slave region */ + .phys = 0xf4000000UL, + .virt = 0xf4000000UL, + .size = 0x02000000UL, /* 32MiB internal registers */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + { /* List terminator */ 0, }

Since the cp110 slave also has comphy DT nodes, the names need to be renamed to avoid a name clash. Lets use the common naming scheme: "cpm_xxx" for master and "cps_xxx" for slave.

Signed-off-by: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/dts/armada-7040-db.dts | 6 +++--- arch/arm/dts/armada-cp110-master.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 7d0059a..b8fe5a9 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -152,7 +152,7 @@ status = "okay"; };

-&comphy_cp110 { +&cpm_comphy { phy0 { phy-type = <PHY_TYPE_SGMII2>; phy-speed = <PHY_SPEED_3_125G>; @@ -184,10 +184,10 @@ }; };

-&utmi0 { +&cpm_utmi0 { status = "okay"; };

-&utmi1 { +&cpm_utmi1 { status = "okay"; }; diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 7da98bf..422d754 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -149,7 +149,7 @@ status = "disabled"; };

- comphy_cp110: comphy@441000 { + cpm_comphy: comphy@441000 { compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; reg = <0x441000 0x8>, <0x120000 0x8>; @@ -157,7 +157,7 @@ max-lanes = <6>; };

- utmi0: utmi@580000 { + cpm_utmi0: utmi@580000 { compatible = "marvell,mvebu-utmi-2.6.0"; reg = <0x580000 0x1000>, /* utmi-unit */ <0x440420 0x4>, /* usb-cfg */ @@ -166,7 +166,7 @@ status = "disabled"; };

- utmi1: utmi@581000 { + cpm_utmi1: utmi@581000 { compatible = "marvell,mvebu-utmi-2.6.0"; reg = <0x581000 0x1000>, /* utmi-unit */ <0x440420 0x4>, /* usb-cfg */

This patch adds the COMPHY device tree configuration to the DT file for the Marvell DB-88F8040 devel board.

Signed-off-by: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/dts/armada-8040-db.dts | 84 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+)

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 6e6f182..4978092 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -148,3 +148,87 @@ &cps_usb3_1 { status = "okay"; }; + +&cpm_comphy { + /* + * Serdes Configuration: + * Lane 0: SGMII2 + * Lane 1: USB3_HOST0 + * Lane 2: KR (10G) + * Lane 3: SATA1 + * Lane 4: USB3_HOST1 + * Lane 5: PEX2x1 + */ + phy0 { + phy-type = <PHY_TYPE_SGMII2>; + phy-speed = <PHY_SPEED_3_125G>; + }; + + phy1 { + phy-type = <PHY_TYPE_USB3_HOST0>; + }; + + phy2 { + phy-type = <PHY_TYPE_KR>; + }; + + phy3 { + phy-type = <PHY_TYPE_SATA1>; + }; + + phy4 { + phy-type = <PHY_TYPE_USB3_HOST1>; + }; + + phy5 { + phy-type = <PHY_TYPE_PEX2>; + }; +}; + +&cps_comphy { + /* + * Serdes Configuration: + * Lane 0: SGMII2 + * Lane 1: USB3_HOST0 + * Lane 2: KR (10G) + * Lane 3: SATA1 + * Lane 4: Unconnected + * Lane 5: PEX2x1 + */ + phy0 { + phy-type = <PHY_TYPE_SGMII2>; + phy-speed = <PHY_SPEED_3_125G>; + }; + + phy1 { + phy-type = <PHY_TYPE_USB3_HOST0>; + }; + + phy2 { + phy-type = <PHY_TYPE_KR>; + }; + + phy3 { + phy-type = <PHY_TYPE_SATA1>; + }; + + phy4 { + phy-type = <PHY_TYPE_UNCONNECTED>; + }; + + phy5 { + phy-type = <PHY_TYPE_PEX2>; + }; +}; + +&cpm_utmi0 { + status = "okay"; +}; + +&cpm_utmi1 { + status = "okay"; +}; + +&cps_utmi0 { + status = "okay"; +};

The Armada8k implements 2 CPs (communication processors) and the 2nd CP also is equipped with a COMPHY controller. This patch now loops over all enabled MISC devices (CP110) enabled in the DT to initialize all CPs.

Signed-off-by: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/mach-mvebu/arm64-common.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 7055a81..1fc2ff2 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -109,12 +109,20 @@ int arch_early_init_r(void) { struct udevice *dev; int ret; - - /* Call the comphy code via the MISC uclass driver */ - ret = uclass_get_device(UCLASS_MISC, 0, &dev); - if (ret) { - debug("COMPHY init failed: %d\n", ret); - return -ENODEV; + int i; + + /* + * Loop over all MISC uclass drivers to call the comphy code + * and init all CP110 devices enabled in the DT + */ + i = 0; + while (1) { + /* Call the comphy code via the MISC uclass driver */ + ret = uclass_get_device(UCLASS_MISC, i++, &dev); + + /* We're done, once no further CP110 device is found */ + if (ret) + break; }

/* Cause the SATA device to do its early init */

From: Shadi Ammouri shadi@marvell.com

This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core.

The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support.

Tested on the Marvell DB-88F8040 Armada-8K eval board.

Signed-off-by: Shadi Ammouri shadi@marvell.com Signed-off-by: Yehuda Yitschak yehuday@marvell.com Signed-off-by: Stefan Roese sr@denx.de Cc: Simon Glass sjg@chromium.org Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- drivers/pci/Kconfig | 10 ++ drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_mvebu.c | 415 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 426 insertions(+) create mode 100644 drivers/pci/pcie_dw_mvebu.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index b8376b4..ff2c370 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -33,6 +33,16 @@ config PCI_PNP help Enable PCI memory and I/O space resource allocation and assignment.

+config PCIE_DW_MVEBU + bool "Enable Armada-8K PCIe driver (DesignWare core)" + default n + depends on DM_PCI + depends on ARMADA_8K + help + Say Y here if you want to enable PCIe controller support on + Armada-8K SoCs. The PCIe controller on Armada-8K is based on + DesignWare hardware. + config PCI_SANDBOX bool "Sandbox PCI support" depends on SANDBOX && DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 9583e91..86717a4 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -30,5 +30,6 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o +obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c new file mode 100644 index 0000000..dd5ba34 --- /dev/null +++ b/drivers/pci/pcie_dw_mvebu.c @@ -0,0 +1,415 @@ +/* + * Copyright (C) 2015 Marvell International Ltd. + * + * Copyright (C) 2016 Stefan Roese sr@denx.de + * + * Based on: + * - drivers/pci/pcie_imx.c + * - drivers/pci/pci_mvebu.c + * - drivers/pci/pcie_xilinx.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pci.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* PCI Config space registers */ +#define PCIE_CONFIG_BAR0 0x10 +#define PCIE_LINK_STATUS_REG 0x80 +#define PCIE_LINK_STATUS_SPEED_OFF 16 +#define PCIE_LINK_STATUS_SPEED_MASK 0xf +#define PCIE_LINK_STATUS_WIDTH_OFF 20 +#define PCIE_LINK_STATUS_WIDTH_MASK 0xf + +/* Resizable bar capability registers */ +#define RESIZABLE_BAR_CAP 0x250 +#define RESIZABLE_BAR_CTL0 0x254 +#define RESIZABLE_BAR_CTL1 0x258 + +/* iATU registers */ +#define PCIE_ATU_VIEWPORT 0x900 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31) +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_CR1 0x904 +#define PCIE_ATU_TYPE_MEM (0x0 << 0) +#define PCIE_ATU_TYPE_IO (0x2 << 0) +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_CR2 0x908 +#define PCIE_ATU_ENABLE (0x1 << 31) +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_LOWER_BASE 0x90C +#define PCIE_ATU_UPPER_BASE 0x910 +#define PCIE_ATU_LIMIT 0x914 +#define PCIE_ATU_LOWER_TARGET 0x918 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_UPPER_TARGET 0x91C + +#define PCIE_LINK_CAPABILITY 0x7C +#define PCIE_LINK_CTL_2 0xA0 +#define TARGET_LINK_SPEED_MASK 0xF +#define LINK_SPEED_GEN_1 0x1 +#define LINK_SPEED_GEN_2 0x2 +#define LINK_SPEED_GEN_3 0x3 + +#define PCIE_GEN3_RELATED 0x890 +#define GEN3_EQU_DISABLE (1 << 16) +#define GEN3_ZRXDC_NON_COMP (1 << 0) + +#define PCIE_GEN3_EQU_CTRL 0x8A8 +#define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5) + +#define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4) + +#define PCIE_LINK_UP_TIMEOUT_MS 100 + +#define PCIE_GLOBAL_CONTROL 0x8000 +#define PCIE_APP_LTSSM_EN (1 << 2) +#define PCIE_DEVICE_TYPE_OFFSET (4) +#define PCIE_DEVICE_TYPE_MASK (0xF) +#define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */ +#define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */ +#define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */ + +#define PCIE_GLOBAL_STATUS 0x8008 +#define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1) +#define PCIE_GLB_STS_PHY_LINK_UP (1 << 9) + +#define PCIE_ARCACHE_TRC 0x8050 +#define PCIE_AWCACHE_TRC 0x8054 +#define ARCACHE_SHAREABLE_CACHEABLE 0x3511 +#define AWCACHE_SHAREABLE_CACHEABLE 0x5311 + +#define LINK_SPEED_GEN_1 0x1 +#define LINK_SPEED_GEN_2 0x2 +#define LINK_SPEED_GEN_3 0x3 + +struct pcie_dw_mvebu { + struct pci_controller hose; + void *ctrl_base; + void *cfg_base; + fdt_size_t cfg_size; + int first_busno; +}; + +static int pcie_dw_get_link_speed(void *regs_base) +{ + return ((readl(regs_base + PCIE_LINK_STATUS_REG)) >> + PCIE_LINK_STATUS_SPEED_OFF) & PCIE_LINK_STATUS_SPEED_MASK; +} + +static int pcie_dw_get_link_width(void *regs_base) +{ + return ((readl(regs_base + PCIE_LINK_STATUS_REG)) >> + PCIE_LINK_STATUS_WIDTH_OFF) & PCIE_LINK_STATUS_WIDTH_MASK; +} + +static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, + pci_dev_t d, int where) +{ + uintptr_t va_address; + + /* + * Region #0 is used for Outbound CFG space access. + * Direction = Outbound + * Region Index = 0 + */ + writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT); + + if (PCI_BUS(d) == (pcie->first_busno + 1)) + /* For local bus, change TLP Type field to 4. */ + writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1); + else + /* Otherwise, change TLP Type field to 5. */ + writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1); + + if (PCI_BUS(d) == pcie->first_busno) { + /* Accessing root port configuration space. */ + va_address = (uintptr_t)pcie->ctrl_base; + } else { + writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); + va_address = (uintptr_t)pcie->cfg_base; + } + + va_address += (where & ~0x3); + + return va_address; +} + +static int pcie_dw_addr_valid(pci_dev_t d, int first_busno) +{ + if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) + return 0; + if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) + return 0; + + return 1; +} + +static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct pcie_dw_mvebu *pcie = dev_get_priv(bus); + uintptr_t va_address; + ulong value; + + debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + + if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { + debug("- out of range\n"); + *valuep = pci_get_ff(size); + return 0; + } + + va_address = set_cfg_address(pcie, bdf, offset); + + value = readl(va_address); + + debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); + *valuep = pci_conv_32_to_size(value, offset, size); + + return 0; +} + +static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct pcie_dw_mvebu *pcie = dev_get_priv(bus); + uintptr_t va_address; + ulong old; + + debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); + + if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) { + debug("- out of range\n"); + return 0; + } + + va_address = set_cfg_address(pcie, bdf, offset); + + old = readl(va_address); + value = pci_conv_size_to_32(old, value, offset, size); + writel(value, va_address); + + return 0; +} + +static void pcie_dw_configure(void *regs_base, u32 cap_speed) +{ + u32 reg; + + /* TODO: need to read the serdes speed from the dts + and according to it configure the PCIe gen */ + + /* Set link to GEN 3 */ + reg = readl(regs_base + PCIE_LINK_CTL_2); + reg &= ~TARGET_LINK_SPEED_MASK; + reg |= cap_speed; + writel(reg, regs_base + PCIE_LINK_CTL_2); + + reg = readl(regs_base + PCIE_LINK_CAPABILITY); + reg &= ~TARGET_LINK_SPEED_MASK; + reg |= cap_speed; + writel(reg, regs_base + PCIE_LINK_CAPABILITY); + + reg = readl(regs_base + PCIE_GEN3_EQU_CTRL); + reg |= GEN3_EQU_EVAL_2MS_DISABLE; + writel(reg, regs_base + PCIE_GEN3_EQU_CTRL); +} + +static int is_link_up(void *regs_base) +{ + u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; + u32 reg; + + reg = readl(regs_base + PCIE_GLOBAL_STATUS); + if ((reg & mask) == mask) + return 1; + + return 0; +} + +static int wait_link_up(void *regs_base) +{ + unsigned long timeout; + + timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS; + while (!is_link_up(regs_base)) { + if (get_timer(0) > timeout) + return 0; + }; + + return 1; +} + +static int pcie_dw_mvebu_pcie_link_up(void *regs_base, u32 cap_speed) +{ + u32 reg; + + if (!is_link_up(regs_base)) { + /* Disable LTSSM state machine to enable configuration */ + reg = readl(regs_base + PCIE_GLOBAL_CONTROL); + reg &= ~(PCIE_APP_LTSSM_EN); + writel(reg, regs_base + PCIE_GLOBAL_CONTROL); + } + + reg = readl(regs_base + PCIE_GLOBAL_CONTROL); + reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET); + reg |= (PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET); + writel(reg, regs_base + PCIE_GLOBAL_CONTROL); + + /* Set the PCIe master AXI attributes */ + writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC); + writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC); + + /* DW pre link configurations */ + pcie_dw_configure(regs_base, cap_speed); + + if (!is_link_up(regs_base)) { + /* Configuration done. Start LTSSM */ + reg = readl(regs_base + PCIE_GLOBAL_CONTROL); + reg |= PCIE_APP_LTSSM_EN; + writel(reg, regs_base + PCIE_GLOBAL_CONTROL); + } + + /* Check that link was established */ + if (!wait_link_up(regs_base)) + return 0; + + /* + * Link can be established in Gen 1. still need to wait + * till MAC nagaotiation is completed + */ + udelay(100); + + return 1; +} + +/* + * iATU region setup + */ +static int pcie_dw_regions_setup(struct pcie_dw_mvebu *pcie) +{ + /* + * Region #0 is used for Outbound CFG space access. + * Direction = Outbound + * Region Index = 0 + */ + writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT); + + writel((u32)(uintptr_t)pcie->cfg_base, pcie->ctrl_base + + PCIE_ATU_LOWER_BASE); + writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_BASE); + writel((u32)(uintptr_t)pcie->cfg_base + pcie->cfg_size, + pcie->ctrl_base + PCIE_ATU_LIMIT); + + writel(0, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); + writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_TARGET); + writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1); + writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2); + + return 0; +} + +static void pcie_dw_set_host_bars(void *regs_base) +{ + u32 size = gd->ram_size; + u64 max_size; + u32 reg; + u32 bar0; + + /* Verify the maximal BAR size */ + reg = readl(regs_base + RESIZABLE_BAR_CAP); + max_size = 1ULL << (5 + (reg + (1 << 4))); + + if (size > max_size) { + size = max_size; + printf("Warning: PCIe BARs can't map all DRAM space\n"); + } + + /* Set the BAR base and size towards DDR */ + bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; + bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; + writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); + + reg = ((size >> 20) - 1) << 12; + writel(size, regs_base + RESIZABLE_BAR_CTL0); +} + +static int pcie_dw_mvebu_probe(struct udevice *dev) +{ + struct pcie_dw_mvebu *pcie = dev_get_priv(dev); + + pcie->first_busno = dev->seq; + + /* Don't register host if link is down */ + if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) { + printf("PCIE-%d: Link down\n", dev->seq); + return -ENODEV; + } + + printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq, + pcie_dw_get_link_speed(pcie->ctrl_base), + pcie_dw_get_link_width(pcie->ctrl_base), pcie->hose.first_busno); + + pcie_dw_regions_setup(pcie); + pcie_dw_set_host_bars(pcie->ctrl_base); + + return 0; +} + +static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev) +{ + struct pcie_dw_mvebu *pcie = dev_get_priv(dev); + + pcie->ctrl_base = (void *)dev_get_addr_index(dev, 0); + if (IS_ERR(pcie->ctrl_base)) + return PTR_ERR(pcie->ctrl_base); + + /* + * We need to know the size for the cfg space as well from the + * DT "reg" property. dev_get_addr_index() doesn't provide this + * size, so we need to use a different method to acquire the + * address and size here. + */ + pcie->cfg_base = (void *)fdtdec_get_addr_size_auto_noparent( + gd->fdt_blob, dev->of_offset, "reg", 1, &pcie->cfg_size, true); + if (pcie->cfg_base == NULL) + return -ENODEV; + + return 0; +} + +static const struct dm_pci_ops pcie_dw_mvebu_ops = { + .read_config = pcie_dw_mvebu_read_config, + .write_config = pcie_dw_mvebu_write_config, +}; + +static const struct udevice_id pcie_dw_mvebu_ids[] = { + { .compatible = "marvell,armada8k-pcie" }, + { } +}; + +U_BOOT_DRIVER(pcie_dw_mvebu) = { + .name = "pcie_dw_mvebu", + .id = UCLASS_PCI, + .of_match = pcie_dw_mvebu_ids, + .ops = &pcie_dw_mvebu_ops, + .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata, + .probe = pcie_dw_mvebu_probe, + .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu), +};

To use the PCIe driver, its controller memory and the PCIe regions need to get mapped in the MMU. Otherwise these areas can't be accessed.

Signed-off-by: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/mach-mvebu/armada8k/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index f8e69d6..2719d68 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -55,6 +55,14 @@ static struct mm_region mvebu_mem_map[] = { PTE_BLOCK_NON_SHARE }, { + /* PCI regions */ + .phys = 0xf8000000UL, + .virt = 0xf8000000UL, + .size = 0x08000000UL, /* 128MiB PCI space (master & slave) */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, + { /* List terminator */ 0, }

Not all memory is mapped in the MMU. So we need to restrict the memory size so that U-Boot does not try to access it. Also, the internal registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB are mapped for system memory. This is what we pass to the U-Boot subsystem here.

Signed-off-by: Stefan Roese sr@denx.de Cc: Nadav Haklai nadavh@marvell.com Cc: Neta Zur Hershkovits neta@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Omri Itach omrii@marvell.com Cc: Igal Liberman igall@marvell.com Cc: Haim Boot hayim@marvell.com Cc: Hanna Hawa hannah@marvell.com --- arch/arm/mach-mvebu/arm64-common.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 1fc2ff2..8f02655 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -17,6 +17,23 @@ DECLARE_GLOBAL_DATA_PTR;

/* + * Not all memory is mapped in the MMU. So we need to restrict the + * memory size so that U-Boot does not try to access it. Also, the + * internal registers are located at 0xf000.0000 - 0xffff.ffff. + * Currently only 2GiB are mapped for system memory. This is what + * we pass to the U-Boot subsystem here. + */ +#define USABLE_RAM_SIZE 0x80000000 + +ulong board_get_usable_ram_top(ulong total_size) +{ + if (gd->ram_size > USABLE_RAM_SIZE) + return USABLE_RAM_SIZE; + + return gd->ram_size; +} + +/* * On ARMv8, MBus is not configured in U-Boot. To enable compilation * of the already implemented drivers, lets add a dummy version of * this function so that linking does not fail.