[PATCH 00/13] USB support for QCS404 SoC
This series add support for USB on QCS404 SoC. USB support have dependencies on PHY, reset and PMIC GPIO drivers, so corresponding support has been added. There are also some renaming/reorganising patches (#1, #3 and #9) which tries to generalize drivers support for Qcom SoCs. - Patch #1 moves all Qcom PHY drivers to drivers/phy/qcom/. - Patch #3 coverts ipq4019 reset driver to a generic Qcom reset driver. - Patch #9 Convert pm8916 driver to a generic Qcom PMIC driver.
Sumit Garg (13): phy: Move qcom SoCs specific phy drivers to qcom folder phy: Add support for drivers to enable USB on QCS404 SoC reset: Convert ipq4019 driver to a generic Qcom driver reset: qcom: Add support for QCS404 SoC reset table dts: qcs404-evb: Add reset controller node clocks: qcom: Add clock enable callback support clocks: qcs404: Add support for USB clocks dts: qcs404-evb: Add USB controller and PHY nodes pmic: Convert pm8916 driver to a generic Qcom PMIC driver gpio: qcom_pmic: Add support for GPIO LV/MV subtype dts: qcs404-evb: Add PMIC GPIO controller node board: qcs404-evb: Enable USB3 specific PMIC GPIO qcs404evb_defconfig: Enable USB configs
arch/arm/dts/qcs404-evb-uboot.dtsi | 6 + arch/arm/dts/qcs404-evb.dts | 118 ++++++ arch/arm/mach-snapdragon/clock-apq8016.c | 5 + arch/arm/mach-snapdragon/clock-apq8096.c | 5 + arch/arm/mach-snapdragon/clock-qcs404.c | 40 ++ arch/arm/mach-snapdragon/clock-sdm845.c | 5 + arch/arm/mach-snapdragon/clock-snapdragon.c | 7 + .../include/mach/sysmap-qcs404.h | 17 + board/qualcomm/qcs404-evb/qcs404-evb.c | 29 ++ configs/dragonboard410c_defconfig | 4 +- configs/dragonboard820c_defconfig | 4 +- configs/dragonboard845c_defconfig | 4 +- configs/qcs404evb_defconfig | 18 + configs/sandbox64_defconfig | 4 +- configs/sandbox_defconfig | 4 +- configs/sandbox_flattree_defconfig | 4 +- configs/sandbox_noinst_defconfig | 4 +- configs/sandbox_spl_defconfig | 4 +- configs/sandbox_vpl_defconfig | 4 +- configs/starqltechn_defconfig | 4 +- doc/device-tree-bindings/pmic/pm8916.txt | 18 - .../pmic/qcom,spmi-pmic.txt | 94 +++++ drivers/gpio/Kconfig | 10 +- drivers/gpio/Makefile | 2 +- drivers/gpio/pm8916_gpio.c | 303 --------------- drivers/gpio/qcom_pmic_gpio.c | 359 ++++++++++++++++++ drivers/phy/Kconfig | 15 +- drivers/phy/Makefile | 3 +- drivers/phy/qcom/Kconfig | 29 ++ drivers/phy/qcom/Makefile | 4 + drivers/phy/{ => qcom}/msm8916-usbh-phy.c | 0 drivers/phy/{ => qcom}/phy-qcom-ipq4019-usb.c | 0 drivers/phy/qcom/phy-qcom-usb-hs-28nm.c | 250 ++++++++++++ drivers/phy/qcom/phy-qcom-usb-ss.c | 154 ++++++++ drivers/power/pmic/Kconfig | 8 +- drivers/power/pmic/Makefile | 2 +- drivers/power/pmic/{pm8916.c => pmic_qcom.c} | 42 +- drivers/reset/Kconfig | 9 +- drivers/reset/Makefile | 2 +- .../reset/{reset-ipq4019.c => reset-qcom.c} | 76 +++- 40 files changed, 1254 insertions(+), 416 deletions(-) delete mode 100644 doc/device-tree-bindings/pmic/pm8916.txt create mode 100644 doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt delete mode 100644 drivers/gpio/pm8916_gpio.c create mode 100644 drivers/gpio/qcom_pmic_gpio.c create mode 100644 drivers/phy/qcom/Kconfig create mode 100644 drivers/phy/qcom/Makefile rename drivers/phy/{ => qcom}/msm8916-usbh-phy.c (100%) rename drivers/phy/{ => qcom}/phy-qcom-ipq4019-usb.c (100%) create mode 100644 drivers/phy/qcom/phy-qcom-usb-hs-28nm.c create mode 100644 drivers/phy/qcom/phy-qcom-usb-ss.c rename drivers/power/pmic/{pm8916.c => pmic_qcom.c} (52%) rename drivers/reset/{reset-ipq4019.c => reset-qcom.c} (64%)
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/phy/Kconfig | 15 +-------------- drivers/phy/Makefile | 3 +-- drivers/phy/qcom/Kconfig | 13 +++++++++++++ drivers/phy/qcom/Makefile | 2 ++ drivers/phy/{ => qcom}/msm8916-usbh-phy.c | 0 drivers/phy/{ => qcom}/phy-qcom-ipq4019-usb.c | 0 6 files changed, 17 insertions(+), 16 deletions(-) create mode 100644 drivers/phy/qcom/Kconfig create mode 100644 drivers/phy/qcom/Makefile rename drivers/phy/{ => qcom}/msm8916-usbh-phy.c (100%) rename drivers/phy/{ => qcom}/phy-qcom-ipq4019-usb.c (100%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c25b42c68f..cf4d5908d7 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -143,12 +143,6 @@ config STI_USB_PHY used by USB2 and USB3 Host controllers available on STiH407 SoC families.
-config PHY_QCOM_IPQ4019_USB - tristate "Qualcomm IPQ4019 USB PHY driver" - depends on PHY && ARCH_IPQ40XX - help - Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. - config PHY_RCAR_GEN2 tristate "Renesas R-Car Gen2 USB PHY" depends on PHY && RCAR_GEN2 @@ -220,14 +214,6 @@ config MESON_AXG_MIPI_PCIE_ANALOG_PHY This is the generic phy driver for the Amlogic Meson AXG MIPI PCIe Analog PHY.
-config MSM8916_USB_PHY - bool "Qualcomm MSM8916 USB PHY support" - depends on PHY - help - Support the USB PHY in msm8916 - - This PHY is found on qualcomm dragonboard410c development board. - config OMAP_USB2_PHY bool "Support OMAP's USB2 PHY" depends on PHY @@ -298,5 +284,6 @@ config PHY_XILINX_ZYNQMP source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" +source "drivers/phy/qcom/Kconfig"
endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d95439c425..a3b9f3c5b1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o -obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o @@ -30,7 +29,6 @@ obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o obj-$(CONFIG_MESON_AXG_MIPI_DPHY) += meson-axg-mipi-dphy.o obj-$(CONFIG_MESON_AXG_MIPI_PCIE_ANALOG_PHY) += meson-axg-mipi-pcie-analog.o -obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o @@ -42,3 +40,4 @@ obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ +obj-y += qcom/ diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig new file mode 100644 index 0000000000..f685a6455e --- /dev/null +++ b/drivers/phy/qcom/Kconfig @@ -0,0 +1,13 @@ +config MSM8916_USB_PHY + bool "Qualcomm MSM8916 USB PHY support" + depends on PHY + help + Support the USB PHY in msm8916 + + This PHY is found on qualcomm dragonboard410c development board. + +config PHY_QCOM_IPQ4019_USB + tristate "Qualcomm IPQ4019 USB PHY driver" + depends on PHY && ARCH_IPQ40XX + help + Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile new file mode 100644 index 0000000000..4a340e33c8 --- /dev/null +++ b/drivers/phy/qcom/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o +obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o diff --git a/drivers/phy/msm8916-usbh-phy.c b/drivers/phy/qcom/msm8916-usbh-phy.c similarity index 100% rename from drivers/phy/msm8916-usbh-phy.c rename to drivers/phy/qcom/msm8916-usbh-phy.c diff --git a/drivers/phy/phy-qcom-ipq4019-usb.c b/drivers/phy/qcom/phy-qcom-ipq4019-usb.c similarity index 100% rename from drivers/phy/phy-qcom-ipq4019-usb.c rename to drivers/phy/qcom/phy-qcom-ipq4019-usb.c
On Thu, Aug 04, 2022 at 07:57:09PM +0530, Sumit Garg wrote:
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
QCS404 SoC supports two types of PHY, one supports high speed mode or USB2 PHY and the other supports super speed mode or USB3 PHY. So add corresponding PHY drivers.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/phy/qcom/Kconfig | 16 ++ drivers/phy/qcom/Makefile | 2 + drivers/phy/qcom/phy-qcom-usb-hs-28nm.c | 250 ++++++++++++++++++++++++ drivers/phy/qcom/phy-qcom-usb-ss.c | 154 +++++++++++++++ 4 files changed, 422 insertions(+) create mode 100644 drivers/phy/qcom/phy-qcom-usb-hs-28nm.c create mode 100644 drivers/phy/qcom/phy-qcom-usb-ss.c
diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index f685a6455e..f4ca174805 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -11,3 +11,19 @@ config PHY_QCOM_IPQ4019_USB depends on PHY && ARCH_IPQ40XX help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. + +config PHY_QCOM_USB_HS_28NM + tristate "Qualcomm 28nm High-Speed PHY" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Qualcomm Synopsys DesignWare Core 28nm + High-Speed PHY driver. This driver supports the Hi-Speed PHY which + is usually paired with either the ChipIdea or Synopsys DWC3 USB + IPs on MSM SOCs. + +config PHY_QCOM_USB_SS + tristate "Qualcomm USB Super-Speed PHY driver" + depends on PHY && ARCH_SNAPDRAGON + help + Enable this to support the Super-Speed USB transceiver on various + Qualcomm chipsets. diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile index 4a340e33c8..2113f178c0 100644 --- a/drivers/phy/qcom/Makefile +++ b/drivers/phy/qcom/Makefile @@ -1,2 +1,4 @@ obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o +obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o +obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c b/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c new file mode 100644 index 0000000000..14c3d8394d --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-usb-hs-28nm.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sumit Garg sumit.garg@linaro.org + * + * Based on Linux driver + */ + +#include <common.h> +#include <dm.h> +#include <generic-phy.h> +#include <reset.h> +#include <clk.h> +#include <asm/io.h> +#include <linux/delay.h> + +/* PHY register and bit definitions */ +#define PHY_CTRL_COMMON0 0x078 +#define SIDDQ BIT(2) + +struct hsphy_init_seq { + int offset; + int val; + int delay; +}; + +struct hsphy_data { + const struct hsphy_init_seq *init_seq; + unsigned int init_seq_num; +}; + +struct hsphy_priv { + void __iomem *base; + struct clk_bulk clks; + struct reset_ctl phy_rst; + struct reset_ctl por_rst; + const struct hsphy_data *data; +}; + +static int hsphy_power_on(struct phy *phy) +{ + struct hsphy_priv *priv = dev_get_priv(phy->dev); + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val &= ~SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); + + return 0; +} + +static int hsphy_power_off(struct phy *phy) +{ + struct hsphy_priv *priv = dev_get_priv(phy->dev); + u32 val; + + val = readb(priv->base + PHY_CTRL_COMMON0); + val |= SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); + + return 0; +} + +static int hsphy_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_assert(&priv->phy_rst); + if (ret) + return ret; + + udelay(10); + + ret = reset_deassert(&priv->phy_rst); + if (ret) + return ret; + + udelay(80); + + return 0; +} + +static void hsphy_init_sequence(struct hsphy_priv *priv) +{ + const struct hsphy_data *data = priv->data; + const struct hsphy_init_seq *seq; + int i; + + /* Device match data is optional. */ + if (!data) + return; + + seq = data->init_seq; + + for (i = 0; i < data->init_seq_num; i++, seq++) { + writeb(seq->val, priv->base + seq->offset); + if (seq->delay) + udelay(seq->delay); + } +} + +static int hsphy_por_reset(struct hsphy_priv *priv) +{ + int ret; + u32 val; + + ret = reset_assert(&priv->por_rst); + if (ret) + return ret; + + /* + * The Femto PHY is POR reset in the following scenarios. + * + * 1. After overriding the parameter registers. + * 2. Low power mode exit from PHY retention. + * + * Ensure that SIDDQ is cleared before bringing the PHY + * out of reset. + */ + val = readb(priv->base + PHY_CTRL_COMMON0); + val &= ~SIDDQ; + writeb(val, priv->base + PHY_CTRL_COMMON0); + + /* + * As per databook, 10 usec delay is required between + * PHY POR assert and de-assert. + */ + udelay(10); + ret = reset_deassert(&priv->por_rst); + if (ret) + return ret; + + /* + * As per databook, it takes 75 usec for PHY to stabilize + * after the reset. + */ + udelay(80); + + return 0; +} + +static int hsphy_clk_init(struct udevice *dev, struct hsphy_priv *priv) +{ + int ret; + + ret = clk_get_bulk(dev, &priv->clks); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable_bulk(&priv->clks); + if (ret) { + clk_release_bulk(&priv->clks); + return ret; + } + + return 0; +} + +static int hsphy_init(struct phy *phy) +{ + struct hsphy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = hsphy_clk_init(phy->dev, priv); + if (ret) + return ret; + + ret = hsphy_reset(priv); + if (ret) + return ret; + + hsphy_init_sequence(priv); + + hsphy_por_reset(priv); + if (ret) + return ret; + + return 0; +} + +static int hsphy_probe(struct udevice *dev) +{ + struct hsphy_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = (void *)dev_read_addr(dev); + if ((ulong)priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = reset_get_by_name(dev, "phy", &priv->phy_rst); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "por", &priv->por_rst); + if (ret) + return ret; + + priv->data = (const struct hsphy_data *)dev_get_driver_data(dev); + + return 0; +} + +static struct phy_ops hsphy_ops = { + .power_on = hsphy_power_on, + .power_off = hsphy_power_off, + .init = hsphy_init, +}; + +/* + * The macro is used to define an initialization sequence. Each tuple + * is meant to program 'value' into phy register at 'offset' with 'delay' + * in us followed. + */ +#define HSPHY_INIT_CFG(o, v, d) { .offset = o, .val = v, .delay = d, } + +static const struct hsphy_init_seq init_seq_femtophy[] = { + HSPHY_INIT_CFG(0xc0, 0x01, 0), + HSPHY_INIT_CFG(0xe8, 0x0d, 0), + HSPHY_INIT_CFG(0x74, 0x12, 0), + HSPHY_INIT_CFG(0x98, 0x63, 0), + HSPHY_INIT_CFG(0x9c, 0x03, 0), + HSPHY_INIT_CFG(0xa0, 0x1d, 0), + HSPHY_INIT_CFG(0xa4, 0x03, 0), + HSPHY_INIT_CFG(0x8c, 0x23, 0), + HSPHY_INIT_CFG(0x78, 0x08, 0), + HSPHY_INIT_CFG(0x7c, 0xdc, 0), + HSPHY_INIT_CFG(0x90, 0xe0, 20), + HSPHY_INIT_CFG(0x74, 0x10, 0), + HSPHY_INIT_CFG(0x90, 0x60, 0), +}; + +static const struct hsphy_data data_femtophy = { + .init_seq = init_seq_femtophy, + .init_seq_num = ARRAY_SIZE(init_seq_femtophy), +}; + +static const struct udevice_id hsphy_ids[] = { + { .compatible = "qcom,usb-hs-28nm-femtophy", .data = (ulong)&data_femtophy }, + { } +}; + +U_BOOT_DRIVER(qcom_usb_hs_28nm) = { + .name = "qcom-usb-hs-28nm", + .id = UCLASS_PHY, + .of_match = hsphy_ids, + .ops = &hsphy_ops, + .probe = hsphy_probe, + .priv_auto = sizeof(struct hsphy_priv), +}; diff --git a/drivers/phy/qcom/phy-qcom-usb-ss.c b/drivers/phy/qcom/phy-qcom-usb-ss.c new file mode 100644 index 0000000000..4e816879c6 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-usb-ss.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Sumit Garg sumit.garg@linaro.org + * + * Based on Linux driver + */ + +#include <common.h> +#include <dm.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <asm/io.h> +#include <reset.h> +#include <clk.h> +#include <linux/delay.h> + +#define PHY_CTRL0 0x6C +#define PHY_CTRL1 0x70 +#define PHY_CTRL2 0x74 +#define PHY_CTRL4 0x7C + +/* PHY_CTRL bits */ +#define REF_PHY_EN BIT(0) +#define LANE0_PWR_ON BIT(2) +#define SWI_PCS_CLK_SEL BIT(4) +#define TST_PWR_DOWN BIT(4) +#define PHY_RESET BIT(7) + +struct ssphy_priv { + void __iomem *base; + struct clk_bulk clks; + struct reset_ctl com_rst; + struct reset_ctl phy_rst; +}; + +static inline void ssphy_updatel(void __iomem *addr, u32 mask, u32 val) +{ + writel((readl(addr) & ~mask) | val, addr); +} + +static int ssphy_do_reset(struct ssphy_priv *priv) +{ + int ret; + + ret = reset_assert(&priv->com_rst); + if (ret) + return ret; + + ret = reset_assert(&priv->phy_rst); + if (ret) + return ret; + + udelay(10); + + ret = reset_deassert(&priv->com_rst); + if (ret) + return ret; + + ret = reset_deassert(&priv->phy_rst); + if (ret) + return ret; + + return 0; +} + +static int ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = ssphy_do_reset(priv); + if (ret) + return ret; + + writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); + ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); + ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); + ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); + + return 0; +} + +static int ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = dev_get_priv(phy->dev); + + ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); + ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); + ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); + + return 0; +} + +static int ssphy_clk_init(struct udevice *dev, struct ssphy_priv *priv) +{ + int ret; + + ret = clk_get_bulk(dev, &priv->clks); + if (ret == -ENOSYS || ret == -ENOENT) + return 0; + if (ret) + return ret; + + ret = clk_enable_bulk(&priv->clks); + if (ret) { + clk_release_bulk(&priv->clks); + return ret; + } + + return 0; +} + +static int ssphy_probe(struct udevice *dev) +{ + struct ssphy_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = (void *)dev_read_addr(dev); + if ((ulong)priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = ssphy_clk_init(dev, priv); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "com", &priv->com_rst); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "phy", &priv->phy_rst); + if (ret) + return ret; + + return 0; +} + +static struct phy_ops ssphy_ops = { + .power_on = ssphy_power_on, + .power_off = ssphy_power_off, +}; + +static const struct udevice_id ssphy_ids[] = { + { .compatible = "qcom,usb-ss-28nm-phy" }, + { } +}; + +U_BOOT_DRIVER(qcom_usb_ss) = { + .name = "qcom-usb-ss", + .id = UCLASS_PHY, + .of_match = ssphy_ids, + .ops = &ssphy_ops, + .probe = ssphy_probe, + .priv_auto = sizeof(struct ssphy_priv), +};
On Thu, Aug 04, 2022 at 07:57:10PM +0530, Sumit Garg wrote:
QCS404 SoC supports two types of PHY, one supports high speed mode or USB2 PHY and the other supports super speed mode or USB3 PHY. So add corresponding PHY drivers.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/reset/Kconfig | 9 ++-- drivers/reset/Makefile | 2 +- .../reset/{reset-ipq4019.c => reset-qcom.c} | 46 ++++++++++--------- 3 files changed, 30 insertions(+), 27 deletions(-) rename drivers/reset/{reset-ipq4019.c => reset-qcom.c} (79%)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 69a7b4ccba..4cb0ba0850 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -156,13 +156,12 @@ config RESET_IMX7 help Support for reset controller on i.MX7/8 SoCs.
-config RESET_IPQ419 - bool "Reset driver for Qualcomm IPQ40xx SoCs" - depends on DM_RESET && ARCH_IPQ40XX +config RESET_QCOM + bool "Reset driver for Qualcomm SoCs" + depends on DM_RESET && (ARCH_SNAPDRAGON || ARCH_IPQ40XX) default y help - Support for reset controller on Qualcomm - IPQ40xx SoCs. + Support for reset controller on Qualcomm SoCs.
config RESET_SIFIVE bool "Reset Driver for SiFive SoC's" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 97e3a782c0..0620b62809 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o -obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o +obj-$(CONFIG_RESET_QCOM) += reset-qcom.o obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o diff --git a/drivers/reset/reset-ipq4019.c b/drivers/reset/reset-qcom.c similarity index 79% rename from drivers/reset/reset-ipq4019.c rename to drivers/reset/reset-qcom.c index 7f0bd85ad6..40f436ede4 100644 --- a/drivers/reset/reset-ipq4019.c +++ b/drivers/reset/reset-qcom.c @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020 Sartura Ltd. + * Copyright (c) 2022 Linaro Ltd. * * Author: Robert Marko robert.marko@sartura.hr + * Sumit Garg sumit.garg@linaro.org * * Based on Linux driver */ @@ -10,12 +12,11 @@ #include <asm/io.h> #include <common.h> #include <dm.h> -#include <dt-bindings/reset/qcom,ipq4019-reset.h> #include <reset-uclass.h> #include <linux/bitops.h> #include <malloc.h>
-struct ipq4019_reset_priv { +struct qcom_reset_priv { phys_addr_t base; };
@@ -24,7 +25,9 @@ struct qcom_reset_map { u8 bit; };
-static const struct qcom_reset_map gcc_ipq4019_resets[] = { +#ifdef CONFIG_ARCH_IPQ40XX +#include <dt-bindings/reset/qcom,ipq4019-reset.h> +static const struct qcom_reset_map gcc_qcom_resets[] = { [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, @@ -97,11 +100,12 @@ static const struct qcom_reset_map gcc_ipq4019_resets[] = { [GCC_MPM_BCR] = {0x24000, 0}, [GCC_SPDM_BCR] = {0x25000, 0}, }; +#endif
-static int ipq4019_reset_assert(struct reset_ctl *rst) +static int qcom_reset_assert(struct reset_ctl *rst) { - struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev); - const struct qcom_reset_map *reset_map = gcc_ipq4019_resets; + struct qcom_reset_priv *priv = dev_get_priv(rst->dev); + const struct qcom_reset_map *reset_map = gcc_qcom_resets; const struct qcom_reset_map *map; u32 value;
@@ -114,10 +118,10 @@ static int ipq4019_reset_assert(struct reset_ctl *rst) return 0; }
-static int ipq4019_reset_deassert(struct reset_ctl *rst) +static int qcom_reset_deassert(struct reset_ctl *rst) { - struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev); - const struct qcom_reset_map *reset_map = gcc_ipq4019_resets; + struct qcom_reset_priv *priv = dev_get_priv(rst->dev); + const struct qcom_reset_map *reset_map = gcc_qcom_resets; const struct qcom_reset_map *map; u32 value;
@@ -130,19 +134,19 @@ static int ipq4019_reset_deassert(struct reset_ctl *rst) return 0; }
-static const struct reset_ops ipq4019_reset_ops = { - .rst_assert = ipq4019_reset_assert, - .rst_deassert = ipq4019_reset_deassert, +static const struct reset_ops qcom_reset_ops = { + .rst_assert = qcom_reset_assert, + .rst_deassert = qcom_reset_deassert, };
-static const struct udevice_id ipq4019_reset_ids[] = { +static const struct udevice_id qcom_reset_ids[] = { { .compatible = "qcom,gcc-reset-ipq4019" }, { } };
-static int ipq4019_reset_probe(struct udevice *dev) +static int qcom_reset_probe(struct udevice *dev) { - struct ipq4019_reset_priv *priv = dev_get_priv(dev); + struct qcom_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) @@ -151,11 +155,11 @@ static int ipq4019_reset_probe(struct udevice *dev) return 0; }
-U_BOOT_DRIVER(ipq4019_reset) = { - .name = "ipq4019_reset", +U_BOOT_DRIVER(qcom_reset) = { + .name = "qcom_reset", .id = UCLASS_RESET, - .of_match = ipq4019_reset_ids, - .ops = &ipq4019_reset_ops, - .probe = ipq4019_reset_probe, - .priv_auto = sizeof(struct ipq4019_reset_priv), + .of_match = qcom_reset_ids, + .ops = &qcom_reset_ops, + .probe = qcom_reset_probe, + .priv_auto = sizeof(struct qcom_reset_priv), };
On Thu, Aug 04, 2022 at 07:57:11PM +0530, Sumit Garg wrote:
Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/reset/reset-qcom.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 40f436ede4..94315e76d5 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -102,6 +102,35 @@ static const struct qcom_reset_map gcc_qcom_resets[] = { }; #endif
+#ifdef CONFIG_TARGET_QCS404EVB +#include <dt-bindings/clock/qcom,gcc-qcs404.h> +static const struct qcom_reset_map gcc_qcom_resets[] = { + [GCC_GENI_IR_BCR] = { 0x0F000 }, + [GCC_CDSP_RESTART] = { 0x18000 }, + [GCC_USB_HS_BCR] = { 0x41000 }, + [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, + [GCC_QUSB2_PHY_BCR] = { 0x4103c }, + [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 }, + [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 }, + [GCC_USB3_PHY_BCR] = { 0x39004 }, + [GCC_USB_30_BCR] = { 0x39000 }, + [GCC_USB3PHY_PHY_BCR] = { 0x39008 }, + [GCC_PCIE_0_BCR] = { 0x3e000 }, + [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, + [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, + [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, + [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, + [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, + [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, + [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, + [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, + [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, + [GCC_EMAC_BCR] = { 0x4e000 }, + [GCC_WDSP_RESTART] = {0x19000}, +}; +#endif + static int qcom_reset_assert(struct reset_ctl *rst) { struct qcom_reset_priv *priv = dev_get_priv(rst->dev); @@ -141,6 +170,7 @@ static const struct reset_ops qcom_reset_ops = {
static const struct udevice_id qcom_reset_ids[] = { { .compatible = "qcom,gcc-reset-ipq4019" }, + { .compatible = "qcom,gcc-reset-qcs404" }, { } };
On Thu, Aug 4, 2022 at 4:28 PM Sumit Garg sumit.garg@linaro.org wrote:
Signed-off-by: Sumit Garg sumit.garg@linaro.org
drivers/reset/reset-qcom.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 40f436ede4..94315e76d5 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -102,6 +102,35 @@ static const struct qcom_reset_map gcc_qcom_resets[] = { }; #endif
+#ifdef CONFIG_TARGET_QCS404EVB
Hi, Why not pass the reset maps via match data per compatible?
Regards, Robert
+#include <dt-bindings/clock/qcom,gcc-qcs404.h> +static const struct qcom_reset_map gcc_qcom_resets[] = {
[GCC_GENI_IR_BCR] = { 0x0F000 },[GCC_CDSP_RESTART] = { 0x18000 },[GCC_USB_HS_BCR] = { 0x41000 },[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },[GCC_QUSB2_PHY_BCR] = { 0x4103c },[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },[GCC_USB3_PHY_BCR] = { 0x39004 },[GCC_USB_30_BCR] = { 0x39000 },[GCC_USB3PHY_PHY_BCR] = { 0x39008 },[GCC_PCIE_0_BCR] = { 0x3e000 },[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },[GCC_EMAC_BCR] = { 0x4e000 },[GCC_WDSP_RESTART] = {0x19000},+}; +#endif
static int qcom_reset_assert(struct reset_ctl *rst) { struct qcom_reset_priv *priv = dev_get_priv(rst->dev); @@ -141,6 +170,7 @@ static const struct reset_ops qcom_reset_ops = {
static const struct udevice_id qcom_reset_ids[] = { { .compatible = "qcom,gcc-reset-ipq4019" },
{ .compatible = "qcom,gcc-reset-qcs404" }, { }};
-- 2.25.1
Hi Robert,
Thanks for your review.
On Sat, 6 Aug 2022 at 13:11, Robert Marko robert.marko@sartura.hr wrote:
On Thu, Aug 4, 2022 at 4:28 PM Sumit Garg sumit.garg@linaro.org wrote:
Signed-off-by: Sumit Garg sumit.garg@linaro.org
drivers/reset/reset-qcom.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 40f436ede4..94315e76d5 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -102,6 +102,35 @@ static const struct qcom_reset_map gcc_qcom_resets[] = { }; #endif
+#ifdef CONFIG_TARGET_QCS404EVB
Hi, Why not pass the reset maps via match data per compatible?
Yeah but that won't allow me to get rid of this "#ifdef" since bindings header (qcom,gcc-qcs404.h) and corresponding reset table needs to be included under it due to overlapping reset IDs. So it won't add any value.
-Sumit
Regards, Robert
+#include <dt-bindings/clock/qcom,gcc-qcs404.h> +static const struct qcom_reset_map gcc_qcom_resets[] = {
[GCC_GENI_IR_BCR] = { 0x0F000 },[GCC_CDSP_RESTART] = { 0x18000 },[GCC_USB_HS_BCR] = { 0x41000 },[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },[GCC_QUSB2_PHY_BCR] = { 0x4103c },[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },[GCC_USB3_PHY_BCR] = { 0x39004 },[GCC_USB_30_BCR] = { 0x39000 },[GCC_USB3PHY_PHY_BCR] = { 0x39008 },[GCC_PCIE_0_BCR] = { 0x3e000 },[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },[GCC_EMAC_BCR] = { 0x4e000 },[GCC_WDSP_RESTART] = {0x19000},+}; +#endif
static int qcom_reset_assert(struct reset_ctl *rst) { struct qcom_reset_priv *priv = dev_get_priv(rst->dev); @@ -141,6 +170,7 @@ static const struct reset_ops qcom_reset_ops = {
static const struct udevice_id qcom_reset_ids[] = { { .compatible = "qcom,gcc-reset-ipq4019" },
{ .compatible = "qcom,gcc-reset-qcs404" }, { }};
-- 2.25.1
-- Robert Marko Staff Embedded Linux Engineer Sartura Ltd. Lendavska ulica 16a 10000 Zagreb, Croatia Email: robert.marko@sartura.hr Web: www.sartura.hr
On Tue, Aug 9, 2022 at 3:25 PM Sumit Garg sumit.garg@linaro.org wrote:
Hi Robert,
Thanks for your review.
On Sat, 6 Aug 2022 at 13:11, Robert Marko robert.marko@sartura.hr wrote:
On Thu, Aug 4, 2022 at 4:28 PM Sumit Garg sumit.garg@linaro.org wrote:
Signed-off-by: Sumit Garg sumit.garg@linaro.org
drivers/reset/reset-qcom.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 40f436ede4..94315e76d5 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -102,6 +102,35 @@ static const struct qcom_reset_map gcc_qcom_resets[] = { }; #endif
+#ifdef CONFIG_TARGET_QCS404EVB
Hi, Why not pass the reset maps via match data per compatible?
Yeah but that won't allow me to get rid of this "#ifdef" since bindings header (qcom,gcc-qcs404.h) and corresponding reset table needs to be included under it due to overlapping reset IDs. So it won't add any value.
Hi,
I see it now.
Regards, Robert
-Sumit
Regards, Robert
+#include <dt-bindings/clock/qcom,gcc-qcs404.h> +static const struct qcom_reset_map gcc_qcom_resets[] = {
[GCC_GENI_IR_BCR] = { 0x0F000 },[GCC_CDSP_RESTART] = { 0x18000 },[GCC_USB_HS_BCR] = { 0x41000 },[GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },[GCC_QUSB2_PHY_BCR] = { 0x4103c },[GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },[GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },[GCC_USB3_PHY_BCR] = { 0x39004 },[GCC_USB_30_BCR] = { 0x39000 },[GCC_USB3PHY_PHY_BCR] = { 0x39008 },[GCC_PCIE_0_BCR] = { 0x3e000 },[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },[GCC_EMAC_BCR] = { 0x4e000 },[GCC_WDSP_RESTART] = {0x19000},+}; +#endif
static int qcom_reset_assert(struct reset_ctl *rst) { struct qcom_reset_priv *priv = dev_get_priv(rst->dev); @@ -141,6 +170,7 @@ static const struct reset_ops qcom_reset_ops = {
static const struct udevice_id qcom_reset_ids[] = { { .compatible = "qcom,gcc-reset-ipq4019" },
{ .compatible = "qcom,gcc-reset-qcs404" }, { }};
-- 2.25.1
-- Robert Marko Staff Embedded Linux Engineer Sartura Ltd. Lendavska ulica 16a 10000 Zagreb, Croatia Email: robert.marko@sartura.hr Web: www.sartura.hr
On Thu, Aug 04, 2022 at 07:57:12PM +0530, Sumit Garg wrote:
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/dts/qcs404-evb.dts | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 09687e1fd3..1b280efff6 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -54,6 +54,12 @@ #size-cells = <0x0>; };
+ reset: gcc-reset@1800000 { + compatible = "qcom,gcc-reset-qcs404"; + reg = <0x1800000 0x80000>; + #reset-cells = <1>; + }; + debug_uart: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4"; reg = <0x78b1000 0x200>;
On Thu, Aug 04, 2022 at 07:57:13PM +0530, Sumit Garg wrote:
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Drivers like USB, ethernet etc. uses ".enable" hook to enable clocks. So add corresponding support for Qcom clock drivers.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/mach-snapdragon/clock-apq8016.c | 5 +++++ arch/arm/mach-snapdragon/clock-apq8096.c | 5 +++++ arch/arm/mach-snapdragon/clock-qcs404.c | 5 +++++ arch/arm/mach-snapdragon/clock-sdm845.c | 5 +++++ arch/arm/mach-snapdragon/clock-snapdragon.c | 7 +++++++ 5 files changed, 27 insertions(+)
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c index 6e4a0ccb90..23a37a1714 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/arch/arm/mach-snapdragon/clock-apq8016.c @@ -111,3 +111,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index e5011be8f2..66184596d5 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -93,3 +93,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c index bb8a6fe067..230d7779a7 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -77,3 +77,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
return 0; } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c index f69be80898..d6df0365af 100644 --- a/arch/arm/mach-snapdragon/clock-sdm845.c +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -91,3 +91,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) return 0; } } + +int msm_enable(struct clk *clk) +{ + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 5652d2fa36..fda7098274 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -20,6 +20,7 @@ #define CBCR_BRANCH_OFF_BIT BIT(31)
extern ulong msm_set_rate(struct clk *clk, ulong rate); +extern int msm_enable(struct clk *clk);
/* Enable clock controlled by CBC soft macro */ void clk_enable_cbc(phys_addr_t cbcr) @@ -126,8 +127,14 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate) return msm_set_rate(clk, rate); }
+static int msm_clk_enable(struct clk *clk) +{ + return msm_enable(clk); +} + static struct clk_ops msm_clk_ops = { .set_rate = msm_clk_set_rate, + .enable = msm_clk_enable, };
static const struct udevice_id msm_clk_ids[] = {
On Thu, Aug 04, 2022 at 07:57:14PM +0530, Sumit Garg wrote:
Drivers like USB, ethernet etc. uses ".enable" hook to enable clocks. So add corresponding support for Qcom clock drivers.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Add support for USB controller and PHY clocks for QCS404 SoC.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/mach-snapdragon/clock-qcs404.c | 35 +++++++++++++++++++ .../include/mach/sysmap-qcs404.h | 17 +++++++++ 2 files changed, 52 insertions(+)
diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c index 230d7779a7..6fe92afe8d 100644 --- a/arch/arm/mach-snapdragon/clock-qcs404.c +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -47,6 +47,14 @@ static struct pll_vote_clk gpll0_vote_clk = { .vote_bit = BIT(0), };
+static const struct bcr_regs usb30_master_regs = { + .cfg_rcgr = USB30_MASTER_CFG_RCGR, + .cmd_rcgr = USB30_MASTER_CMD_RCGR, + .M = USB30_MASTER_M, + .N = USB30_MASTER_N, + .D = USB30_MASTER_D, +}; + ulong msm_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -80,5 +88,32 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
int msm_enable(struct clk *clk) { + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_USB30_MASTER_CLK: + clk_enable_cbc(priv->base + USB30_MASTER_CBCR); + clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0, + CFG_CLK_SRC_GPLL0); + break; + case GCC_SYS_NOC_USB3_CLK: + clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR); + break; + case GCC_USB30_SLEEP_CLK: + clk_enable_cbc(priv->base + USB30_SLEEP_CBCR); + break; + case GCC_USB30_MOCK_UTMI_CLK: + clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR); + break; + case GCC_USB_HS_PHY_CFG_AHB_CLK: + clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR); + break; + case GCC_USB2A_PHY_SLEEP_CLK: + clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR); + break; + default: + return 0; + } + return 0; } diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h index 4dc96b9fbc..e448faad2d 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h @@ -37,4 +37,21 @@ #define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) #define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
+/* USB-3.0 controller clock control registers */ +#define SYS_NOC_USB3_CBCR (0x26014) +#define USB30_BCR (0x39000) +#define USB3PHY_BCR (0x39008) +#define USB30_MASTER_CBCR (0x3900C) +#define USB30_SLEEP_CBCR (0x39010) +#define USB30_MOCK_UTMI_CBCR (0x39014) +#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C) +#define USB30_MOCK_UTMI_CFG_RCGR (0x39020) +#define USB30_MASTER_CMD_RCGR (0x39028) +#define USB30_MASTER_CFG_RCGR (0x3902C) +#define USB30_MASTER_M (0x39030) +#define USB30_MASTER_N (0x39034) +#define USB30_MASTER_D (0x39038) +#define USB2A_PHY_SLEEP_CBCR (0x4102C) +#define USB_HS_PHY_CFG_AHB_CBCR (0x41030) + #endif
On Thu, Aug 04, 2022 at 07:57:15PM +0530, Sumit Garg wrote:
Add support for USB controller and PHY clocks for QCS404 SoC.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
QCS404 SoC provides support for two USB controllers: one USB3 and the other one being USB2. The USB3 controller supports further 2 PHY: one high speed PHY and the other super speed PHY. The USB2 controller supports a single high speed PHY. So add corresponding DT nodes.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/dts/qcs404-evb.dts | 87 +++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+)
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 1b280efff6..2e3a0c6958 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -52,6 +52,7 @@ reg = <0x1800000 0x80000>; #address-cells = <0x1>; #size-cells = <0x0>; + #clock-cells = <1>; };
reset: gcc-reset@1800000 { @@ -81,6 +82,92 @@ mmc-ddr-1_8v; mmc-hs400-1_8v; }; + + usb3_phy: phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + #phy-cells = <0>; + reg = <0x78000 0x400>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ahb", "pipe"; + resets = <&reset GCC_USB3_PHY_BCR>, + <&reset GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + #phy-cells = <0>; + reg = <0x7a000 0x200>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ahb", "sleep"; + resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&reset GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + #phy-cells = <0>; + reg = <0x7c000 0x200>; + clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ahb", "sleep"; + resets = <&reset GCC_QUSB2_PHY_BCR>, + <&reset GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + }; + + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x7678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x7580000 0xcd00>; + phys = <&usb2_phy_prim>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x79b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x78c0000 0xcc00>; + phys = <&usb2_phy_sec>; + phy-names = "usb2-phy"; + dr_mode = "peripheral"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + }; + }; }; };
On Thu, Aug 04, 2022 at 07:57:16PM +0530, Sumit Garg wrote:
QCS404 SoC provides support for two USB controllers: one USB3 and the other one being USB2. The USB3 controller supports further 2 PHY: one high speed PHY and the other super speed PHY. The USB2 controller supports a single high speed PHY. So add corresponding DT nodes.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Since both pm8916.c and pm8916_gpio.c are already supporting multiple Qcom SoCs, it makes sense to rename these drivers to pmic_qcom.c and qcom_pmic_gpio.c respectively. Also, these driver can be extended to support additional functionality if required for other Qcom SoCs.
Along with this import latest DT binding: qcom,spmi-pmic.txt from Linux kernel and thereby remove pm8916.txt.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- configs/dragonboard410c_defconfig | 4 +- configs/dragonboard820c_defconfig | 4 +- configs/dragonboard845c_defconfig | 4 +- configs/sandbox64_defconfig | 4 +- configs/sandbox_defconfig | 4 +- configs/sandbox_flattree_defconfig | 4 +- configs/sandbox_noinst_defconfig | 4 +- configs/sandbox_spl_defconfig | 4 +- configs/sandbox_vpl_defconfig | 4 +- configs/starqltechn_defconfig | 4 +- doc/device-tree-bindings/pmic/pm8916.txt | 18 --- .../pmic/qcom,spmi-pmic.txt | 94 +++++++++++++++ drivers/gpio/Kconfig | 10 +- drivers/gpio/Makefile | 2 +- .../gpio/{pm8916_gpio.c => qcom_pmic_gpio.c} | 108 +++++++++--------- drivers/power/pmic/Kconfig | 8 +- drivers/power/pmic/Makefile | 2 +- drivers/power/pmic/{pm8916.c => pmic_qcom.c} | 42 +++---- 18 files changed, 200 insertions(+), 124 deletions(-) delete mode 100644 doc/device-tree-bindings/pmic/pm8916.txt create mode 100644 doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt rename drivers/gpio/{pm8916_gpio.c => qcom_pmic_gpio.c} (67%) rename drivers/power/pmic/{pm8916.c => pmic_qcom.c} (52%)
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 2bf759d843..fa6476ed1a 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -43,7 +43,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x91000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_MSM_GPIO=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_SDHCI=y @@ -52,7 +52,7 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_PMIC=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_MSM_SERIAL=y CONFIG_SPMI_MSM=y CONFIG_USB=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index 2ede13fed1..6b4483bf69 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -36,12 +36,12 @@ CONFIG_ENV_EXT4_INTERFACE="mmc" CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MSM=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_PMIC=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_MSM_SERIAL=y CONFIG_SPMI_MSM=y diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig index cf1a1d25cf..a69d82761a 100644 --- a/configs/dragonboard845c_defconfig +++ b/configs/dragonboard845c_defconfig @@ -20,10 +20,10 @@ CONFIG_CMD_GPIO=y # CONFIG_NET is not set CONFIG_CLK=y CONFIG_MSM_GPIO=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_PINCTRL=y CONFIG_DM_PMIC=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_MSM_GENI_SERIAL=y CONFIG_SPMI_MSM=y CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 6553568e76..537495d159 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -127,7 +127,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_SANDBOX_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y @@ -179,7 +179,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_PMIC_MAX77686=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_PMIC_RK8XX=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_PMIC_SANDBOX=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 572cf8edd8..72a7b5bb76 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -169,7 +169,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_SANDBOX_GPIO=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_SANDBOX=y @@ -230,7 +230,7 @@ CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_PMIC_MC34708=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_PMIC_RK8XX=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_PMIC_SANDBOX=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index a71ce77c40..a8aeedc75c 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -99,7 +99,7 @@ CONFIG_DM_DEMO_SHAPE=y CONFIG_DFU_SF=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_SANDBOX_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y @@ -153,7 +153,7 @@ CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_PMIC_MC34708=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_PMIC_SANDBOX=y CONFIG_PMIC_S5M8767=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index 9ee70c29c1..aa8868acba 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -126,7 +126,7 @@ CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y CONFIG_SPL_FIRMWARE=y CONFIG_GPIO_HOG=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_SANDBOX_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y @@ -177,7 +177,7 @@ CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_PMIC_MC34708=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_PMIC_RK8XX=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_PMIC_SANDBOX=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index ec2d26d443..da55d609de 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -127,7 +127,7 @@ CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y CONFIG_SPL_FIRMWARE=y CONFIG_GPIO_HOG=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_SANDBOX_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y @@ -180,7 +180,7 @@ CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_PMIC_MC34708=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_PMIC_RK8XX=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_PMIC_SANDBOX=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 0d946b4ad7..aa701c8111 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -136,7 +136,7 @@ CONFIG_DM_DEMO_SIMPLE=y CONFIG_DM_DEMO_SHAPE=y CONFIG_SPL_FIRMWARE=y CONFIG_GPIO_HOG=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_SANDBOX_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y @@ -185,7 +185,7 @@ CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_PMIC_MC34708=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y CONFIG_PMIC_RK8XX=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_PMIC_SANDBOX=y diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig index 2d07767b61..4f84f5f974 100644 --- a/configs/starqltechn_defconfig +++ b/configs/starqltechn_defconfig @@ -23,10 +23,10 @@ CONFIG_CMD_BMP=y # CONFIG_DM_STDIO is not set CONFIG_CLK=y CONFIG_MSM_GPIO=y -CONFIG_PM8916_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y CONFIG_PINCTRL=y CONFIG_DM_PMIC=y -CONFIG_PMIC_PM8916=y +CONFIG_PMIC_QCOM=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_SPMI_MSM=y CONFIG_DM_VIDEO=y diff --git a/doc/device-tree-bindings/pmic/pm8916.txt b/doc/device-tree-bindings/pmic/pm8916.txt deleted file mode 100644 index 15c598b8c4..0000000000 --- a/doc/device-tree-bindings/pmic/pm8916.txt +++ /dev/null @@ -1,18 +0,0 @@ -Qualcomm pm8916 PMIC - -This PMIC is connected using SPMI bus so should be child of SPMI bus controller. - -Required properties: -- compatible: "qcom,spmi-pmic"; -- reg: SPMI Slave ID, size (ignored) -- #address-cells: 0x1 (peripheral ID) -- #size-cells: 0x1 (size of peripheral register space) - -Example: - -pm8916@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 0x1>; - #address-cells = <0x1>; - #size-cells = <0x1>; -}; diff --git a/doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt b/doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt new file mode 100644 index 0000000000..eb78e3ae77 --- /dev/null +++ b/doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt @@ -0,0 +1,94 @@ + Qualcomm SPMI PMICs multi-function device bindings + +The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084 +PMICs. These PMICs use a QPNP scheme through SPMI interface. +QPNP is effectively a partitioning scheme for dividing the SPMI extended +register space up into logical pieces, and set of fixed register +locations/definitions within these regions, with some of these regions +specifically used for interrupt handling. + +The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are +interfaced to the chip via the SPMI (System Power Management Interface) bus. +Support for multiple independent functions are implemented by splitting the +16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes +each. A function can consume one or more of these fixed-size register regions. + +Required properties: +- compatible: Should contain one of: + "qcom,pm660", + "qcom,pm660l", + "qcom,pm7325", + "qcom,pm8004", + "qcom,pm8005", + "qcom,pm8019", + "qcom,pm8028", + "qcom,pm8110", + "qcom,pm8150", + "qcom,pm8150b", + "qcom,pm8150c", + "qcom,pm8150l", + "qcom,pm8226", + "qcom,pm8350c", + "qcom,pm8841", + "qcom,pm8901", + "qcom,pm8909", + "qcom,pm8916", + "qcom,pm8941", + "qcom,pm8950", + "qcom,pm8953", + "qcom,pm8994", + "qcom,pm8998", + "qcom,pma8084", + "qcom,pmd9635", + "qcom,pmi8950", + "qcom,pmi8962", + "qcom,pmi8994", + "qcom,pmi8998", + "qcom,pmk8002", + "qcom,pmk8350", + "qcom,pmr735a", + "qcom,smb2351", + or generalized "qcom,spmi-pmic". +- reg: Specifies the SPMI USID slave address for this device. + For more information see: + Documentation/devicetree/bindings/spmi/spmi.yaml + +Required properties for peripheral child nodes: +- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name. + +Optional properties for peripheral child nodes: +- interrupts: Interrupts are specified as a 4-tuple. For more information + see: + Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml +- interrupt-names: Corresponding interrupt name to the interrupts property + +Each child node of SPMI slave id represents a function of the PMIC. In the +example below the rtc device node represents a peripheral of pm8941 +SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1. + +Example: + + spmi { + compatible = "qcom,spmi-pmic-arb"; + + pm8941@0 { + compatible = "qcom,pm8941", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + + rtc { + compatible = "qcom,rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm"; + }; + }; + + pm8941@1 { + compatible = "qcom,pm8941", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + + regulator { + compatible = "qcom,regulator"; + regulator-name = "8941_boost"; + }; + }; + }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index aaa152fae7..39dfdac195 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -303,14 +303,14 @@ config CMD_PCA953X legacy GPIO interface. Several subcommands are provided which mirror the standard 'gpio' command. It should use that instead.
-config PM8916_GPIO - bool "Qualcomm PM8916 PMIC GPIO/keypad driver" - depends on DM_GPIO && PMIC_PM8916 +config QCOM_PMIC_GPIO + bool "Qualcomm generic PMIC GPIO/keypad driver" + depends on DM_GPIO && PMIC_QCOM help Support for GPIO pins and power/reset buttons found on - Qualcomm PM8916 PMIC. + Qualcomm SoCs PMIC. Default name for GPIO bank is "pm8916". - Power and reset buttons are placed in "pm8916_key" bank and + Power and reset buttons are placed in "pwkey_qcom" bank and have gpio numbers 0 and 1 respectively.
config PCF8575_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d7552762d0..ff6dcc332f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -64,7 +64,7 @@ obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o -obj-$(CONFIG_$(SPL_TPL_)PM8916_GPIO) += pm8916_gpio.o +obj-$(CONFIG_$(SPL_TPL_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/qcom_pmic_gpio.c similarity index 67% rename from drivers/gpio/pm8916_gpio.c rename to drivers/gpio/qcom_pmic_gpio.c index 7ad95784a8..e9232a007f 100644 --- a/drivers/gpio/pm8916_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Qualcomm pm8916 pmic gpio driver - part of Qualcomm PM8916 PMIC + * Qualcomm generic pmic gpio driver * * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com */ @@ -19,7 +19,7 @@
/* Register maps */
-/* Type and subtype are shared for all pm8916 peripherals */ +/* Type and subtype are shared for all PMIC peripherals */ #define REG_TYPE 0x4 #define REG_SUBTYPE 0x5
@@ -47,14 +47,14 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7)
-struct pm8916_gpio_bank { +struct qcom_gpio_bank { uint32_t pid; /* Peripheral ID on SPMI bus */ };
-static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset, - bool input, int value) +static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, + bool input, int value) { - struct pm8916_gpio_bank *priv = dev_get_priv(dev); + struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); int ret;
@@ -101,20 +101,20 @@ static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset, REG_EN_CTL_ENABLE); }
-static int pm8916_gpio_direction_input(struct udevice *dev, unsigned offset) +static int qcom_gpio_direction_input(struct udevice *dev, unsigned offset) { - return pm8916_gpio_set_direction(dev, offset, true, 0); + return qcom_gpio_set_direction(dev, offset, true, 0); }
-static int pm8916_gpio_direction_output(struct udevice *dev, unsigned offset, - int value) +static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) { - return pm8916_gpio_set_direction(dev, offset, false, value); + return qcom_gpio_set_direction(dev, offset, false, value); }
-static int pm8916_gpio_get_function(struct udevice *dev, unsigned offset) +static int qcom_gpio_get_function(struct udevice *dev, unsigned offset) { - struct pm8916_gpio_bank *priv = dev_get_priv(dev); + struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); int reg;
@@ -134,9 +134,9 @@ static int pm8916_gpio_get_function(struct udevice *dev, unsigned offset) } }
-static int pm8916_gpio_get_value(struct udevice *dev, unsigned offset) +static int qcom_gpio_get_value(struct udevice *dev, unsigned offset) { - struct pm8916_gpio_bank *priv = dev_get_priv(dev); + struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); int reg;
@@ -147,10 +147,10 @@ static int pm8916_gpio_get_value(struct udevice *dev, unsigned offset) return !!(reg & REG_STATUS_VAL_MASK); }
-static int pm8916_gpio_set_value(struct udevice *dev, unsigned offset, - int value) +static int qcom_gpio_set_value(struct udevice *dev, unsigned offset, + int value) { - struct pm8916_gpio_bank *priv = dev_get_priv(dev); + struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
/* Set the output value of the gpio */ @@ -158,17 +158,17 @@ static int pm8916_gpio_set_value(struct udevice *dev, unsigned offset, REG_CTL_OUTPUT_MASK, !!value); }
-static const struct dm_gpio_ops pm8916_gpio_ops = { - .direction_input = pm8916_gpio_direction_input, - .direction_output = pm8916_gpio_direction_output, - .get_value = pm8916_gpio_get_value, - .set_value = pm8916_gpio_set_value, - .get_function = pm8916_gpio_get_function, +static const struct dm_gpio_ops qcom_gpio_ops = { + .direction_input = qcom_gpio_direction_input, + .direction_output = qcom_gpio_direction_output, + .get_value = qcom_gpio_get_value, + .set_value = qcom_gpio_set_value, + .get_function = qcom_gpio_get_function, };
-static int pm8916_gpio_probe(struct udevice *dev) +static int qcom_gpio_probe(struct udevice *dev) { - struct pm8916_gpio_bank *priv = dev_get_priv(dev); + struct qcom_gpio_bank *priv = dev_get_priv(dev); int reg;
priv->pid = dev_read_addr(dev); @@ -187,33 +187,33 @@ static int pm8916_gpio_probe(struct udevice *dev) return 0; }
-static int pm8916_gpio_of_to_plat(struct udevice *dev) +static int qcom_gpio_of_to_plat(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0); uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); if (uc_priv->bank_name == NULL) - uc_priv->bank_name = "pm8916"; + uc_priv->bank_name = "qcom_pmic";
return 0; }
-static const struct udevice_id pm8916_gpio_ids[] = { +static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pm8998-gpio" }, { } };
-U_BOOT_DRIVER(gpio_pm8916) = { - .name = "gpio_pm8916", +U_BOOT_DRIVER(qcom_pmic_gpio) = { + .name = "qcom_pmic_gpio", .id = UCLASS_GPIO, - .of_match = pm8916_gpio_ids, - .of_to_plat = pm8916_gpio_of_to_plat, - .probe = pm8916_gpio_probe, - .ops = &pm8916_gpio_ops, - .priv_auto = sizeof(struct pm8916_gpio_bank), + .of_match = qcom_gpio_ids, + .of_to_plat = qcom_gpio_of_to_plat, + .probe = qcom_gpio_probe, + .ops = &qcom_gpio_ops, + .priv_auto = sizeof(struct qcom_gpio_bank), };
@@ -222,14 +222,14 @@ U_BOOT_DRIVER(gpio_pm8916) = { #define KPDPWR_ON_INT_BIT 0 #define RESIN_ON_INT_BIT 1
-static int pm8941_pwrkey_get_function(struct udevice *dev, unsigned offset) +static int qcom_pwrkey_get_function(struct udevice *dev, unsigned offset) { return GPIOF_INPUT; }
-static int pm8941_pwrkey_get_value(struct udevice *dev, unsigned offset) +static int qcom_pwrkey_get_value(struct udevice *dev, unsigned offset) { - struct pm8916_gpio_bank *priv = dev_get_priv(dev); + struct qcom_gpio_bank *priv = dev_get_priv(dev);
int reg = pmic_reg_read(dev->parent, priv->pid + PON_INT_RT_STS);
@@ -247,14 +247,14 @@ static int pm8941_pwrkey_get_value(struct udevice *dev, unsigned offset) } }
-static const struct dm_gpio_ops pm8941_pwrkey_ops = { - .get_value = pm8941_pwrkey_get_value, - .get_function = pm8941_pwrkey_get_function, +static const struct dm_gpio_ops qcom_pwrkey_ops = { + .get_value = qcom_pwrkey_get_value, + .get_function = qcom_pwrkey_get_function, };
-static int pm8941_pwrkey_probe(struct udevice *dev) +static int qcom_pwrkey_probe(struct udevice *dev) { - struct pm8916_gpio_bank *priv = dev_get_priv(dev); + struct qcom_gpio_bank *priv = dev_get_priv(dev); int reg;
priv->pid = dev_read_addr(dev); @@ -273,31 +273,31 @@ static int pm8941_pwrkey_probe(struct udevice *dev) return 0; }
-static int pm8941_pwrkey_of_to_plat(struct udevice *dev) +static int qcom_pwrkey_of_to_plat(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->gpio_count = 2; uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); if (uc_priv->bank_name == NULL) - uc_priv->bank_name = "pm8916_key"; + uc_priv->bank_name = "pwkey_qcom";
return 0; }
-static const struct udevice_id pm8941_pwrkey_ids[] = { +static const struct udevice_id qcom_pwrkey_ids[] = { { .compatible = "qcom,pm8916-pwrkey" }, { .compatible = "qcom,pm8994-pwrkey" }, { .compatible = "qcom,pm8998-pwrkey" }, { } };
-U_BOOT_DRIVER(pwrkey_pm89xx) = { - .name = "pwrkey_pm89xx", +U_BOOT_DRIVER(pwrkey_qcom) = { + .name = "pwrkey_qcom", .id = UCLASS_GPIO, - .of_match = pm8941_pwrkey_ids, - .of_to_plat = pm8941_pwrkey_of_to_plat, - .probe = pm8941_pwrkey_probe, - .ops = &pm8941_pwrkey_ops, - .priv_auto = sizeof(struct pm8916_gpio_bank), + .of_match = qcom_pwrkey_ids, + .of_to_plat = qcom_pwrkey_of_to_plat, + .probe = qcom_pwrkey_probe, + .ops = &qcom_pwrkey_ops, + .priv_auto = sizeof(struct qcom_gpio_bank), }; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 66b16b06e0..0478f2aa1d 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -216,10 +216,10 @@ config PMIC_MAX8997 - MUIC - Others
-config PMIC_PM8916 - bool "Enable Driver Model for Qualcomm PM8916 PMIC" +config PMIC_QCOM + bool "Enable Driver Model for Qualcomm generic PMIC" ---help--- - The PM8916 is a PMIC connected to one (or several) processors + The Qcom PMIC is connected to one (or several) processors with SPMI bus. It has 2 slaves with several peripherals: - 18x LDO - 4x GPIO @@ -229,7 +229,7 @@ config PMIC_PM8916 - Vibrator drivers - Others
- Driver binding info: doc/device-tree-bindings/pmic/pm8916.txt + Driver binding info: doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt
config PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index f73b326255..e1d3545490 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o obj-$(CONFIG_PMIC_MAX8997) += max8997.o -obj-$(CONFIG_PMIC_PM8916) += pm8916.o +obj-$(CONFIG_PMIC_QCOM) += pmic_qcom.o obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o diff --git a/drivers/power/pmic/pm8916.c b/drivers/power/pmic/pmic_qcom.c similarity index 52% rename from drivers/power/pmic/pm8916.c rename to drivers/power/pmic/pmic_qcom.c index 5f4386d4ad..ad8daf43f0 100644 --- a/drivers/power/pmic/pm8916.c +++ b/drivers/power/pmic/pmic_qcom.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Qualcomm pm8916 pmic driver + * Qualcomm generic pmic driver * * (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com */ @@ -13,19 +13,19 @@ #define PID_MASK (0xFF << PID_SHIFT) #define REG_MASK 0xFF
-struct pm8916_priv { +struct pmic_qcom_priv { uint32_t usid; /* Slave ID on SPMI bus */ };
-static int pm8916_reg_count(struct udevice *dev) +static int pmic_qcom_reg_count(struct udevice *dev) { return 0xFFFF; }
-static int pm8916_write(struct udevice *dev, uint reg, const uint8_t *buff, - int len) +static int pmic_qcom_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) { - struct pm8916_priv *priv = dev_get_priv(dev); + struct pmic_qcom_priv *priv = dev_get_priv(dev);
if (len != 1) return -EINVAL; @@ -35,9 +35,9 @@ static int pm8916_write(struct udevice *dev, uint reg, const uint8_t *buff, *buff); }
-static int pm8916_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +static int pmic_qcom_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { - struct pm8916_priv *priv = dev_get_priv(dev); + struct pmic_qcom_priv *priv = dev_get_priv(dev); int val;
if (len != 1) @@ -52,20 +52,20 @@ static int pm8916_read(struct udevice *dev, uint reg, uint8_t *buff, int len) return 0; }
-static struct dm_pmic_ops pm8916_ops = { - .reg_count = pm8916_reg_count, - .read = pm8916_read, - .write = pm8916_write, +static struct dm_pmic_ops pmic_qcom_ops = { + .reg_count = pmic_qcom_reg_count, + .read = pmic_qcom_read, + .write = pmic_qcom_write, };
-static const struct udevice_id pm8916_ids[] = { +static const struct udevice_id pmic_qcom_ids[] = { { .compatible = "qcom,spmi-pmic" }, { } };
-static int pm8916_probe(struct udevice *dev) +static int pmic_qcom_probe(struct udevice *dev) { - struct pm8916_priv *priv = dev_get_priv(dev); + struct pmic_qcom_priv *priv = dev_get_priv(dev);
priv->usid = dev_read_addr(dev);
@@ -75,12 +75,12 @@ static int pm8916_probe(struct udevice *dev) return 0; }
-U_BOOT_DRIVER(pmic_pm8916) = { - .name = "pmic_pm8916", +U_BOOT_DRIVER(pmic_qcom) = { + .name = "pmic_qcom", .id = UCLASS_PMIC, - .of_match = pm8916_ids, + .of_match = pmic_qcom_ids, .bind = dm_scan_fdt_dev, - .probe = pm8916_probe, - .ops = &pm8916_ops, - .priv_auto = sizeof(struct pm8916_priv), + .probe = pmic_qcom_probe, + .ops = &pmic_qcom_ops, + .priv_auto = sizeof(struct pmic_qcom_priv), };
On Thu, Aug 04, 2022 at 07:57:17PM +0530, Sumit Garg wrote:
Since both pm8916.c and pm8916_gpio.c are already supporting multiple Qcom SoCs, it makes sense to rename these drivers to pmic_qcom.c and qcom_pmic_gpio.c respectively. Also, these driver can be extended to support additional functionality if required for other Qcom SoCs.
Along with this import latest DT binding: qcom,spmi-pmic.txt from Linux kernel and thereby remove pm8916.txt.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes.
With GPIO LV/MV subtype available, add "qcom,pms405-gpio" compatible which requires support for GPIO MV subtype.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/gpio/qcom_pmic_gpio.c | 96 +++++++++++++++++++++++++++-------- 1 file changed, 76 insertions(+), 20 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index e9232a007f..3be1be8692 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -23,6 +23,15 @@ #define REG_TYPE 0x4 #define REG_SUBTYPE 0x5
+/* GPIO peripheral type and subtype out_values */ +#define REG_TYPE_VAL 0x10 +#define REG_SUBTYPE_GPIO_4CH 0x1 +#define REG_SUBTYPE_GPIOC_4CH 0x5 +#define REG_SUBTYPE_GPIO_8CH 0x9 +#define REG_SUBTYPE_GPIOC_8CH 0xd +#define REG_SUBTYPE_GPIO_LV 0x10 +#define REG_SUBTYPE_GPIO_MV 0x11 + #define REG_STATUS 0x08 #define REG_STATUS_VAL_MASK 0x1
@@ -33,6 +42,10 @@ #define REG_CTL_MODE_INOUT 0x20 #define REG_CTL_MODE_OUTPUT 0x10 #define REG_CTL_OUTPUT_MASK 0x0F +#define REG_CTL_LV_MV_MODE_MASK 0x3 +#define REG_CTL_LV_MV_MODE_INPUT 0x0 +#define REG_CTL_LV_MV_MODE_INOUT 0x2 +#define REG_CTL_LV_MV_MODE_OUTPUT 0x1
#define REG_DIG_VIN_CTL 0x41 #define REG_DIG_VIN_VIN0 0 @@ -40,6 +53,10 @@ #define REG_DIG_PULL_CTL 0x42 #define REG_DIG_PULL_NO_PU 0x5
+#define REG_LV_MV_OUTPUT_CTL 0x44 +#define REG_LV_MV_OUTPUT_CTL_MASK 0x80 +#define REG_LV_MV_OUTPUT_CTL_SHIFT 7 + #define REG_DIG_OUT_CTL 0x45 #define REG_DIG_OUT_CTL_CMOS (0x0 << 4) #define REG_DIG_OUT_CTL_DRIVE_L 0x1 @@ -49,6 +66,7 @@
struct qcom_gpio_bank { uint32_t pid; /* Peripheral ID on SPMI bus */ + bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ };
static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, @@ -56,6 +74,7 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, { struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); + uint32_t reg_ctl_val; int ret;
/* Disable the GPIO */ @@ -64,16 +83,31 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, if (ret < 0) return ret;
- /* Select the mode */ - if (input) - ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, - REG_CTL_MODE_INPUT); - else - ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, - REG_CTL_MODE_INOUT | (value ? 1 : 0)); + /* Select the mode and output */ + if (priv->lv_mv_type) { + if (input) + reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT; + else + reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT; + } else { + if (input) + reg_ctl_val = REG_CTL_MODE_INPUT; + else + reg_ctl_val = REG_CTL_MODE_INOUT | !!value; + } + + ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val); if (ret < 0) return ret;
+ if (priv->lv_mv_type && !input) { + ret = pmic_reg_write(dev->parent, + gpio_base + REG_LV_MV_OUTPUT_CTL, + !!value << REG_LV_MV_OUTPUT_CTL_SHIFT); + if (ret < 0) + return ret; + } + /* Set the right pull (no pull) */ ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL, REG_DIG_PULL_NO_PU); @@ -118,19 +152,30 @@ static int qcom_gpio_get_function(struct udevice *dev, unsigned offset) uint32_t gpio_base = priv->pid + REG_OFFSET(offset); int reg;
- /* Set the output value of the gpio */ reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL); if (reg < 0) return reg;
- switch (reg & REG_CTL_MODE_MASK) { - case REG_CTL_MODE_INPUT: - return GPIOF_INPUT; - case REG_CTL_MODE_INOUT: /* Fallthrough */ - case REG_CTL_MODE_OUTPUT: - return GPIOF_OUTPUT; - default: - return GPIOF_UNKNOWN; + if (priv->lv_mv_type) { + switch (reg & REG_CTL_LV_MV_MODE_MASK) { + case REG_CTL_LV_MV_MODE_INPUT: + return GPIOF_INPUT; + case REG_CTL_LV_MV_MODE_INOUT: /* Fallthrough */ + case REG_CTL_LV_MV_MODE_OUTPUT: + return GPIOF_OUTPUT; + default: + return GPIOF_UNKNOWN; + } + } else { + switch (reg & REG_CTL_MODE_MASK) { + case REG_CTL_MODE_INPUT: + return GPIOF_INPUT; + case REG_CTL_MODE_INOUT: /* Fallthrough */ + case REG_CTL_MODE_OUTPUT: + return GPIOF_OUTPUT; + default: + return GPIOF_UNKNOWN; + } } }
@@ -154,8 +199,14 @@ static int qcom_gpio_set_value(struct udevice *dev, unsigned offset, uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
/* Set the output value of the gpio */ - return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL, - REG_CTL_OUTPUT_MASK, !!value); + if (priv->lv_mv_type) + return pmic_clrsetbits(dev->parent, + gpio_base + REG_LV_MV_OUTPUT_CTL, + REG_LV_MV_OUTPUT_CTL_MASK, + !!value << REG_LV_MV_OUTPUT_CTL_SHIFT); + else + return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL, + REG_CTL_OUTPUT_MASK, !!value); }
static const struct dm_gpio_ops qcom_gpio_ops = { @@ -177,13 +228,17 @@ static int qcom_gpio_probe(struct udevice *dev)
/* Do a sanity check */ reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE); - if (reg != 0x10) + if (reg != REG_TYPE_VAL) return log_msg_ret("bad type", -ENXIO);
reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE); - if (reg != 0x5 && reg != 0x1) + if (reg != REG_SUBTYPE_GPIO_4CH && reg != REG_SUBTYPE_GPIOC_4CH && + reg != REG_SUBTYPE_GPIO_LV && reg != REG_SUBTYPE_GPIO_MV) return log_msg_ret("bad subtype", -ENXIO);
+ priv->lv_mv_type = reg == REG_SUBTYPE_GPIO_LV || + reg == REG_SUBTYPE_GPIO_MV; + return 0; }
@@ -203,6 +258,7 @@ static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,pm8998-gpio" }, + { .compatible = "qcom,pms405-gpio" }, { } };
On Thu, Aug 04, 2022 at 07:57:18PM +0530, Sumit Garg wrote:
GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes.
With GPIO LV/MV subtype available, add "qcom,pms405-gpio" compatible which requires support for GPIO MV subtype.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
PMIC GPIOs are special GPIOs which are accessible through SPMI bus. So add corresponding DT nodes.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/dts/qcs404-evb.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 2e3a0c6958..0639af8fe3 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -168,6 +168,31 @@ maximum-speed = "high-speed"; }; }; + + spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000 + 0x2400000 0x400000 + 0x2c00000 0x400000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pms405_0: pms405@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pms405_gpios: pms405_gpios@c000 { + compatible = "qcom,pms405-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + gpio-count = <12>; + #gpio-cells = <2>; + gpio-bank-name="pmic"; + }; + }; + }; }; };
On Thu, Aug 04, 2022 at 07:57:19PM +0530, Sumit Garg wrote:
PMIC GPIOs are special GPIOs which are accessible through SPMI bus. So add corresponding DT nodes.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
For USB3 host controller to detect devices on the bus it is required to enable a PMIC GPIO: usb_vbus_boost_pin. So enable that during board specific initialization.
And since this PMIC GPIO parsing is quite u-boot specific, so add a DT override to qcs404-evb-uboot.dtsi to represent usb_vbus_boost_pin.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/dts/qcs404-evb-uboot.dtsi | 6 ++++++ board/qualcomm/qcs404-evb/qcs404-evb.c | 29 ++++++++++++++++++++++++++ 2 files changed, 35 insertions(+)
diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi index c18080a483..c73d71e8c7 100644 --- a/arch/arm/dts/qcs404-evb-uboot.dtsi +++ b/arch/arm/dts/qcs404-evb-uboot.dtsi @@ -22,3 +22,9 @@ }; }; }; + +&pms405_gpios { + usb_vbus_boost_pin { + gpios = <&pms405_gpios 2 0>; + }; +}; diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c index f1e6e7f7eb..249dca7e72 100644 --- a/board/qualcomm/qcs404-evb/qcs404-evb.c +++ b/board/qualcomm/qcs404-evb/qcs404-evb.c @@ -11,6 +11,7 @@ #include <env.h> #include <init.h> #include <asm/cache.h> +#include <asm/gpio.h> #include <asm/global_data.h> #include <fdt_support.h> #include <asm/arch/dram.h> @@ -24,6 +25,34 @@ int dram_init(void)
int board_init(void) { + struct udevice *pmic_gpio; + struct gpio_desc usb_vbus_boost_pin; + int ret, node; + + ret = uclass_get_device_by_name(UCLASS_GPIO, + "pms405_gpios@c000", + &pmic_gpio); + if (ret < 0) { + printf("Failed to find pms405_gpios@c000 node.\n"); + return ret; + } + + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio), + "usb_vbus_boost_pin"); + if (node < 0) { + printf("Failed to find usb_hub_reset_pm dt node.\n"); + return node; + } + ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &usb_vbus_boost_pin, 0); + if (ret < 0) { + printf("Failed to request usb_hub_reset_pm gpio.\n"); + return ret; + } + + dm_gpio_set_dir_flags(&usb_vbus_boost_pin, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + return 0; }
On Thu, Aug 04, 2022 at 07:57:20PM +0530, Sumit Garg wrote:
For USB3 host controller to detect devices on the bus it is required to enable a PMIC GPIO: usb_vbus_boost_pin. So enable that during board specific initialization.
And since this PMIC GPIO parsing is quite u-boot specific, so add a DT override to qcs404-evb-uboot.dtsi to represent usb_vbus_boost_pin.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Enable USB config options along with its dependencies like PHY, RESET, PMIC GPIO etc. config options.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- configs/qcs404evb_defconfig | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig index d45f6b2348..432d5d50c1 100644 --- a/configs/qcs404evb_defconfig +++ b/configs/qcs404evb_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y # CONFIG_NET is not set CONFIG_CLK=y CONFIG_MMC_HS400_SUPPORT=y @@ -35,4 +36,21 @@ CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_MSM=y CONFIG_PINCTRL=y CONFIG_MSM_SERIAL=y +CONFIG_SPMI_MSM=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_QCOM=y +CONFIG_QCOM_PMIC_GPIO=y +CONFIG_MISC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_DM_RESET=y +CONFIG_RESET_QCOM=y +CONFIG_PHY=y +CONFIG_PHY_QCOM_USB_HS_28NM=y +CONFIG_PHY_QCOM_USB_SS=y CONFIG_LMB_MAX_REGIONS=64
On Thu, Aug 04, 2022 at 07:57:21PM +0530, Sumit Garg wrote:
Enable USB config options along with its dependencies like PHY, RESET, PMIC GPIO etc. config options.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
Applied to u-boot/next, thanks!
Hi,
On Thu, 4 Aug 2022 at 19:57, Sumit Garg sumit.garg@linaro.org wrote:
This series add support for USB on QCS404 SoC. USB support have dependencies on PHY, reset and PMIC GPIO drivers, so corresponding support has been added. There are also some renaming/reorganising patches (#1, #3 and #9) which tries to generalize drivers support for Qcom SoCs.
- Patch #1 moves all Qcom PHY drivers to drivers/phy/qcom/.
- Patch #3 coverts ipq4019 reset driver to a generic Qcom reset driver.
- Patch #9 Convert pm8916 driver to a generic Qcom PMIC driver.
Sumit Garg (13): phy: Move qcom SoCs specific phy drivers to qcom folder phy: Add support for drivers to enable USB on QCS404 SoC reset: Convert ipq4019 driver to a generic Qcom driver reset: qcom: Add support for QCS404 SoC reset table dts: qcs404-evb: Add reset controller node clocks: qcom: Add clock enable callback support clocks: qcs404: Add support for USB clocks dts: qcs404-evb: Add USB controller and PHY nodes pmic: Convert pm8916 driver to a generic Qcom PMIC driver gpio: qcom_pmic: Add support for GPIO LV/MV subtype dts: qcs404-evb: Add PMIC GPIO controller node board: qcs404-evb: Enable USB3 specific PMIC GPIO qcs404evb_defconfig: Enable USB configs
Gentle ping for any further review comments.
-Sumit
arch/arm/dts/qcs404-evb-uboot.dtsi | 6 + arch/arm/dts/qcs404-evb.dts | 118 ++++++ arch/arm/mach-snapdragon/clock-apq8016.c | 5 + arch/arm/mach-snapdragon/clock-apq8096.c | 5 + arch/arm/mach-snapdragon/clock-qcs404.c | 40 ++ arch/arm/mach-snapdragon/clock-sdm845.c | 5 + arch/arm/mach-snapdragon/clock-snapdragon.c | 7 + .../include/mach/sysmap-qcs404.h | 17 + board/qualcomm/qcs404-evb/qcs404-evb.c | 29 ++ configs/dragonboard410c_defconfig | 4 +- configs/dragonboard820c_defconfig | 4 +- configs/dragonboard845c_defconfig | 4 +- configs/qcs404evb_defconfig | 18 + configs/sandbox64_defconfig | 4 +- configs/sandbox_defconfig | 4 +- configs/sandbox_flattree_defconfig | 4 +- configs/sandbox_noinst_defconfig | 4 +- configs/sandbox_spl_defconfig | 4 +- configs/sandbox_vpl_defconfig | 4 +- configs/starqltechn_defconfig | 4 +- doc/device-tree-bindings/pmic/pm8916.txt | 18 - .../pmic/qcom,spmi-pmic.txt | 94 +++++ drivers/gpio/Kconfig | 10 +- drivers/gpio/Makefile | 2 +- drivers/gpio/pm8916_gpio.c | 303 --------------- drivers/gpio/qcom_pmic_gpio.c | 359 ++++++++++++++++++ drivers/phy/Kconfig | 15 +- drivers/phy/Makefile | 3 +- drivers/phy/qcom/Kconfig | 29 ++ drivers/phy/qcom/Makefile | 4 + drivers/phy/{ => qcom}/msm8916-usbh-phy.c | 0 drivers/phy/{ => qcom}/phy-qcom-ipq4019-usb.c | 0 drivers/phy/qcom/phy-qcom-usb-hs-28nm.c | 250 ++++++++++++ drivers/phy/qcom/phy-qcom-usb-ss.c | 154 ++++++++ drivers/power/pmic/Kconfig | 8 +- drivers/power/pmic/Makefile | 2 +- drivers/power/pmic/{pm8916.c => pmic_qcom.c} | 42 +- drivers/reset/Kconfig | 9 +- drivers/reset/Makefile | 2 +- .../reset/{reset-ipq4019.c => reset-qcom.c} | 76 +++- 40 files changed, 1254 insertions(+), 416 deletions(-) delete mode 100644 doc/device-tree-bindings/pmic/pm8916.txt create mode 100644 doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt delete mode 100644 drivers/gpio/pm8916_gpio.c create mode 100644 drivers/gpio/qcom_pmic_gpio.c create mode 100644 drivers/phy/qcom/Kconfig create mode 100644 drivers/phy/qcom/Makefile rename drivers/phy/{ => qcom}/msm8916-usbh-phy.c (100%) rename drivers/phy/{ => qcom}/phy-qcom-ipq4019-usb.c (100%) create mode 100644 drivers/phy/qcom/phy-qcom-usb-hs-28nm.c create mode 100644 drivers/phy/qcom/phy-qcom-usb-ss.c rename drivers/power/pmic/{pm8916.c => pmic_qcom.c} (52%) rename drivers/reset/{reset-ipq4019.c => reset-qcom.c} (64%)
-- 2.25.1
participants (3)
-
Robert Marko -
Sumit Garg -
Tom Rini