Re: [PATCH v3] spl: introduce SPL_XIP to config

From: Nikita Shubin nikita.shubin@maquefel.me Sent: Friday, September 02, 2022 4:48 PM To: u-boot@lists.denx.de Cc: linux@yadro.com; Sean Anderson seanga2@gmail.com; Rick Chen rickchen36@gmail.com; Nikita Shubin n.shubin@yadro.com; Rick Jian-Zhi Chen(陳建志) rick@andestech.com; Leo Yu-Chi Liang(梁育齊) ycliang@andestech.com; Simon Glass sjg@chromium.org; Bin Meng bmeng.cn@gmail.com; Ilias Apalodimas ilias.apalodimas@linaro.org; Heinrich Schuchardt xypron.glpk@gmx.de Subject: [PATCH v3] spl: introduce SPL_XIP to config
From: Nikita Shubin n.shubin@yadro.com
U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.
In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics.
The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.
This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess.
Signed-off-by: Nikita Shubin n.shubin@yadro.com
v2->v3: Rick Chen: - move SPL_XIP to arch/riscv/Kconfig right after XIP - change ae350_spl defconfig's to use SPL_XIP instead of XIP
arch/riscv/Kconfig | 7 +++++++ arch/riscv/cpu/cpu.c | 2 +- arch/riscv/cpu/start.S | 4 ++-- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/asm-offsets.c | 2 +- arch/riscv/lib/smp.c | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- 8 files changed, 15 insertions(+), 8 deletions(-)
Reviewed-by: Rick Chen rick@andestech.com
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Rick Chen