From: Markus Niebel Markus.Niebel@tq-group.com

according to

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14802.htm...

and the clarification given by Marc Rutland of ARM

data cache invalidation should go from outer to inner cache. This patch corrects the order in

flush_dcache_range flush_dcache_all

Signed-off-by: Markus Niebel Markus.Niebel@tq-group.com --- arch/arm/cpu/armv7/cache_v7.c | 8 ++++---- include/configs/tqma6.h | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a5aa4fa..81eb286 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -235,9 +235,9 @@ static void v7_inval_tlb(void)

void invalidate_dcache_all(void) { - v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); - v7_outer_cache_inval_all(); + + v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); }

/* @@ -257,9 +257,9 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); - v7_outer_cache_inval_range(start, stop); + + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); }

/* diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index f7fade1..0a0cbbe 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -111,10 +111,11 @@

#define CONFIG_ARP_TIMEOUT 200UL /* Network config - Allow larger/faster download for TFTP/NFS */ +/* #define CONFIG_IP_DEFRAG #define CONFIG_TFTP_BLOCKSIZE 4096 #define CONFIG_NFS_READ_SIZE 4096 - +*/ /* Command definition */ #define CONFIG_CMD_BMODE