-----Original Message----- From: Z.q. Hou zhiqiang.hou@nxp.com Sent: Tuesday, December 17, 2019 3:41 PM To: u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com; M.h. Lian minghuan.lian@nxp.com Cc: Z.q. Hou zhiqiang.hou@nxp.com Subject: [PATCH 2/2] pci: layerscape: Fix the BARs disable function

From: Hou Zhiqiang Zhiqiang.Hou@nxp.com

There is not any difference for disabling BARs in RC mode between PCIe controllers with and without SRIOV.

Fixes: 80afc63fc342 ("pci: layerscape: add pci driver based on DM") Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com

---

drivers/pci/pcie_layerscape.c | 11 ----------- 1 file changed, 11 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 96533cb2d9..d8ca7e71f8 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -312,17 +312,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) /* Disable all bars in RC mode */ static void ls_pcie_disable_bars(struct ls_pcie *pcie) {

• u32 sriov;
• sriov = in_le32(pcie->dbi + PCIE_SRIOV);
• /*

• * TODO: For PCIe controller with SRIOV, the method to disable bars
  

• * is different and more complex, so will add later.
  

• */
  

Patch description and code comment statement looks contradictory. Is method to disable BAR same or different for with and without SRIOV.

• if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)

• return;
  

• dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0); dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1); dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);

-- 2.17.1

Priyanka