Yuli,

Thanks very much for your instruction. It seems I move further, however I still do not make Ethernet port2 works fine. Following is the my modification and the symptom.

1) I changed the BCSRs bit FETHIEN2 to 0, reset the Ethernet Port2 (Phy addr 3) to enable auto-negatiation. Now, the MII reg0 = 0x3100, reg1=0x782D. IP Addr 172.18.100.54 does exist. when I enable FCC2 and ping 172.18.100.54, ping success. When I "ping 172.18.100.54", the message "fex: tx error" is gone. It seems TX is fine. Is it correct?

2) However, "ping 172.18.100.54" fail. the message "ping failed; host 172.18.100.54" is not alive. FCC3 Rx Clock is set to CLK15. PortB4~17, PortC16~17 are enabled. I added a debug message to fec_recv(...) in cpu\mpc8260\ether_fcc.c, as follows.

static int fec_recv(struct eth_device* dev) { int length;

for (;;) { if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { length = -1; #ifdef ET_DEBUG printf("%s::%s Nothing Rcv\n", __FILE__, __FUNCTION__); /*Added Debug*/ #endif break; /* nothing received - leave for() loop */ } ..... }

I got "ether_fcc.c::fec_recv Nothing Rcv" message.

The following few lines for the CPM clock route in added in include\configs\MPC8260ADS.h: #if (CONFIG_ETHER_INDEX == 3) /* * - Rx-CLK is CLK15 * - Tx-CLK is CLK16 * - Select bus for bd/buffers (see 28-13) * - Full duplex */ # define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) #endif /* CONFIG_ETHER_INDEX */

Ethernet port2 dedicated Pin setting for PortB 4~17 and PortC 17~17 are enabled. The definition in board\mpc8260ads\mpc8260ads.c is shown as follows: /* Port B configuration */ { /* conf ppar psor pdir podr pdat */ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV*/ /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ },

/* Port C */ { /* conf ppar psor pdir podr pdat */ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* RX Clk15*/ /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* Tx Clock (CLK16) */ /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ },

Thanks a lot!

Regards,

Charles

-----Original Message----- From: Yuli Barcohen [mailto:yuli@arabellasw.com] Sent: Monday, July 19, 2004 8:47 AM To: Jihua Cheng Cc: u-boot-users@lists.sourceforge.net Subject: RE: [U-Boot-Users] PQ2FADS-VR 2nd Ethernet

...

...

...

...

Jihua Cheng writes:

Jihua> Yuli, Thanks very much!

Jihua> Here is the sympotoms.

Jihua> Based on the PQ2FADS-VR schematic, I route parallel portC pin Jihua> PC17(Clk 15 for RX) and pin PC16(Clk16 for TX) for Jihua> FCC3. PortB PB4~PB17 are enabled for FCC3. When I use ping Jihua> command, I got "fec: tx error!" message in the console. I Jihua> found the message is from fec_send(...) at Jihua> cpu/mpc8260/ether_fcc.c. It seems CPM did not send out the Jihua> data to Phy.

This usually indicates that there is no Tx clock, probably because the PHY does not provide it.

Jihua> 1) I check BCSR3. Both FETHIEN2 and FETH2_RST are 1.

FETHIEN2=1 means that the PHY is isolated after power-up. This is not what you want. Set FETHIEN2 to zero and reset PHY by toggling FETH2_RST.

Jihua> 2) Phy Register seems OK (Reg0 = 0x2100, reg1 = 0x7809).

It's not completely OK because auto-negotiation is disabled. It's can be a result of above mentioned isolation. Check what happens after enabling the PHY, and set as necessary.

Jihua> 3) I check PortB PB4~PB17. Dedicated Pin setting seems OK.

Jihua> Where do I need to check?

Jihua> I appreciate your help!