[U-Boot] [PATCH 00/11] ARMV7: OMAP: Add support for OMAP36XX/37XX, cleanup OMAP3 common code

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Steve Sakoman

1 Sep 2010 1 Sep '10

1:21 a.m.

This patch series adds support for TI's OMAP36XX/377XX processors and modifies the Beagle and Overo board files to support upcoming versions of these boards based upon processors from the OMAP36XX/37XX families.

A number of cleanups and bug fixes to generic OMAP3 code are also included since they were discovered during the process of adding this support.

This patch depends on the previous series:

ARMV7: OMAP3: Board updates for Beagle and Overo

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/82805

Tested on Beagle C3, C4, and xM; Overo 35XX and 37XX; and Panda Also did MAKEALL ARMV7

Mans Rullgard (3): ARMV7: OMAP3: Fix and clean up L2 cache enable/disable functions ARMV7: OMAP3: Convert setup_auxcr() to pure asm ARMV7: OMAP3: Apply Cortex-A8 errata workarounds only on affected revisions

Steve Sakoman (8): ARMV7: OMAP3: Update CPU type detection for AM35XX/OMAP36XX/37XX ARMV7: OMAP3: Add clock setup for OMAP36XX/37XX ARMV7: OMAP3: Fix broken reset command on OMAP36XX/37XX and OMAP4 ARMV7: OMAP3: Remove erroneous hard coded sdram setup for 128MB/bank mtd: nand: honor CONFIG_SYS_NAND_QUIET_TEST with unknown NAND printk ARMV7: OMAP3: Add CONFIG_SYS_NAND_QUIET_TEST to Beagle and Overo configs ARMV7: OMAP3: Add support for Beagle xM ARMV7: OMAP: Overo: Autodetect presence/absence of transceiver on mmc2

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Steve Sakoman

1 Sep 1 Sep

1:21 a.m.

New subject: [U-Boot] [PATCH 01/11] ARMV7: OMAP3: Update CPU type detection for AM35XX/OMAP36XX/37XX

TI has added new processors to the OMAP3 family. This patch enhances the code in sysinfo.c to detect which family member is present.

Signed-off-by: Steve Sakoman steve@sakoman.com --- arch/arm/cpu/armv7/omap3/sys_info.c | 147 ++++++++++++++++++++++----- arch/arm/include/asm/arch-omap3/cpu.h | 14 ++-- arch/arm/include/asm/arch-omap3/omap3.h | 32 ++++++- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 + 4 files changed, 161 insertions(+), 34 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 1df4401..549ac19 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -38,7 +38,10 @@ static char *rev_s[CPU_3XX_MAX_REV] = { "2.0", "2.1", "3.0", - "3.1"}; + "3.1", + "UNKNOWN", + "UNKNOWN", + "3.1.2"};

/***************************************************************** * dieid_num_r(void) - read and set die ID @@ -75,32 +78,81 @@ u32 get_cpu_type(void) }

/****************************************** - * get_cpu_rev(void) - extract version info + * get_cpu_id(void) - extract cpu id + * returns 0 for ES1.0, cpuid otherwise ******************************************/ -u32 get_cpu_rev(void) +u32 get_cpu_id(void) { - u32 cpuid = 0; struct ctrl_id *id_base; + u32 cpuid = 0;

/* * On ES1.0 the IDCODE register is not exposed on L4 * so using CPU ID to differentiate between ES1.0 and > ES1.0. */ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); - if ((cpuid & 0xf) == 0x0) - return CPU_3XX_ES10; - else { + if ((cpuid & 0xf) == 0x0) { + return 0; + } else { /* Decode the IDs on > ES1.0 */ id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;

- cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf; + cpuid = readl(&id_base->idcode); + }

- /* Some early ES2.0 seem to report ID 0, fix this */ - if(cpuid == 0) - cpuid = CPU_3XX_ES20; + return cpuid; +}

- return cpuid; +/****************************************** + * get_cpu_family(void) - extract cpu info + ******************************************/ +u32 get_cpu_family(void) +{ + u16 hawkeye; + u32 cpu_family; + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_OMAP34XX; + + hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; + switch (hawkeye) { + case HAWKEYE_OMAP34XX: + cpu_family = CPU_OMAP34XX; + break; + case HAWKEYE_AM35XX: + cpu_family = CPU_AM35XX; + break; + case HAWKEYE_OMAP36XX: + cpu_family = CPU_OMAP36XX; + break; + default: + cpu_family = CPU_OMAP34XX; } + + return cpu_family; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_3XX_ES10; + else + return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf; +} + +/***************************************************************** + * get_sku_id(void) - read sku_id to get info on max clock rate + *****************************************************************/ +u32 get_sku_id(void) +{ + struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; + return readl(&id_base->sku_id) & SKUID_CLK_MASK; }

/*************************************************************************** @@ -213,24 +265,66 @@ u32 get_device_type(void) */ int print_cpuinfo (void) { - char *cpu_s, *sec_s; + char *cpu_family_s, *cpu_s, *sec_s, *max_clk; + + switch (get_cpu_family()) { + case CPU_OMAP34XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3503: + cpu_s = "3503"; + break; + case OMAP3515: + cpu_s = "3515"; + break; + case OMAP3525: + cpu_s = "3525"; + break; + case OMAP3530: + cpu_s = "3530"; + break; + default: + cpu_s = "35XX"; + break; + } + if ((get_cpu_rev() >= CPU_3XX_ES31) && + (get_sku_id() == SKUID_CLK_720MHZ)) + max_clk = "720 mHz"; + else + max_clk = "600 mHz";

- switch (get_cpu_type()) { - case OMAP3503: - cpu_s = "3503"; break; - case OMAP3515: - cpu_s = "3515"; + case CPU_AM35XX: + cpu_family_s = "AM"; + switch (get_cpu_type()) { + case AM3505: + cpu_s = "3505"; + break; + case AM3517: + cpu_s = "3517"; + break; + default: + cpu_s = "35XX"; + break; + } + max_clk = "600 Mhz"; break; - case OMAP3525: - cpu_s = "3525"; - break; - case OMAP3530: - cpu_s = "3530"; + case CPU_OMAP36XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3730: + cpu_s = "3630/3730"; + break; + default: + cpu_s = "36XX/37XX"; + break; + } + max_clk = "1 Ghz"; break; default: + cpu_family_s = "OMAP"; cpu_s = "35XX"; - break; + max_clk = "600 Mhz"; }

switch (get_device_type()) { @@ -250,8 +344,9 @@ int print_cpuinfo (void) sec_s = "?"; }

- printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n", - cpu_s, sec_s, rev_s[get_cpu_rev()]); + printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", + cpu_family_s, cpu_s, sec_s, + rev_s[get_cpu_rev()], max_clk);

return 0; } diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 390b007..99da756 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -60,19 +60,14 @@ struct ctrl { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */

-/* cpu type */ -#define OMAP3503 0x5c00 -#define OMAP3515 0x1c00 -#define OMAP3525 0x4c00 -#define OMAP3530 0x0c00 - #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct ctrl_id { u8 res1[0x4]; u32 idcode; /* 0x04 */ u32 prod_id; /* 0x08 */ - u8 res2[0x0C]; + u32 sku_id; /* 0x0c */ + u8 res2[0x08]; u32 die_id_0; /* 0x18 */ u32 die_id_1; /* 0x1C */ u32 die_id_2; /* 0x20 */ @@ -89,6 +84,11 @@ struct ctrl_id { #define HS_DEVICE 0x2 #define GP_DEVICE 0x3

+/* device speed */ +#define SKUID_CLK_MASK 0xf +#define SKUID_CLK_600MHZ 0x0 +#define SKUID_CLK_720MHZ 0x8 + #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 12815f6..3957c79 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -176,11 +176,41 @@ struct gpio { #define CPU_3XX_ES21 2 #define CPU_3XX_ES30 3 #define CPU_3XX_ES31 4 -#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1) +#define CPU_3XX_ES312 7 +#define CPU_3XX_MAX_REV 8

#define CPU_3XX_ID_SHIFT 28

#define WIDTH_8BIT 0x0000 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */

+/* + * Hawkeye values + */ +#define HAWKEYE_OMAP34XX 0xb7ae +#define HAWKEYE_AM35XX 0xb868 +#define HAWKEYE_OMAP36XX 0xb891 + +#define HAWKEYE_SHIFT 12 + +/* + * Define CPU families + */ +#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ +#define CPU_AM35XX 0x3500 /* AM35xx devices */ +#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ + +/* + * Control status register values corresponding to cpu variants + */ +#define OMAP3503 0x5c00 +#define OMAP3515 0x1c00 +#define OMAP3525 0x4c00 +#define OMAP3530 0x0c00 + +#define AM3505 0x5c00 +#define AM3517 0x1c00 + +#define OMAP3730 0x0c00 + #endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index db7b42a..4a28ba1 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -41,7 +41,9 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, void watchdog_init(void); void set_muxconf_regs(void);

+u32 get_cpu_family(void); u32 get_cpu_rev(void); +u32 get_sku_id(void); u32 get_mem_type(void); u32 get_sysboot_value(void); u32 is_gpmc_muxed(void);

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 02/11] ARMV7: OMAP3: Add clock setup for OMAP36XX/37XX

This patch configures clocks properly when a 36XX/37XX processor is detected.

Signed-off-by: Steve Sakoman steve@sakoman.com --- arch/arm/cpu/armv7/omap3/clock.c | 549 +++++++++++++++++------- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 69 +++ arch/arm/include/asm/arch-omap3/clocks.h | 17 + arch/arm/include/asm/arch-omap3/clocks_omap3.h | 27 ++ 4 files changed, 515 insertions(+), 147 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 6330c9e..2238c52 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -50,12 +50,7 @@ u32 get_osc_clk_speed(void)

if (val & SYSCLKDIV_2) cdiv = 2; - else if (val & SYSCLKDIV_1) - cdiv = 1; else - /* - * Should never reach here! (Assume divider as 1) - */ cdiv = 1;

/* enable timer2 */ @@ -89,11 +84,7 @@ u32 get_osc_clk_speed(void) while (readl(&s32k_base->s32k_cr) < (start + 20)) ; cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ cdiff = cend - cstart; /* get elapsed ticks */ - - if (cdiv == 2) - { - cdiff *= 2; - } + cdiff *= cdiv;

/* based on number of ticks assign speed */ if (cdiff > 19000) @@ -135,65 +126,22 @@ void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) } }

-/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) +/* + * OMAP34XX/35XX specific functions + */ + +static void dpll3_init_34xx(u32 sil_index, u32 clk_index) { + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_core_dpll_param(); void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; - u32 osc_clk = 0, sys_clkin_sel; - u32 clk_index, sil_index = 0; - struct prm *prm_base = (struct prm *)PRM_BASE; - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - dpll_param *dpll_param_p; - - f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE);

xip_safe = is_running_in_sram();

- /* - * Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - /* set input crystal speed */ - sr32(&prm_base->clksel, 0, 3, sys_clkin_sel); + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index;

- /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - /* input clock divider */ - sr32(&prm_base->clksrc_ctrl, 6, 2, 2); - clk_index = sys_clkin_sel / 2; - } else { - /* input clock divider */ - sr32(&prm_base->clksrc_ctrl, 6, 2, 1); - clk_index = sys_clkin_sel; - } - - /* - * The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if (get_cpu_rev()) - sil_index = 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; if (xip_safe) { /* * CORE DPLL @@ -208,34 +156,38 @@ void prcm_init(void) * work. write another value and then default value. */

- /* m3x2 */ - sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1); - /* m3x2 */ + /* CM_CLKSEL1_EMU[DIV_DPLL3] */ + sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ; sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); - /* Set M2 */ - sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2); - /* Set M */ - sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m); - /* Set N */ - sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n); - /* 96M Src */ + + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2); + + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m); + + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n); + + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ sr32(&prcm_base->clksel1_pll, 6, 1, 0); - /* ssi */ + + /* SSI */ sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); - /* fsusb */ + /* FSUSB */ sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); - /* l4 */ + /* L4 */ sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); - /* l3 */ + /* L3 */ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); - /* gfx */ - sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); - /* reset mgr */ + /* GFX */ + sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + /* RESET MGR */ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); - /* FREQSEL */ - sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel); - /* lock mode */ - sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); + /* LOCK MODE */ + sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);

wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, LDELAY); @@ -244,102 +196,405 @@ void prcm_init(void) * if running from flash, jump to small relocated code * area in SRAM. */ + f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + + SRAM_VECT_CODE); + p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); - sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&p0, 4, 4, ptr->fsel);

p1 = readl(&prcm_base->clksel1_pll); - sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */ - sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */ - sr32(&p1, 6, 1, 0); /* set source for 96M */ + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&p1, 27, 5, ptr->m2); + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&p1, 16, 11, ptr->m); + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&p1, 8, 7, ptr->n); + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + sr32(&p1, 6, 1, 0);

p2 = readl(&prcm_base->clksel_core); - sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */ + /* SSI */ + sr32(&p2, 8, 4, CORE_SSI_DIV); + /* FSUSB */ + sr32(&p2, 4, 2, CORE_FUSB_DIV); + /* L4 */ + sr32(&p2, 2, 2, CORE_L4_DIV); + /* L3 */ + sr32(&p2, 0, 2, CORE_L3_DIV);

p3 = (u32)&prcm_base->idlest_ckgen;

(*f_lock_pll) (p0, p1, p2, p3); } +}

- /* PER DPLL */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); - wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); - - /* Getting the base address to PER DPLL param table */ - - /* Set N */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); +static void dpll4_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_per_dpll_param();

/* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; + ptr = ptr + clk_index; + + /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); + wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);

/* * Errata 1.50 Workaround for OMAP3 ES1.0 only * If using default divisors, write default divisor + 1 * and then the actual divisor value */ - sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */ - sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */ - sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */ - sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */ - sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */ - sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */ - sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */ - sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */ - sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */ - sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */ + /* M6 */ + sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1)); + sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); + /* M5 */ + sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1)); + sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); + /* M4 */ + sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1)); + sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); + /* M3 */ + sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1)); + sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); + /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ + sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1)); + sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2); /* Workaround end */

- sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */ - sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */ - sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */ + /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */ + sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m); + + /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ + sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n); + + /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */ + sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel); + + /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); +}

- /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); +static void mpu_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();

- /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index;

/* MPU DPLL (unlocked already) */

- /* Set M2 */ - sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2); - /* Set M */ - sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m); - /* Set N */ - sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n); - /* FREQSEL */ - sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel); - /* lock mode */ - sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); - wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* IVA DPLL (set to 12*20=240MHz) */ + /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ + sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2); + + /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ + sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m); + + /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ + sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n); + + /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */ + sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel); +} + +static void iva_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_iva_dpll_param(); + + /* Moving to the right sysclk and ES rev base */ + ptr = ptr + (3 * clk_index) + sil_index; + + /* IVA DPLL */ + /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ + sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP); + wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); + + /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ + sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2); + + /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ + sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m); + + /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ + sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n); + + /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */ + sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel); + + /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ + sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK); + + wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); +} + +/* + * OMAP3630 specific functions + */ + +static void dpll3_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param(); + void (*f_lock_pll) (u32, u32, u32, u32); + int xip_safe, p0, p1, p2, p3; + + xip_safe = is_running_in_sram(); + + /* Moving it to the right sysclk base */ + ptr += clk_index; + + if (xip_safe) { + /* CORE DPLL */ + + /* Select relock bypass: CM_CLKEN_PLL[0:2] */ + sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, + LDELAY); + + /* CM_CLKSEL1_EMU[DIV_DPLL3] */ + sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); + + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2); + + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m); + + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n); + + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + sr32(&prcm_base->clksel1_pll, 6, 1, 0); + + /* SSI */ + sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); + /* FSUSB */ + sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); + /* L4 */ + sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); + /* L3 */ + sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); + /* GFX */ + sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + /* RESET MGR */ + sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); + /* LOCK MODE */ + sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); + + wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, + LDELAY); + } else if (is_running_in_flash()) { + /* + * if running from flash, jump to small relocated code + * area in SRAM. + */ + f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + + SRAM_VECT_CODE); + + p0 = readl(&prcm_base->clken_pll); + sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); + /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ + sr32(&p0, 4, 4, ptr->fsel); + + p1 = readl(&prcm_base->clksel1_pll); + /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ + sr32(&p1, 27, 5, ptr->m2); + /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ + sr32(&p1, 16, 11, ptr->m); + /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ + sr32(&p1, 8, 7, ptr->n); + /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ + sr32(&p1, 6, 1, 0); + + p2 = readl(&prcm_base->clksel_core); + /* SSI */ + sr32(&p2, 8, 4, CORE_SSI_DIV); + /* FSUSB */ + sr32(&p2, 4, 2, CORE_FUSB_DIV); + /* L4 */ + sr32(&p2, 2, 2, CORE_L4_DIV); + /* L3 */ + sr32(&p2, 0, 2, CORE_L3_DIV); + + p3 = (u32)&prcm_base->idlest_ckgen; + + (*f_lock_pll) (p0, p1, p2, p3); + } +} + +static void dpll4_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + struct dpll_per_36x_param *ptr; + + ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr += clk_index; + + /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); + wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); + + /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */ + sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6); + + /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */ + sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5); + + /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */ + sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4); + + /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */ + sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3); + + /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ + sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2); + + /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */ + sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m); + + /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ + sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n); + + /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */ + sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div); + + /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); + wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); +} + +static void mpu_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param(); + + /* Moving to the right sysclk */ + ptr += clk_index; + + /* MPU DPLL (unlocked already */ + + /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ + sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2); + + /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */ + sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m); + + /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ + sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n); +} + +static void iva_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param(); + + /* Moving to the right sysclk */ + ptr += clk_index; + + /* IVA DPLL */ + /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP); wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); - /* set M2 */ - sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2); - /* set M */ - sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m); - /* set N */ - sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n); - /* FREQSEL */ - sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel); - /* lock mode */ + + /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ + sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2); + + /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */ + sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m); + + /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ + sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n); + + /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK); + wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY); +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk = 0, sys_clkin_sel; + u32 clk_index, sil_index = 0; + struct prm *prm_base = (struct prm *)PRM_BASE; + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + + /* + * Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + /* set input crystal speed */ + sr32(&prm_base->clksel, 0, 3, sys_clkin_sel); + + /* If the input clock is greater than 19.2M always divide/2 */ + if (sys_clkin_sel > 2) { + /* input clock divider */ + sr32(&prm_base->clksrc_ctrl, 6, 2, 2); + clk_index = sys_clkin_sel / 2; + } else { + /* input clock divider */ + sr32(&prm_base->clksrc_ctrl, 6, 2, 1); + clk_index = sys_clkin_sel; + } + + if (get_cpu_family() == CPU_OMAP36XX) { + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, + LDELAY); + + dpll3_init_36xx(0, clk_index); + dpll4_init_36xx(0, clk_index); + iva_init_36xx(0, clk_index); + mpu_init_36xx(0, clk_index); + + /* Lock MPU DPLL to set frequency */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, + LDELAY); + } else { + /* + * The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + if (((get_cpu_family() == CPU_OMAP34XX) + && (get_cpu_rev() >= CPU_3XX_ES20)) || + (get_cpu_family() == CPU_AM35XX)) + sil_index = 1; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, + LDELAY); + + dpll3_init_34xx(sil_index, clk_index); + dpll4_init_34xx(sil_index, clk_index); + iva_init_34xx(sil_index, clk_index); + mpu_init_34xx(sil_index, clk_index); + + /* Lock MPU DPLL to set frequency */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, + LDELAY); + }

/* Set up GPTimers to sys_clk source only */ sr32(&prcm_base->clksel_per, 0, 8, 0xff); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 73063ec..91c6dbc 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -359,3 +359,72 @@ per_dpll_param: get_per_dpll_param: adr r0, per_dpll_param mov pc, lr + +/* + * Tables for 36XX/37XX devices + * + */ +mpu_36x_dpll_param: +/* 12MHz */ +.word 50, 0, 0, 1 +/* 13MHz */ +.word 600, 12, 0, 1 +/* 19.2MHz */ +.word 125, 3, 0, 1 +/* 26MHz */ +.word 300, 12, 0, 1 +/* 38.4MHz */ +.word 125, 7, 0, 1 + +iva_36x_dpll_param: +/* 12MHz */ +.word 130, 2, 0, 1 +/* 13MHz */ +.word 20, 0, 0, 1 +/* 19.2MHz */ +.word 325, 11, 0, 1 +/* 26MHz */ +.word 10, 0, 0, 1 +/* 38.4MHz */ +.word 325, 23, 0, 1 + +core_36x_dpll_param: +/* 12MHz */ +.word 100, 2, 0, 1 +/* 13MHz */ +.word 400, 12, 0, 1 +/* 19.2MHz */ +.word 375, 17, 0, 1 +/* 26MHz */ +.word 200, 12, 0, 1 +/* 38.4MHz */ +.word 375, 35, 0, 1 + +per_36x_dpll_param: +/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */ +.word 12000, 360, 4, 9, 16, 5, 4, 3, 1 +.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 +.word 19200, 360, 7, 9, 16, 5, 4, 3, 1 +.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 +.word 38400, 360, 15, 9, 16, 5, 4, 3, 1 + +.globl get_36x_mpu_dpll_param +get_36x_mpu_dpll_param: + adr r0, mpu_36x_dpll_param + mov pc, lr + +.globl get_36x_iva_dpll_param +get_36x_iva_dpll_param: + adr r0, iva_36x_dpll_param + mov pc, lr + +.globl get_36x_core_dpll_param +get_36x_core_dpll_param: + adr r0, core_36x_dpll_param + mov pc, lr + +.globl get_36x_per_dpll_param +get_36x_per_dpll_param: + adr r0, per_36x_dpll_param + mov pc, lr + diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h index 71a0cb6..40f80ba 100644 --- a/arch/arm/include/asm/arch-omap3/clocks.h +++ b/arch/arm/include/asm/arch-omap3/clocks.h @@ -51,12 +51,29 @@ typedef struct { unsigned int m2; } dpll_param;

+struct dpll_per_36x_param { + unsigned int sys_clk; + unsigned int m; + unsigned int n; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m2div; +}; + /* Following functions are exported from lowlevel_init.S */ extern dpll_param *get_mpu_dpll_param(void); extern dpll_param *get_iva_dpll_param(void); extern dpll_param *get_core_dpll_param(void); extern dpll_param *get_per_dpll_param(void);

+extern dpll_param *get_36x_mpu_dpll_param(void); +extern dpll_param *get_36x_iva_dpll_param(void); +extern dpll_param *get_36x_core_dpll_param(void); +extern dpll_param *get_36x_per_dpll_param(void); + extern void *_end_vect, *_start;

#endif diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index 661407b..30ef690 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -282,4 +282,31 @@ #define PER_FSEL_38P4 0x07 #define PER_M2_38P4 0x09

+/* 36XX PER DPLL */ + +#define PER_36XX_M_12 0x1B0 +#define PER_36XX_N_12 0x05 +#define PER_36XX_FSEL_12 0x07 +#define PER_36XX_M2_12 0x09 + +#define PER_36XX_M_13 0x360 +#define PER_36XX_N_13 0x0C +#define PER_36XX_FSEL_13 0x03 +#define PER_36XX_M2_13 0x09 + +#define PER_36XX_M_19P2 0x1C2 +#define PER_36XX_N_19P2 0x09 +#define PER_36XX_FSEL_19P2 0x07 +#define PER_36XX_M2_19P2 0x09 + +#define PER_36XX_M_26 0x1B0 +#define PER_36XX_N_26 0x0C +#define PER_36XX_FSEL_26 0x07 +#define PER_36XX_M2_26 0x09 + +#define PER_36XX_M_38P4 0x1C2 +#define PER_36XX_N_38P4 0x13 +#define PER_36XX_FSEL_38P4 0x07 +#define PER_36XX_M2_38P4 0x09 + #endif /* endif _CLOCKS_OMAP3_H_ */

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 03/11] ARMV7: OMAP3: Fix and clean up L2 cache enable/disable functions

From: Mans Rullgard mans@mansr.com

On OMAP34xx ES1.0, the L2 enable bit can only be set in secure mode, so an SMC call to the ROM monitor is required. On later versions, and on newer devices, this bit is banked and we can set it directly.

The code checked only the ES revision of the chip, and hence incorrectly used the ROM call on ES1.0 versions of other devices.

This patch adds a check for chip family as well as revision, and also removes some code duplication between the enable and disable functions.

Signed-off-by: Mans Rullgard mans@mansr.com Signed-off-by: Steve Sakoman steve@sakoman.com --- arch/arm/cpu/armv7/omap3/cache.S | 75 +++++++++++--------------------------- 1 files changed, 21 insertions(+), 54 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S index 4b65ac5..cb7ca11 100644 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -128,64 +128,31 @@ finished_inval:

ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}

- -l2_cache_enable: - stmfd r13!, {r0, r1, r2, lr} - @ ES2 onwards we can disable/enable L2 ourselves +l2_cache_set: + stmfd r13!, {r4 - r6, lr} + mov r5, r0 bl get_cpu_rev - cmp r0, #CPU_3XX_ES20 - blt l2_cache_disable_EARLIER_THAN_ES2 - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - b l2_cache_enable_END -l2_cache_enable_EARLIER_THAN_ES2: - @ Save r0, r12 and restore them after usage - mov r3, ip - str r3, [sp, #4] - mov r3, r0 - @ + mov r4, r0 + bl get_cpu_family + @ ES2 onwards we can disable/enable L2 ourselves + cmp r0, #CPU_OMAP34XX + cmpeq r4, #CPU_3XX_ES10 + mrc 15, 0, r0, cr1, cr0, 1 + bic r0, r0, #2 + orr r0, r0, r5, lsl #1 + mcreq 15, 0, r0, cr1, cr0, 1 @ GP Device ROM code API usage here @ r12 = AUXCR Write function and r0 value - @ mov ip, #3 - mrc 15, 0, r0, cr1, cr0, 1 - orr r0, r0, #2 - @ SMI instruction to call ROM Code API - .word 0xe1600070 - mov r0, r3 - mov ip, r3 - str r3, [sp, #4] -l2_cache_enable_END: - ldmfd r13!, {r1, r2, r3, pc} + @ SMCNE instruction to call ROM Code API + .word 0x11600070 + ldmfd r13!, {r4 - r6, pc}

+l2_cache_enable: + mov r0, #1 + b l2_cache_set

l2_cache_disable: - stmfd r13!, {r0, r1, r2, lr} - @ ES2 onwards we can disable/enable L2 ourselves - bl get_cpu_rev - cmp r0, #CPU_3XX_ES20 - blt l2_cache_disable_EARLIER_THAN_ES2 - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - b l2_cache_disable_END -l2_cache_disable_EARLIER_THAN_ES2: - @ Save r0, r12 and restore them after usage - mov r3, ip - str r3, [sp, #4] - mov r3, r0 - @ - @ GP Device ROM code API usage here - @ r12 = AUXCR Write function and r0 value - @ - mov ip, #3 - mrc 15, 0, r0, cr1, cr0, 1 - bic r0, r0, #2 - @ SMI instruction to call ROM Code API - .word 0xe1600070 - mov r0, r3 - mov ip, r3 - str r3, [sp, #4] -l2_cache_disable_END: - ldmfd r13!, {r1, r2, r3, pc} + mov r0, #0 + b l2_cache_set +

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 04/11] ARMV7: OMAP3: Convert setup_auxcr() to pure asm

From: Mans Rullgard mans@mansr.com

This function consists entirely of inline asm statements, so writing it directly in a .S file is simpler. Additionally, the inline asm is not safe as is, since registers are not guaranteed to be preserved between asm() statements.

Signed-off-by: Mans Rullgard mans@mansr.com Signed-off-by: Steve Sakoman steve@sakoman.com --- arch/arm/cpu/armv7/omap3/board.c | 35 ----------------------------------- arch/arm/cpu/armv7/omap3/cache.S | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 35 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 69e56f5..6c2a132 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -120,41 +120,6 @@ void secureworld_exit() }

/****************************************************************************** - * Routine: setup_auxcr() - * Description: Write to AuxCR desired value using SMI. - * general use. - *****************************************************************************/ -void setup_auxcr() -{ - unsigned long i; - volatile unsigned int j; - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - /* Enabling ASA */ - __asm__ __volatile__("orr r0, r0, #0x10"); - /* Enable L1NEON */ - __asm__ __volatile__("orr r0, r0, #1 << 5"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */ - __asm__ __volatile__("mov r12, #0x2"); - __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2"); - __asm__ __volatile__("orr r0, r0, #1 << 27"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); -} - -/****************************************************************************** * Routine: try_unlock_sram() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S index cb7ca11..5a19051 100644 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -43,6 +43,7 @@ .global invalidate_dcache .global l2_cache_enable .global l2_cache_disable +.global setup_auxcr

/* * invalidate_dcache() @@ -156,3 +157,21 @@ l2_cache_disable: mov r0, #0 b l2_cache_set

+/****************************************************************************** + * Routine: setup_auxcr() + * Description: Write to AuxCR desired value using SMI. + * general use. + *****************************************************************************/ +setup_auxcr: + mov r12, #0x3 + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x10 @ Enable ASA + orr r0, r0, #1 << 5 @ Enable L1NEON + .word 0xE1600070 @ SMC + mov r12, #0x2 + mrc p15, 1, r0, c9, c0, 2 + @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) + orr r0, r0, #1 << 27 + .word 0xE1600070 @ SMC + bx lr +

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 05/11] ARMV7: OMAP3: Apply Cortex-A8 errata workarounds only on affected revisions

From: Mans Rullgard mans@mansr.com

The workarounds for errata 621766 and 725233 should only be applied on affected Cortex-A8 revisions. Recent chips use r3px cores where these have been fixed.

Signed-off-by: Mans Rullgard mans@mansr.com Signed-off-by: Steve Sakoman steve@sakoman.com --- arch/arm/cpu/armv7/omap3/cache.S | 13 ++++++++++--- 1 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S index 5a19051..24e950f 100644 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -163,15 +163,22 @@ l2_cache_disable: * general use. *****************************************************************************/ setup_auxcr: + mrc p15, 0, r0, c0, c0, 0 @ read main ID register + and r2, r0, #0x00f00000 @ variant + and r3, r0, #0x0000000f @ revision + orr r1, r3, r2, lsr #20-4 @ combine variant and revision mov r12, #0x3 mrc p15, 0, r0, c1, c0, 1 orr r0, r0, #0x10 @ Enable ASA - orr r0, r0, #1 << 5 @ Enable L1NEON + @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround) + cmp r1, #0x21 + orrlt r0, r0, #1 << 5 .word 0xE1600070 @ SMC mov r12, #0x2 mrc p15, 1, r0, c9, c0, 2 - @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) - orr r0, r0, #1 << 27 + @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround) + cmp r1, #0x21 + orrlt r0, r0, #1 << 27 .word 0xE1600070 @ SMC bx lr

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 06/11] ARMV7: OMAP3: Fix broken reset command on OMAP36XX/37XX and OMAP4

Using the reset command on OMAP36XX/37XX and OMAP4 caused a hang. This patch uses the reset bit appropriate for each CPU architecture.

Signed-off-by: Steve Sakoman steve@sakoman.com --- arch/arm/cpu/armv7/omap-common/reset.S | 4 +++- arch/arm/include/asm/arch-omap3/cpu.h | 1 + arch/arm/include/asm/arch-omap4/omap4.h | 1 + 3 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S index a53c408..838b122 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.S +++ b/arch/arm/cpu/armv7/omap-common/reset.S @@ -27,10 +27,12 @@ reset_cpu: ldr r1, rstctl @ get addr for global reset @ reg - mov r3, #0x2 @ full reset pll + mpu + ldr r3, rstbit @ sw reset bit str r3, [r1] @ force reset mov r0, r0 _loop_forever: b _loop_forever rstctl: .word PRM_RSTCTRL +rstbit: + .word PRM_RSTCTRL_RESET diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 99da756..962d6d4 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -419,6 +419,7 @@ struct prm { }; #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL 0x48307250 +#define PRM_RSTCTRL_RESET 0x04 #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */

diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h index 79ff22c..d0c808d 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap4.h @@ -88,6 +88,7 @@ #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)

#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01

#ifndef __ASSEMBLY__

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 07/11] ARMV7: OMAP3: Remove erroneous hard coded sdram setup for 128MB/bank

Upcoming Beagle and Overo revisions use POP memory with 256MB or 512MB per bank. This patches uses the SDRC settings from x-load or the config header to set up timing properly.

Signed-off-by: Steve Sakoman steve@sakoman.com --- arch/arm/cpu/armv7/omap3/sdrc.c | 43 +++++++++++++++++++-------------------- 1 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 96fd990..8905224 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -107,18 +107,12 @@ u32 get_sdr_cs_offset(u32 cs) /* * do_sdrc_init - * - Initialize the SDRAM for use. - * - Sets up SDRC timings for CS0 * - code called once in C-Stack only context for CS0 and a possible 2nd * time depending on memory configuration from stack+global context */ void do_sdrc_init(u32 cs, u32 early) { - struct sdrc_actim *sdrc_actim_base; - - if (cs) - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - else - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;

if (early) { /* reset sdrc controller */ @@ -138,24 +132,29 @@ void do_sdrc_init(u32 cs, u32 early) sdelay(0x20000); }

- writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | - RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | - DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); - writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); - writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); - writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); - - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - /* - * CAS latency 3, Write Burst = Read Burst, Serial Mode, - * Burst length = 4 + * SDRC timings are set up by x-load or config header + * We don't need to redo them here. + * Older x-loads configure only CS0 + * configure CS1 to handle this ommission */ - writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr); + if (cs) { + sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + writel(readl(&sdrc_base->cs[CS0].mcfg), + &sdrc_base->cs[CS1].mcfg); + writel(readl(&sdrc_base->cs[CS0].rfr_ctrl), + &sdrc_base->cs[CS1].rfr_ctrl); + writel(readl(&sdrc_actim_base0->ctrla), + &sdrc_actim_base1->ctrla); + writel(readl(&sdrc_actim_base0->ctrlb), + &sdrc_actim_base1->ctrlb); + }

+ /* + * Test ram in this bank + * Disable if bad or not present + */ if (!mem_ok(cs)) writel(0, &sdrc_base->cs[cs].mcfg); }

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 08/11] mtd: nand: honor CONFIG_SYS_NAND_QUIET_TEST with unknown NAND printk

This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

Signed-off-by: Steve Sakoman steve@sakoman.com --- drivers/mtd/nand/nand_base.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..cbcf2b8 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,9 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) { +#ifndef CONFIG_SYS_NAND_QUIET_TEST printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" " 0x%02x, Chip ID: 0x%02x\n", __func__, *maf_id, dev_id); +#endif return ERR_PTR(-ENODEV); }

-- 1.7.0.4

Paulraj, Sandeep

2:18 a.m.

New subject: [U-Boot] [PATCH 08/11] mtd: nand: honor CONFIG_SYS_NAND_QUIET_TEST with unknown NAND printk

...

This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

Scott,

What do you think of this patch?

...

Signed-off-by: Steve Sakoman steve@sakoman.com

drivers/mtd/nand/nand_base.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..cbcf2b8 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,9 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) { +#ifndef CONFIG_SYS_NAND_QUIET_TEST printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" " 0x%02x, Chip ID: 0x%02x\n", __func__, *maf_id, dev_id); +#endif return ERR_PTR(-ENODEV); }

-- 1.7.0.4

Scott Wood

6:26 p.m.

New subject: [U-Boot] [PATCH 08/11] mtd: nand: honor CONFIG_SYS_NAND_QUIET_TEST with unknown NAND printk

On Tue, 31 Aug 2010 19:18:27 -0500 "Paulraj, Sandeep" s-paulraj@ti.com wrote:

...

...
This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

[snip]

...

...
if (!type) { +#ifndef CONFIG_SYS_NAND_QUIET_TEST printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" " 0x%02x, Chip ID: 0x%02x\n", __func__, *maf_id, dev_id); +#endif return ERR_PTR(-ENODEV); }

Hmm, the current use of that seems to be suppressing warnings about NAND that isn't present at all, not about NAND whose type we don't recognize.

Perhaps we could instead suppress the warning only for probably-invalid values such as 0x00 and 0xff, if that's how a missing NAND chip manifests?

-Scott

Steve Sakoman

6:43 p.m.

New subject: [U-Boot] [PATCH 08/11] mtd: nand: honor CONFIG_SYS_NAND_QUIET_TEST with unknown NAND printk

On Wed, 2010-09-01 at 11:26 -0500, Scott Wood wrote:

...

On Tue, 31 Aug 2010 19:18:27 -0500 "Paulraj, Sandeep" s-paulraj@ti.com wrote:

...
...
This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

[snip]

...
...
if (!type) { +#ifndef CONFIG_SYS_NAND_QUIET_TEST printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" " 0x%02x, Chip ID: 0x%02x\n", __func__, *maf_id, dev_id); +#endif return ERR_PTR(-ENODEV); }

Hmm, the current use of that seems to be suppressing warnings about NAND that isn't present at all, not about NAND whose type we don't recognize.

Well, that is precisely the case for new Beagle's and Overo's -- these boards do not have nand and output this error.

So perhaps the real issue is that "no nand" is being reported as having a manufacturer id of 0x00 and device id of 0x00 ?

...

Perhaps we could instead suppress the warning only for probably-invalid values such as 0x00 and 0xff, if that's how a missing NAND chip manifests?

That would also be acceptable to me. Is this your preferred fix?

Steve

Scott Wood

7:55 p.m.

New subject: [U-Boot] [PATCH 08/11] mtd: nand: honor CONFIG_SYS_NAND_QUIET_TEST with unknown NAND printk

On Wed, 1 Sep 2010 09:43:17 -0700 Steve Sakoman steve@sakoman.com wrote:

...

On Wed, 2010-09-01 at 11:26 -0500, Scott Wood wrote:

...
Hmm, the current use of that seems to be suppressing warnings about NAND that isn't present at all, not about NAND whose type we don't recognize.

Well, that is precisely the case for new Beagle's and Overo's -- these boards do not have nand and output this error.

Right, I just don't want to end up suppressing the message if there's a real flash that just needs an ID table update.

...

...
Perhaps we could instead suppress the warning only for probably-invalid values such as 0x00 and 0xff, if that's how a missing NAND chip manifests?

That would also be acceptable to me. Is this your preferred fix?

Yes.

-Scott

Steve Sakoman

2 Sep 2 Sep

5:33 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

Signed-off-by: Steve Sakoman steve@sakoman.com --- drivers/mtd/nand/nand_base.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..b2400dd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,8 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) { - printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:" - " 0x%02x, Chip ID: 0x%02x\n", __func__, + /* supress warning if there is no nand */ + if ((*maf_id != 0x00) && (*maf_id != 0xff) && + (dev_id != 0x00) && (dev_id != 0xff)) + printk(KERN_INFO "%s: unknown NAND device: " + "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", __func__, *maf_id, dev_id); return ERR_PTR(-ENODEV); }

-- 1.7.0.4

Paulraj, Sandeep

4 Sep 4 Sep

7:38 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

...

This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

Signed-off-by: Steve Sakoman steve@sakoman.com

Steve,

A proper patch would be very much appreciated instead of an updated patch within an e-mail chain.

Scott,

Is it ok if I add this to my tree?

Its part of a 11 patch series and a total of some 20 patches submitted by Steve

...

drivers/mtd/nand/nand_base.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..b2400dd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,8 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) {
printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:"
       " 0x%02x, Chip ID: 0x%02x\n", __func__,
/* supress warning if there is no nand */
if ((*maf_id != 0x00) && (*maf_id != 0xff) &&
    (dev_id  != 0x00) && (dev_id  != 0xff))
	printk(KERN_INFO "%s: unknown NAND device: "
       "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", __func__,
  *maf_id, dev_id);
return ERR_PTR(-ENODEV); }
-- 1.7.0.4

Regards, Sandeep

Steve Sakoman

10:16 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

On Sat, 2010-09-04 at 12:38 -0500, Paulraj, Sandeep wrote:

...

...
This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

Signed-off-by: Steve Sakoman steve@sakoman.com

Steve,

A proper patch would be very much appreciated instead of an updated patch within an e-mail chain.

Sandeep,

I've updated my omap4-next-upstream branch with the new version of this patch series (it also contains the previous series):

http://www.sakoman.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=shortlog;h=refs/hea...

Would you like me to resubmit the entire series as a v2? The subject patch is the only one that has changed.

Steve

Scott Wood

7 Sep 7 Sep

7:37 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

On Sat, 4 Sep 2010 12:38:34 -0500 "Paulraj, Sandeep" s-paulraj@ti.com wrote:

...

Scott,

Is it ok if I add this to my tree?

Yes, once the whitespace is fixed.

...

Its part of a 11 patch series and a total of some 20 patches submitted by Steve

...
drivers/mtd/nand/nand_base.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..b2400dd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,8 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) {
printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:"
       " 0x%02x, Chip ID: 0x%02x\n", __func__,
/* supress warning if there is no nand */
if ((*maf_id != 0x00) && (*maf_id != 0xff) &&
    (dev_id  != 0x00) && (dev_id  != 0xff))
	printk(KERN_INFO "%s: unknown NAND device: "
       "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", __func__,
  *maf_id, dev_id);
return ERR_PTR(-ENODEV);

printk's continuation lines need one more tab.

-Scott

Steve Sakoman

11:27 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

On Sat, Sep 4, 2010 at 10:38 AM, Paulraj, Sandeep s-paulraj@ti.com wrote:

...

...
This printk was added recently and results in ugly output on systems with no NAND:

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

instead of:

NAND: 0 MiB

Signed-off-by: Steve Sakoman steve@sakoman.com

Steve,

A proper patch would be very much appreciated instead of an updated patch within an e-mail chain.

OK, I will send a revised V3 patch this afternoon which includes the paren and white space changes requested by Scott.

I've also updated the patch in my omap4-next-upstream branch:

http://www.sakoman.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=4700ca...

Steve

Sergei Shtylyov

5 Sep 5 Sep

12:59 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

Hello.

On 02-09-2010 19:33, Steve Sakoman wrote:

...

This printk was added recently and results in ugly output on systems with no NAND:

...

NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

...

instead of:

...

NAND: 0 MiB

...

Signed-off-by: Steve Sakomansteve@sakoman.com

drivers/mtd/nand/nand_base.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-)

...

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..b2400dd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,8 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) {
printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:"
       " 0x%02x, Chip ID: 0x%02x\n", __func__,
/* supress warning if there is no nand */
if ((*maf_id != 0x00)&&  (*maf_id != 0xff)&&
    (dev_id  != 0x00)&&  (dev_id  != 0xff))

Parens around != are not necessary.

WBR, Sergei

Steve Sakoman

11:37 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

On Sun, Sep 5, 2010 at 3:59 AM, Sergei Shtylyov sshtylyov@mvista.com wrote:

...

Hello.

On 02-09-2010 19:33, Steve Sakoman wrote:

...
This printk was added recently and results in ugly output on systems with no NAND:

...
NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB

...
instead of:

...
NAND: 0 MiB

...
Signed-off-by: Steve Sakomansteve@sakoman.com

drivers/mtd/nand/nand_base.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-)

...
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..b2400dd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,8 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) {

printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:"

" 0x%02x, Chip ID: 0x%02x\n", __func__,

/* supress warning if there is no nand */

if ((*maf_id != 0x00) && (*maf_id != 0xff) &&

(dev_id != 0x00) && (dev_id != 0xff))

Parens around != are not necessary.

Understood -- I just think it is easier to read/understand with parens. If the general consensus is that I should remove them I am happy to do so.

Steve

Scott Wood

7 Sep 7 Sep

7:37 p.m.

New subject: [U-Boot] [PATCH V2 08/11] mtd: nand: supress 'unknown NAND' warning if no nand is found

On Sun, 5 Sep 2010 14:37:13 -0700 Steve Sakoman sakoman@gmail.com wrote:

...

On Sun, Sep 5, 2010 at 3:59 AM, Sergei Shtylyov sshtylyov@mvista.com wrote:

...
On 02-09-2010 19:33, Steve Sakoman wrote:

...
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ed1c9c9..b2400dd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2653,8 +2653,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, }

if (!type) {

printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:"

" 0x%02x, Chip ID: 0x%02x\n", __func__,

/* supress warning if there is no nand */

if ((*maf_id != 0x00) && (*maf_id != 0xff) &&

(dev_id != 0x00) && (dev_id != 0xff))

Parens around != are not necessary.

Understood -- I just think it is easier to read/understand with parens. If the general consensus is that I should remove them I am happy to do so.

My vote is no parens.

-Scott

Steve Sakoman

1 Sep 1 Sep

1:21 a.m.

New subject: [U-Boot] [PATCH 09/11] ARMV7: OMAP3: Add CONFIG_SYS_NAND_QUIET_TEST to Beagle and Overo configs

Future versions of these boards have options for POP memory with no NAND. This option prevents display of error messages when no NAND is detected.

Signed-off-by: Steve Sakoman steve@sakoman.com --- include/configs/omap3_beagle.h | 1 + include/configs/omap3_overo.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index e7cd93b..71553f9 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -158,6 +158,7 @@ /* * Board NAND Info. */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index ca90786..a0e0f24 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -129,6 +129,7 @@ /* * Board NAND Info. */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 10/11] ARMV7: OMAP3: Add support for Beagle xM

This patch adds support for the Beagle xM. It uses the board ID GPIO bits to recognize this revision and perform appropriate setup.

Signed-off-by: Steve Sakoman steve@sakoman.com --- board/ti/beagle/beagle.c | 16 ++++++++++++++-- board/ti/beagle/beagle.h | 33 ++++++++++++++++++++++++++++++--- 2 files changed, 44 insertions(+), 5 deletions(-)

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index ec95ad0..4647908 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -58,12 +58,13 @@ int board_init(void) /* * Routine: get_board_revision * Description: Detect if we are running on a Beagle revision Ax/Bx, - * C1/2/3, or C4. This can be done by reading + * C1/2/3, C4 or xM. This can be done by reading * the level of GPIO173, GPIO172 and GPIO171. This should * result in * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 + * GPIO173, GPIO172, GPIO171: 0 0 0 => xM */ int get_board_revision(void) { @@ -115,7 +116,7 @@ int misc_init_r(void) break; case REVISION_C4: printf("Beagle Rev C4\n"); - setenv("beaglerev", "Cx"); + setenv("beaglerev", "C4"); setenv("mpurate", "720"); MUX_BEAGLE_C(); /* Set VAUX2 to 1.8V for EHCI PHY */ @@ -124,6 +125,17 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); break; + case REVISION_XM: + printf("Beagle xM Rev A\n"); + setenv("beaglerev", "xMA"); + setenv("mpurate", "1000"); + MUX_BEAGLE_XM(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; default: printf("Beagle unknown 0x%02x\n", get_board_revision()); } diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index e5f380c..d860337 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -37,6 +37,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_AXBX 0x7 #define REVISION_CX 0x6 #define REVISION_C4 0x5 +#define REVISION_XM 0x0

/* * IEN - Input Enable @@ -377,11 +378,37 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/

#define MUX_BEAGLE_C() \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/

+#define MUX_BEAGLE_XM() \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ + MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ + MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ + MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ + MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ + MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ + #endif

-- 1.7.0.4

Steve Sakoman

1:21 a.m.

New subject: [U-Boot] [PATCH 11/11] ARMV7: OMAP: Overo: Autodetect presence/absence of transceiver on mmc2

An upcoming version of Overo uses a Wifi/BT module with 1.8V signaling, eliminating the need for an external transceiver to handle the level shifting. This patch detects whether an external transceiver is present and adjusts the pinmux settings as appropriate.

Signed-off-by: Steve Sakoman steve@sakoman.com --- board/overo/overo.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ board/overo/overo.h | 35 +++++++++++++++++++++++++++++++++-- 2 files changed, 80 insertions(+), 2 deletions(-)

diff --git a/board/overo/overo.c b/board/overo/overo.c index 4a60917..1b67f1f 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -103,6 +103,39 @@ int get_board_revision(void) }

/* + * Routine: get_sdio2_config + * Description: Return information about the wifi module connection + * Returns 0 if the module connects though a level translator + * Returns 1 if the module connects directly + */ +int get_sdio2_config(void) +{ + int sdio_direct; + + if (!omap_request_gpio(130) && !omap_request_gpio(139)) { + + omap_set_gpio_direction(130, 0); + omap_set_gpio_direction(139, 1); + + sdio_direct = 1; + omap_set_gpio_dataout(130, 0); + if (omap_get_gpio_datain(139) == 0) { + omap_set_gpio_dataout(130, 1); + if (omap_get_gpio_datain(139) == 1) + sdio_direct = 0; + } + + omap_free_gpio(130); + omap_free_gpio(139); + } else { + printf("Error: unable to acquire sdio2 clk GPIOs\n"); + sdio_direct = -1; + } + + return sdio_direct; +} + +/* * Routine: misc_init_r * Description: Configure board specific parts */ @@ -116,6 +149,20 @@ int misc_init_r(void) #endif

printf("Board revision: %d\n", get_board_revision()); + + switch (get_sdio2_config()) { + case 0: + printf("Tranceiver detected on mmc2\n"); + MUX_OVERO_SDIO2_TRANSCEIVER(); + break; + case 1: + printf("Direct connection on mmc2\n"); + MUX_OVERO_SDIO2_DIRECT(); + break; + default: + printf("Unable to detect mmc2 connection type\n"); + } + dieid_num_r();

return 0; diff --git a/board/overo/overo.h b/board/overo/overo.h index 2744ffe..33a92e4 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -211,7 +211,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ /*Wireless LAN */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ @@ -220,7 +220,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ /*Bluetooth*/\ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ @@ -387,5 +387,36 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/

+#define MUX_OVERO_SDIO2_DIRECT() \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/ + +#define MUX_OVERO_SDIO2_TRANSCEIVER() \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/

#endif

-- 1.7.0.4

Steve Sakoman

1:35 a.m.

New subject: [U-Boot] [PATCH 00/11] ARMV7: OMAP: Add support for OMAP36XX/37XX, cleanup OMAP3 common code

On Tue, 2010-08-31 at 16:21 -0700, Steve Sakoman wrote:

...

This patch series adds support for TI's OMAP36XX/377XX processors and modifies the Beagle and Overo board files to support upcoming versions of these boards based upon processors from the OMAP36XX/37XX families.

A number of cleanups and bug fixes to generic OMAP3 code are also included since they were discovered during the process of adding this support.

This patch depends on the previous series:

ARMV7: OMAP3: Board updates for Beagle and Overo

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/82805

Both this series and the one mentioned above are also available in the omap4-next-upstream branch of my repository:

http://www.sakoman.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=shortlog;h=refs/hea...

Steve

Paulraj, Sandeep

2:20 a.m.

New subject: [U-Boot] [PATCH 00/11] ARMV7: OMAP: Add support for OMAP36XX/37XX, cleanup OMAP3 common code

...

On Tue, 2010-08-31 at 16:21 -0700, Steve Sakoman wrote:

...
This patch series adds support for TI's OMAP36XX/377XX processors and modifies the Beagle and Overo board files to support upcoming versions of these boards based upon processors from the OMAP36XX/37XX families.

A number of cleanups and bug fixes to generic OMAP3 code are also included since they were discovered during the process of adding this support.

This patch depends on the previous series:

ARMV7: OMAP3: Board updates for Beagle and Overo

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/82805

Both this series and the one mentioned above are also available in the omap4-next-upstream branch of my repository:

http://www.sakoman.com/cgi-bin/gitweb.cgi?p=u- boot.git;a=shortlog;h=refs/heads/omap4-next-upstream

Steve

Thanks,

I am taking a look at the entire series.

There are a couple of patches which I obviously cannot add by myself.

Sandeep

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Paulraj, Sandeep
Scott Wood
Sergei Shtylyov
Steve Sakoman
Steve Sakoman