All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec.

Signed-off-by: Kumar Gala galak@kernel.crashing.org ---

Can you guys ack and decide who will actually apply this.

- k

board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +- board/sbc8548/sbc8548.c | 2 +- board/sbc8641d/sbc8641d.c | 4 ++-- cpu/mpc85xx/spd_sdram.c | 4 ++-- cpu/mpc86xx/spd_sdram.c | 4 ++-- include/asm-ppc/immap_85xx.h | 2 +- include/asm-ppc/immap_86xx.h | 2 +- include/configs/MPC8610HPCD.h | 2 +- include/configs/sbc8641d.h | 2 +- 10 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index d9a740e..3a855b5 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -192,7 +192,7 @@ long int fixed_sdram(void) ddr->cs0_bnds = 0x0000001f; ddr->cs0_config = 0x80010202;

- ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_3 = 0x00000000; ddr->timing_cfg_0 = 0x00260802; ddr->timing_cfg_1 = 0x3935d322; ddr->timing_cfg_2 = 0x14904cc8; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 31e7d67..bb1f927 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -130,7 +130,7 @@ fixed_sdram(void)

ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; ddr->timing_cfg_0 = CFG_DDR_TIMING_0; ddr->timing_cfg_1 = CFG_DDR_TIMING_1; ddr->timing_cfg_2 = CFG_DDR_TIMING_2; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 8a6ced3..46496da 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -299,7 +299,7 @@ long int fixed_sdram (void) ddr->cs1_config = 0x80010101; ddr->cs2_config = 0x00000000; ddr->cs3_config = 0x00000000; - ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_3 = 0x00000000; ddr->timing_cfg_0 = 0x00220802; ddr->timing_cfg_1 = 0x38377322; ddr->timing_cfg_2 = 0x0fa044C7; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index b3dd9c8..519f332 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -135,7 +135,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR_CS1_CONFIG; ddr->cs2_config = CFG_DDR_CS2_CONFIG; ddr->cs3_config = CFG_DDR_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; ddr->timing_cfg_0 = CFG_DDR_TIMING_0; ddr->timing_cfg_1 = CFG_DDR_TIMING_1; ddr->timing_cfg_2 = CFG_DDR_TIMING_2; @@ -166,7 +166,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR2_CS1_CONFIG; ddr->cs2_config = CFG_DDR2_CS2_CONFIG; ddr->cs3_config = CFG_DDR2_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH; ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 435458a..e3a8249 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -610,8 +610,8 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + ddr->timing_cfg_3 = (trfc_high << 16); + debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);

ddr->timing_cfg_1 = (0 diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 60a7818..8485841 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, /* * Sneak in some Extended Refresh Recovery. */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + ddr->timing_cfg_3 = (trfc_high << 16); + debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);

ddr->timing_cfg_1 = (0 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index dc6e278..813be5f 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -92,7 +92,7 @@ typedef struct ccsr_ddr { uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ char res5[48]; - uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 7526061..fd4aa54 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -109,7 +109,7 @@ typedef struct ccsr_ddr { uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 9e70198..585411c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -114,7 +114,7 @@ #if 0 /* TODO */ #define CFG_DDR_CS0_BNDS 0x0000000F #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ -#define CFG_DDR_EXT_REFRESH 0x00000000 +#define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 0x00260802 #define CFG_DDR_TIMING_1 0x3935d322 #define CFG_DDR_TIMING_2 0x14904cc8 diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 18cedff..20da73e 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -136,7 +136,7 @@ #define CFG_DDR_CS1_CONFIG 0x00000000 #define CFG_DDR_CS2_CONFIG 0x00000000 #define CFG_DDR_CS3_CONFIG 0x00000000 - #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 0x00220802 #define CFG_DDR_TIMING_1 0x38377322 #define CFG_DDR_TIMING_2 0x002040c7