[PATCH v6 0/3] ARM: imx6: dh-imx6: Enable d-cache early in SPL
This patch series enables d-cache in SPL for i.MX6 based boards from DH in order to improve boot time.
This can only be achieved after migrating the corresponding symbols to Kconfig, which is done in patch 1/3 and 2/3.
Changes in v6: - Once more improve the dcache_disable() comment
Changes in v5: - Clarify dcache_disable() comment
Changes in v4: - Reduce diffstat by using 'select' statements for omap2, mvebu and mx6 based boards - Elaborate on dcache_disable() comment
Changes in v3: - Introduce CONFIG_SPL_SYS_L2_PL310 - Convert CONFIG_SYS_L2_PL310 to Kconfig - Use newly introduced Kconfig symbol for dh_imx6_defconfig
Changes in v2: - Add comment to explain the relevance of dcache_disable()
Marek Vasut (1): ARM: imx6: dh-imx6: Enable d-cache early in SPL
Philip Oberfichtner (2): Convert CONFIG_SYS_L2_PL310 to Kconfig ARM: cache: Allow SPL to build cache-pl310.c
README | 2 -- arch/arm/Kconfig | 10 ++++++ arch/arm/lib/Makefile | 2 +- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/include/mach/config.h | 2 -- arch/arm/mach-omap2/Kconfig | 1 + board/dhelectronics/dh_imx6/dh_imx6_spl.c | 41 +++++++++++++++++++++++ configs/dh_imx6_defconfig | 1 + configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/poleg_evb_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/stemmy_defconfig | 1 + include/configs/am43xx_evm.h | 1 - include/configs/brppt2.h | 1 - include/configs/cm_t43.h | 1 - include/configs/mx6_common.h | 1 - include/configs/odroid.h | 1 - include/configs/poleg.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stemmy.h | 1 - include/configs/ti_omap4_common.h | 1 - include/configs/trats.h | 1 - include/configs/trats2.h | 1 - include/configs/zynq-common.h | 1 - scripts/config_whitelist.txt | 1 - 41 files changed, 75 insertions(+), 18 deletions(-)
This converts CONFIG_SYS_L2_PL310 to Kconfig.
For omap2 and mvebu the 'select SYS_L2_PL310' locations were determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310.
For mx6 I manually chose ARCH_MX6 as 'select' location. The correctness has been verified using
$ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF 0 matches
That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert the 'select' statement under ARCH_MX6.
Signed-off-by: Philip Oberfichtner pro@denx.de --- I wonder if we could further reduce the diffstat by using 'select' for all the socfpga boards. I did not find an appropriate way - I'm open for suggestions, though.
(no changes since v4)
Changes in v4: - Reduce diffstat by using 'select' statements for omap2, mvebu and mx6 based boards
Changes in v3: new
README | 2 -- arch/arm/Kconfig | 5 +++++ arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/include/mach/config.h | 2 -- arch/arm/mach-omap2/Kconfig | 1 + configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/poleg_evb_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/stemmy_defconfig | 1 + include/configs/am43xx_evm.h | 1 - include/configs/brppt2.h | 1 - include/configs/cm_t43.h | 1 - include/configs/mx6_common.h | 1 - include/configs/odroid.h | 1 - include/configs/poleg.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stemmy.h | 1 - include/configs/ti_omap4_common.h | 1 - include/configs/trats.h | 1 - include/configs/trats2.h | 1 - include/configs/zynq-common.h | 1 - scripts/config_whitelist.txt | 1 - 38 files changed, 27 insertions(+), 17 deletions(-)
diff --git a/README b/README index 6b6f722733..595f007aaf 100644 --- a/README +++ b/README @@ -496,8 +496,6 @@ The following options need to be configured: the defaults discussed just above.
- Cache Configuration for ARM: - CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache - controller CONFIG_SYS_PL310_BASE - Physical base address of PL310 controller register space
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 949ebb46ba..b094d2d51f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -488,6 +488,10 @@ config TPL_SYS_THUMB_BUILD density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC.
+config SYS_L2_PL310 + bool "ARM PL310 L2 cache controller" + help + Enable support for ARM PL310 L2 cache controller in U-Boot
config SYS_L2CACHE_OFF bool "L2cache off" @@ -989,6 +993,7 @@ config ARCH_MX6 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + select SYS_L2_PL310 if !SYS_L2CACHE_OFF imply MXC_GPIO imply SYS_THUMB_BUILD imply SPL_SEPARATE_BSS diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a81b8e2b0d..2ebe341ed1 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -14,6 +14,7 @@ config ARMADA_32BIT select SPL_SKIP_LOWLEVEL_INIT if SPL select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL + select SYS_L2_PL310 if !SYS_L2CACHE_OFF select TRANSLATION_OFFSET select SPL_SYS_NO_VECTOR_TABLE if SPL select ARCH_VERY_EARLY_INIT diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 4add0d9e10..0bba0a4cf9 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -25,8 +25,6 @@ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif
-#define CONFIG_SYS_L2_PL310 - #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
/* Needed for SPI NOR booting in SPL */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fa41047476..fee437c4dc 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -96,6 +96,7 @@ config TI816X config AM43XX bool "AM43XX SoC" select SPECIFY_CONSOLE_INDEX + select SYS_L2_PL310 if !SYS_L2CACHE_OFF imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DM diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index bd6c2ce4ca..899ba50a16 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_DEFAULT_DEVICE_TREE="omap4-panda" diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 62eb75d1f9..82cfc4ab1a 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_OMAP2PLUS=y diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 16f6215148..4669c7fe86 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_NPCM=y CONFIG_SYS_TEXT_BASE=0x8200 CONFIG_SYS_MALLOC_LEN=0x240000 diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index c98c106851..716a68a67b 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 24c21090b1..810604ec03 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index e78d3b51de..80a965c7e2 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x4400 diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index d010b54240..7383fa1d3e 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index a1574b6a5d..9f1bed2b75 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index ec7355d2cc..8e4154f46c 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index b62f029962..713048ab3a 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index b8bc9da4d0..67b2bafbe8 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 749ec540b4..8bae98e130 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 958adfe25a..b7735689bc 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 18e125f5bd..0e47bcd4e7 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 83e24402a8..89df845ad7 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x800 diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 2a02f1dbfa..c16b3e4820 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 3d0c48d766..7bcea6726b 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index def2ee8dbc..55388da88c 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x4000 diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index d0c87416ef..9c89d631f5 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x4000 diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig index 7fc0a39872..f1d3ef5b12 100644 --- a/configs/stemmy_defconfig +++ b/configs/stemmy_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_U8500=y CONFIG_SUPPORT_PASSING_ATAGS=y # CONFIG_SETUP_MEMORY_TAGS is not set diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 87d3a27099..fc82a8c003 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -29,7 +29,6 @@ /* SPL defines. */
/* Enabling L2 Cache */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000
/* diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index adaba410ce..0c7fe5f3ab 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -13,7 +13,6 @@
/* -- i.mx6 specifica -- */ #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 07c5cb8ded..50cb2a4718 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -36,7 +36,6 @@ #define CONFIG_POWER_TPS65218
/* Enabling L2 Cache */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000
/* diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e416f81e43..4314556754 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -12,7 +12,6 @@ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif
diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 7448cc9520..babd3ca963 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -14,7 +14,6 @@ #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 #endif
diff --git a/include/configs/poleg.h b/include/configs/poleg.h index f1c259f476..05253d59ef 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -7,7 +7,6 @@ #define __CONFIG_POLEG_H
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4a7da76e51..c3f30afe2b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -48,7 +48,6 @@ /* * Cache */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/* diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 71b25c23b1..3c70856fc7 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -15,7 +15,6 @@ */
/* FIXME: This should be loaded from device tree... */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0xa0412000
/* Linux does not boot if FDT / initrd is loaded to end of RAM */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 3d78972bfe..0568946fc8 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -12,7 +12,6 @@ #define __CONFIG_TI_OMAP4_COMMON_H
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 #endif
diff --git a/include/configs/trats.h b/include/configs/trats.h index 53f5a6996b..530b413d5b 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -12,7 +12,6 @@ #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 #endif
diff --git a/include/configs/trats2.h b/include/configs/trats2.h index b7449dab8b..06c1fcd23e 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -13,7 +13,6 @@ #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 #endif
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 75ae68766f..dc0cba0010 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -11,7 +11,6 @@
/* Cache options */ #ifndef CONFIG_SYS_L2CACHE_OFF -# define CONFIG_SYS_L2_PL310 # define CONFIG_SYS_PL310_BASE 0xf8f02000 #endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4f628e0f10..d9d24c0ae0 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -908,7 +908,6 @@ CONFIG_SYS_JFFS2_FIRST_SECTOR CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_KMBEC_FPGA_BASE CONFIG_SYS_KMBEC_FPGA_SIZE -CONFIG_SYS_L2_PL310 CONFIG_SYS_L2_SIZE CONFIG_SYS_L3_SIZE CONFIG_SYS_LATCH_ADDR
On Wed, Aug 17, 2022 at 03:07:12PM +0200, Philip Oberfichtner wrote:
This converts CONFIG_SYS_L2_PL310 to Kconfig.
For omap2 and mvebu the 'select SYS_L2_PL310' locations were determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310.
For mx6 I manually chose ARCH_MX6 as 'select' location. The correctness has been verified using
$ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF 0 matches
That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert the 'select' statement under ARCH_MX6.
Signed-off-by: Philip Oberfichtner pro@denx.de
Applied to u-boot/next, thanks!
Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the SPL to build cache-pl310.c.
Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build.
[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner pro@denx.de ---
(no changes since v3)
Changes in v3: - Introduce CONFIG_SPL_SYS_L2_PL310
arch/arm/Kconfig | 5 +++++ arch/arm/lib/Makefile | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b094d2d51f..318e5e82ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -493,6 +493,11 @@ config SYS_L2_PL310 help Enable support for ARM PL310 L2 cache controller in U-Boot
+config SPL_SYS_L2_PL310 + bool "ARM PL310 L2 cache controller in SPL" + help + Enable support for ARM PL310 L2 cache controller in SPL + config SYS_L2CACHE_OFF bool "L2cache off" help diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..d137b4bf0f 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o -obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o @@ -46,6 +45,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),)
On Wed, Aug 17, 2022 at 03:07:13PM +0200, Philip Oberfichtner wrote:
Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the SPL to build cache-pl310.c.
Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build.
[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner pro@denx.de
Applied to u-boot/next, thanks!
From: Marek Vasut marex@denx.de
Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR.
Signed-off-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de
---
Changes in v6: - Once more improve the dcache_disable() comment
Changes in v5: - Clarify dcache_disable() comment
Changes in v4: - Elaborate on dcache_disable() comment
Changes in v3: - Use newly introduced Kconfig symbol for dh_imx6_defconfig
Changes in v2: - Add comment to explain the relevance of dcache_disable()
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 41 +++++++++++++++++++++++ configs/dh_imx6_defconfig | 1 + 2 files changed, 42 insertions(+)
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e49e97724a..20a330cce6 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -6,6 +6,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> @@ -14,11 +15,13 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> +#include <asm/cache.h> #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> +#include <asm/system.h> #include <errno.h> #include <fuse.h> #include <fsl_esdhc_imx.h> @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) } }
+void dram_bank_mmu_setup(int bank) +{ + int i; + + set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + + for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT; + i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) + + (SZ_1G >> MMU_SECTION_SHIFT)); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -636,9 +653,33 @@ void board_init_f(ulong dummy) /* DDR3 initialization */ dhcom_spl_dram_init();
+ /* Set up early MMU tables at the beginning of DRAM and start d-cache */ + gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M; + gd->arch.tlb_size = PGTABLE_SIZE; + enable_caches(); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */ board_init_r(NULL, 0); } + +void spl_board_prepare_for_boot(void) +{ + /* + * Flush and disable dcache. Without it, the following bootstage might fail randomly because + * dirty cache lines may not have been written back to DRAM. + * + * If dcache_disable() would be omitted, the following scenario may occur: + * + * The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled + * in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations + * have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old + * state of the content. + * + * Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was + * disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data. + */ + dcache_disable(); /* implies flush_dcache_all() */ +} diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 051816f719..1be6ae62ce 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SYS_L2_PL310=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x1000
On Wed, Aug 17, 2022 at 03:07:14PM +0200, Philip Oberfichtner wrote:
From: Marek Vasut marex@denx.de
Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR.
Signed-off-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de
Applied to u-boot/next, thanks!
participants (2)
-
Philip Oberfichtner -
Tom Rini