[U-Boot] [PATCH 01/13 v3] arm: at91: Makefile: Compile lowlevel_init only when really necessary
Make sure that lowlevel_init is not compiled when CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
arch/arm/mach-at91/arm926ejs/Makefile | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 0639d7ea1e..6b0b28957a 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -24,8 +24,10 @@ obj-y += timer.o endif
ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY obj-y += lowlevel_init.o endif +endif
ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2
This patch adds a call to spl_early_init() to board_init_f() which is needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for the early SPL setup including the DTB setup for later usage.
Please note that this call might also be needed for non SPL_OF_CONTROL board, like the smartweb target. But smartweb fails to build with this call because its binary grows too big. So I disabled it for these kind of targets for now.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
arch/arm/mach-at91/spl_at91.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index 23ebaa99b1..1065f090e0 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -75,6 +75,16 @@ void __weak spl_board_init(void)
void board_init_f(ulong dummy) { +#if CONFIG_IS_ENABLED(OF_CONTROL) + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } +#endif + lowlevel_clock_init(); #if !defined(CONFIG_WDT_AT91) at91_disable_wdt();
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - Depend fixed clock atmel_serial_enable_clk() function also on !CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here - Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead of the hardcoded value
v2: - Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/Kconfig | 9 +++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 21 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..d6bf8309d3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,15 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node.
+config SPL_UART_CLOCK + int "SPL fixed UART input clock" + depends on SPL + default 132096000 if ARCH_AT91 + help + Provide a fixed clock value as input to the UART controller. This + might be needed on platforms which can't enable CONFIG_SPL_CLK + because of SPL image size restirctions. + config BCM283X_MU_SERIAL bool "Support for BCM283x Mini-UART" depends on DM_SERIAL && ARCH_BCM283X diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..c450a4e08a 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK) +static int atmel_serial_enable_clk(struct udevice *dev) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + /* Use fixed clock value in SPL */ + priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK; + + return 0; +} +#else static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); @@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
return 0; } +#endif
static int atmel_serial_probe(struct udevice *dev) {
On 02.04.2019 11:57, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on !CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead of the hardcoded value
v2:
Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/Kconfig | 9 +++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 21 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..d6bf8309d3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,15 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node.
+config SPL_UART_CLOCK
- int "SPL fixed UART input clock"
- depends on SPL
- default 132096000 if ARCH_AT91
Hi Stefan,
This doesn't look good. This has to be unset for the platforms that do not specifically set it.
For example, when I build the sama5d2_xplained_mmc_defconfig, I look in .config and :
CONFIG_SPL_UART_CLOCK=132096000
This may be unused, but it's confusing
Can you make this default unset and then specifically set it in the boards that need it ? ( the specific defconfig )
And if you have a mutual exclusion with CONFIG_SPL_CLK can we make it somehow ? (in a menu or choice..., either old behavior or fixed uart clock)
Does this make sense?
Thanks
- help
Provide a fixed clock value as input to the UART controller. Thismight be needed on platforms which can't enable CONFIG_SPL_CLKbecause of SPL image size restirctions.- config BCM283X_MU_SERIAL bool "Support for BCM283x Mini-UART" depends on DM_SERIAL && ARCH_BCM283X
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..c450a4e08a 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK) +static int atmel_serial_enable_clk(struct udevice *dev) +{
- struct atmel_serial_priv *priv = dev_get_priv(dev);
- /* Use fixed clock value in SPL */
- priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
- return 0;
+} +#else static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); @@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
return 0; } +#endif
static int atmel_serial_probe(struct udevice *dev) {
Hi Eugen,
On 02.04.19 12:12, Eugen.Hristev@microchip.com wrote:
On 02.04.2019 11:57, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on !CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead of the hardcoded value
v2:
Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/Kconfig | 9 +++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 21 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..d6bf8309d3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,15 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node.
+config SPL_UART_CLOCK
- int "SPL fixed UART input clock"
- depends on SPL
- default 132096000 if ARCH_AT91
Hi Stefan,
This doesn't look good. This has to be unset for the platforms that do not specifically set it.
For example, when I build the sama5d2_xplained_mmc_defconfig, I look in .config and :
CONFIG_SPL_UART_CLOCK=132096000
This may be unused, but it's confusing
Okay, I agree.
Can you make this default unset and then specifically set it in the boards that need it ? ( the specific defconfig )
And if you have a mutual exclusion with CONFIG_SPL_CLK can we make it somehow ? (in a menu or choice..., either old behavior or fixed uart clock)
How about this version?
config SPL_UART_CLOCK int "SPL fixed UART input clock" depends on SPL && !SPL_CLK help Provide a fixed clock value as input to the UART controller. This might be needed on platforms which can't enable CONFIG_SPL_CLK because of SPL image size restirctions.
Thanks, Stefan
On 02.04.2019 13:40, Stefan Roese wrote:
External E-Mail
Hi Eugen,
On 02.04.19 12:12, Eugen.Hristev@microchip.com wrote:
On 02.04.2019 11:57, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on
!CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead
of the hardcoded value
v2:
- Reword patch subject and commit text to make it more clear, that
this change only affects ports with SPL and DM_SERIAL enabled drivers/serial/Kconfig | 9 +++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 21 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..d6bf8309d3 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,15 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node. +config SPL_UART_CLOCK + int "SPL fixed UART input clock" + depends on SPL + default 132096000 if ARCH_AT91
Hi Stefan,
This doesn't look good. This has to be unset for the platforms that do not specifically set it.
For example, when I build the sama5d2_xplained_mmc_defconfig, I look in .config and :
CONFIG_SPL_UART_CLOCK=132096000
This may be unused, but it's confusing
Okay, I agree.
Can you make this default unset and then specifically set it in the boards that need it ? ( the specific defconfig )
And if you have a mutual exclusion with CONFIG_SPL_CLK can we make it somehow ? (in a menu or choice..., either old behavior or fixed uart clock)
How about this version?
config SPL_UART_CLOCK int "SPL fixed UART input clock" depends on SPL && !SPL_CLK help Provide a fixed clock value as input to the UART controller. This might be needed on platforms which can't enable CONFIG_SPL_CLK because of SPL image size restirctions.
Looks much better. Typo on restrictirions
Can also add some default then, to not break build in case someone disables SPL_CLK but does not set SPL_UART_CLOCK ?
Thanks !
Thanks, Stefan
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v4: - Restrict SPL_UART_CLOCK on SPL && !SPL_CLK - Provide default value for non AT91 platforms to not break the build - Fix typo in Kconfig text
v3: - Depend fixed clock atmel_serial_enable_clk() function also on !CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here - Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead of the hardcoded value
v2: - Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/Kconfig | 10 ++++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 22 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..79fb397cf9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,16 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node.
+config SPL_UART_CLOCK + int "SPL fixed UART input clock" + depends on SPL && !SPL_CLK + default 132096000 if ARCH_AT91 + default 0 + help + Provide a fixed clock value as input to the UART controller. This + might be needed on platforms which can't enable CONFIG_SPL_CLK + because of SPL image size restrictions. + config BCM283X_MU_SERIAL bool "Support for BCM283x Mini-UART" depends on DM_SERIAL && ARCH_BCM283X diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..c450a4e08a 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK) +static int atmel_serial_enable_clk(struct udevice *dev) +{ + struct atmel_serial_priv *priv = dev_get_priv(dev); + + /* Use fixed clock value in SPL */ + priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK; + + return 0; +} +#else static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); @@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
return 0; } +#endif
static int atmel_serial_probe(struct udevice *dev) {
On 02.04.2019 14:21, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v4:
- Restrict SPL_UART_CLOCK on SPL && !SPL_CLK
- Provide default value for non AT91 platforms to not break the build
- Fix typo in Kconfig text
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on !CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead of the hardcoded value
v2:
Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/Kconfig | 10 ++++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 22 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..79fb397cf9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,16 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node.
+config SPL_UART_CLOCK
- int "SPL fixed UART input clock"
- depends on SPL && !SPL_CLK
- default 132096000 if ARCH_AT91
- default 0
- help
Provide a fixed clock value as input to the UART controller. Thismight be needed on platforms which can't enable CONFIG_SPL_CLKbecause of SPL image size restrictions.
Hi Stefan,
Looking again over this, the Kconfig you added is useless and has no effect unless ATMEL_USART driver... Can you make it to depend on atmel usart or be named ATMEL_SPL_UART_CLOCK if this is not needed for anything else whatsoever (no other platforms/drivers) This way nobody gets confused that by enabling this Kconfig on their platform, something changes (like a fixed clock for their serial in SPL, which will not happen).
Eugen
config BCM283X_MU_SERIAL bool "Support for BCM283x Mini-UART" depends on DM_SERIAL && ARCH_BCM283X diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index aa8cdff840..c450a4e08a 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -218,6 +218,17 @@ static const struct dm_serial_ops atmel_serial_ops = { .setbrg = atmel_serial_setbrg, };
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK) +static int atmel_serial_enable_clk(struct udevice *dev) +{
- struct atmel_serial_priv *priv = dev_get_priv(dev);
- /* Use fixed clock value in SPL */
- priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
- return 0;
+} +#else static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); @@ -245,6 +256,7 @@ static int atmel_serial_enable_clk(struct udevice *dev)
return 0; } +#endif
static int atmel_serial_probe(struct udevice *dev) {
Hi Eugen,
On 03.04.19 12:52, Eugen.Hristev@microchip.com wrote:
On 02.04.2019 14:21, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v4:
- Restrict SPL_UART_CLOCK on SPL && !SPL_CLK
- Provide default value for non AT91 platforms to not break the build
- Fix typo in Kconfig text
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on !CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead of the hardcoded value
v2:
Reword patch subject and commit text to make it more clear, that this change only affects ports with SPL and DM_SERIAL enabled
drivers/serial/Kconfig | 10 ++++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 22 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..79fb397cf9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,16 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node.
+config SPL_UART_CLOCK
- int "SPL fixed UART input clock"
- depends on SPL && !SPL_CLK
- default 132096000 if ARCH_AT91
- default 0
- help
Provide a fixed clock value as input to the UART controller. Thismight be needed on platforms which can't enable CONFIG_SPL_CLKbecause of SPL image size restrictions.Hi Stefan,
Looking again over this, the Kconfig you added is useless and has no effect unless ATMEL_USART driver... Can you make it to depend on atmel usart or be named ATMEL_SPL_UART_CLOCK if this is not needed for anything else whatsoever (no other platforms/drivers) This way nobody gets confused that by enabling this Kconfig on their platform, something changes (like a fixed clock for their serial in SPL, which will not happen).
My first intention was to add this Kconfig option as a generic one, which can be used by other (non-AT91) platforms as well. This is the reasoning for its name and the non-exclusive availability.
But I have no hard feelings here. If nobody sees any use of this Kconfig option on other platforms (hard for us to guess), then I can definitely make your suggested changes from above.
Thanks, Stefan
On 03.04.2019 13:58, Stefan Roese wrote:
Hi Eugen,
On 03.04.19 12:52, Eugen.Hristev@microchip.com wrote:
On 02.04.2019 14:21, Stefan Roese wrote:
This patch adds an alterative SPL version of atmel_serial_enable_clk(). This enables the usage of this driver without full clock support (in drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART input clock. It defaults to 132096000 for ARCH_AT91 but can be set to a different value if needed.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v4:
- Restrict SPL_UART_CLOCK on SPL && !SPL_CLK
- Provide default value for non AT91 platforms to not break the
build
- Fix typo in Kconfig text
v3:
- Depend fixed clock atmel_serial_enable_clk() function also on
!CONFIG_SPL_CLK so that board with full clocj support in SPL can still use the normal function here
- Introcude CONFIG_SPL_UART_CLOCK and use this Kconfig option instead
of the hardcoded value
v2:
- Reword patch subject and commit text to make it more clear, that
this change only affects ports with SPL and DM_SERIAL enabled drivers/serial/Kconfig | 10 ++++++++++ drivers/serial/atmel_usart.c | 12 ++++++++++++ 2 files changed, 22 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 887cd687c0..79fb397cf9 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -508,6 +508,16 @@ config ATMEL_USART configured in the device tree, and input clock frequency can be got from the clk node. +config SPL_UART_CLOCK + int "SPL fixed UART input clock" + depends on SPL && !SPL_CLK + default 132096000 if ARCH_AT91 + default 0 + help + Provide a fixed clock value as input to the UART controller. This + might be needed on platforms which can't enable CONFIG_SPL_CLK + because of SPL image size restrictions.
Hi Stefan,
Looking again over this, the Kconfig you added is useless and has no effect unless ATMEL_USART driver... Can you make it to depend on atmel usart or be named ATMEL_SPL_UART_CLOCK if this is not needed for anything else whatsoever (no other platforms/drivers) This way nobody gets confused that by enabling this Kconfig on their platform, something changes (like a fixed clock for their serial in SPL, which will not happen).
My first intention was to add this Kconfig option as a generic one, which can be used by other (non-AT91) platforms as well. This is the reasoning for its name and the non-exclusive availability.
But I have no hard feelings here. If nobody sees any use of this Kconfig option on other platforms (hard for us to guess), then I can definitely make your suggested changes from above.
Makes sense, but as it is now, it has no effect on other platforms. So I think it's best to make it a generic name indeed, but dependent on ATMEL_USART then... and other platforms can add their dependency once and if they implement it.
Sounds good to you ?
Thanks, Stefan
Hi Eugen,
On 03.04.19 13:05, Eugen.Hristev@microchip.com wrote:
<snip>
Looking again over this, the Kconfig you added is useless and has no effect unless ATMEL_USART driver... Can you make it to depend on atmel usart or be named ATMEL_SPL_UART_CLOCK if this is not needed for anything else whatsoever (no other platforms/drivers) This way nobody gets confused that by enabling this Kconfig on their platform, something changes (like a fixed clock for their serial in SPL, which will not happen).
My first intention was to add this Kconfig option as a generic one, which can be used by other (non-AT91) platforms as well. This is the reasoning for its name and the non-exclusive availability.
But I have no hard feelings here. If nobody sees any use of this Kconfig option on other platforms (hard for us to guess), then I can definitely make your suggested changes from above.
Makes sense, but as it is now, it has no effect on other platforms. So I think it's best to make it a generic name indeed, but dependent on ATMEL_USART then... and other platforms can add their dependency once and if they implement it.
Sounds good to you ?
Yes, I'm perfectly fine with this approach. I'll send v5 of this patch soon.
Thanks, Stefan
This patch adds some checks, so that the watchdog can be enabled in main U-Boot proper but can be disabled in SPL.
This will be used by some AT91SAM based boards, which might enable the watchdog in the main U-Boot proper and not in SPL. It will be enabled in SPL by default there, so no need to configure it there. This approach saves some space in SPL.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
include/watchdog.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/watchdog.h b/include/watchdog.h index 14073cfdd2..3a357de903 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -51,9 +51,15 @@ int init_func_watchdog_reset(void); #if defined(__ASSEMBLY__) #define WATCHDOG_RESET bl watchdog_reset #else - extern void watchdog_reset(void); + /* Don't require the watchdog to be enabled in SPL */ + #if defined(CONFIG_SPL_BUILD) && \ + !defined(CONFIG_SPL_WATCHDOG_SUPPORT) + #define WATCHDOG_RESET() {} + #else + extern void watchdog_reset(void);
- #define WATCHDOG_RESET watchdog_reset + #define WATCHDOG_RESET watchdog_reset + #endif #endif #else /*
This patch fixes the timer register setup in at91_wdt_start() to correctly configure the register again. The input timeout value is now in milli-seconds instead of seconds with the new watchdog API. Make sure to take this into account and only use a max timeout value of 16 seconds as appropriate for this SoC.
Also the check against a lower timeout value than 0 is removed. This check makes no sense, as the timeout value is unsigned.
Signed-off-by: Stefan Roese sr@denx.de Reported-by: Heiko Schocher hs@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
drivers/watchdog/at91sam9_wdt.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 13f8772e41..b0a3b4ed58 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/arch/at91_wdt.h> #include <common.h> +#include <div64.h> #include <dm.h> #include <errno.h> #include <wdt.h> @@ -31,27 +32,30 @@ DECLARE_GLOBAL_DATA_PTR; #define WDT_SEC2TICKS(s) (((s) << 8) - 1)
/* Hardware timeout in seconds */ -#define WDT_MAX_TIMEOUT 16 -#define WDT_MIN_TIMEOUT 0 -#define WDT_DEFAULT_TIMEOUT 2 +#define WDT_MAX_TIMEOUT 16 +#define WDT_DEFAULT_TIMEOUT 2
struct at91_wdt_priv { void __iomem *regs; - u32 regval; - u32 timeout; + u32 regval; + u32 timeout; };
/* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ -static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) +static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct at91_wdt_priv *priv = dev_get_priv(dev); - u32 timeout = WDT_SEC2TICKS(timeout_s); + u64 timeout; + u32 ticks;
- if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT) - timeout = priv->timeout; + /* Calculate timeout in seconds and the resulting ticks */ + timeout = timeout_ms; + do_div(timeout, 1000); + timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT); + ticks = WDT_SEC2TICKS(timeout);
/* Check if disabled */ if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { @@ -65,12 +69,10 @@ static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ - priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ - | AT91_WDT_MR_WDV(timeout); /* timer value */ - + | AT91_WDT_MR_WDV(ticks); /* timer value */ writel(priv->regval, priv->regs + AT91_WDT_MR);
return 0;
This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any more. The WD timeout value can be provided via the "timeout-sec" DT property. If not provided this way, the default value of 2 seconds will be used.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v3: - New patch
README | 3 --- configs/smartweb_defconfig | 1 - configs/taurus_defconfig | 1 - drivers/watchdog/Kconfig | 4 ---- drivers/watchdog/at91sam9_wdt.c | 2 -- 5 files changed, 11 deletions(-)
diff --git a/README b/README index c9a20db34f..a514f48cae 100644 --- a/README +++ b/README @@ -767,9 +767,6 @@ The following options need to be configured: SoC, then define this variable and provide board specific code for the "hw_watchdog_reset" function.
- CONFIG_AT91_HW_WDT_TIMEOUT - specify the timeout in seconds. default 2 seconds. - - Real-Time Clock:
When CONFIG_CMD_DATE is selected, the type of the RTC diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 7c7220afc8..807a569121 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -59,6 +59,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_WDT=y CONFIG_WDT_AT91=y -CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 022b0b6da1..d69f4895ef 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -62,5 +62,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y -CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_USE_TINY_PRINTF=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 115fc4551f..34e78beb2a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -139,10 +139,6 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices.
-config AT91_HW_WDT_TIMEOUT - bool "AT91 watchdog timeout specified" - depends on WDT_AT91 - config WDT_MT7621 bool "MediaTek MT7621 watchdog timer support" depends on WDT && ARCH_MT7620 diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index b0a3b4ed58..1c71778bdc 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -117,11 +117,9 @@ static int at91_wdt_probe(struct udevice *dev) if (!priv->regs) return -EINVAL;
-#ifdef CONFIG_AT91_HW_WDT_TIMEOUT priv->timeout = dev_read_u32_default(dev, "timeout-sec", WDT_DEFAULT_TIMEOUT); debug("%s: timeout %d", __func__, priv->timeout); -#endif
debug("%s: Probing wdt%u\n", __func__, dev->seq);
On 02.04.2019 11:57, Stefan Roese wrote:
External E-Mail
This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any more. The WD timeout value can be provided via the "timeout-sec" DT property. If not provided this way, the default value of 2 seconds will be used.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v3:
New patch
README | 3 --- configs/smartweb_defconfig | 1 - configs/taurus_defconfig | 1 - drivers/watchdog/Kconfig | 4 ---- drivers/watchdog/at91sam9_wdt.c | 2 -- 5 files changed, 11 deletions(-)
diff --git a/README b/README index c9a20db34f..a514f48cae 100644 --- a/README +++ b/README @@ -767,9 +767,6 @@ The following options need to be configured: SoC, then define this variable and provide board specific code for the "hw_watchdog_reset" function.
CONFIG_AT91_HW_WDT_TIMEOUTspecify the timeout in seconds. default 2 seconds.
Real-Time Clock:
When CONFIG_CMD_DATE is selected, the type of the RTC
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 7c7220afc8..807a569121 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -59,6 +59,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_WDT=y CONFIG_WDT_AT91=y -CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 022b0b6da1..d69f4895ef 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -62,5 +62,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y -CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_USE_TINY_PRINTF=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 115fc4551f..34e78beb2a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -139,10 +139,6 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices.
-config AT91_HW_WDT_TIMEOUT
- bool "AT91 watchdog timeout specified"
- depends on WDT_AT91
- config WDT_MT7621 bool "MediaTek MT7621 watchdog timer support" depends on WDT && ARCH_MT7620
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index b0a3b4ed58..1c71778bdc 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -117,11 +117,9 @@ static int at91_wdt_probe(struct udevice *dev) if (!priv->regs) return -EINVAL;
-#ifdef CONFIG_AT91_HW_WDT_TIMEOUT priv->timeout = dev_read_u32_default(dev, "timeout-sec", WDT_DEFAULT_TIMEOUT); debug("%s: timeout %d", __func__, priv->timeout); -#endif
debug("%s: Probing wdt%u\n", __func__, dev->seq);
Hi Stefan,
This breaks picosam9g45_defconfig
include/dm/read.h:535: undefined reference to `ofnode_read_u32_default' arm-linux-gnueabihf-ld.bfd: BFD (Linaro_Binutils-2018.05) 2.28.2.20170706 assertion fail /home/tcwg-buildslave/workspace/tcwg-make-release/builder_arch/amd64/label/tcwg-x86_64-build/target/arm-linux-gnueabihf/snapshots/binutils-gdb.git~users~linaro~binutils-2_28-branch/bfd/elf32-arm.c:9514 Makefile:1497: recipe for target 'u-boot' failed
gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)
This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any more. The WD timeout value can be provided via the "timeout-sec" DT property. If not provided this way, the default value of 2 seconds will be used.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v4: - Add CONFIG_IS_ENABLED(OF_CONTROL) to DT property read and provide default value for in the non-DT version
v3: - New patch
README | 3 --- configs/smartweb_defconfig | 1 - configs/taurus_defconfig | 1 - drivers/watchdog/Kconfig | 4 ---- drivers/watchdog/at91sam9_wdt.c | 4 +++- 5 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/README b/README index c9a20db34f..a514f48cae 100644 --- a/README +++ b/README @@ -767,9 +767,6 @@ The following options need to be configured: SoC, then define this variable and provide board specific code for the "hw_watchdog_reset" function.
- CONFIG_AT91_HW_WDT_TIMEOUT - specify the timeout in seconds. default 2 seconds. - - Real-Time Clock:
When CONFIG_CMD_DATE is selected, the type of the RTC diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 7c7220afc8..807a569121 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -59,6 +59,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_WDT=y CONFIG_WDT_AT91=y -CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 022b0b6da1..d69f4895ef 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -62,5 +62,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y -CONFIG_AT91_HW_WDT_TIMEOUT=y CONFIG_USE_TINY_PRINTF=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 115fc4551f..34e78beb2a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -139,10 +139,6 @@ config WDT_AT91 Select this to enable Microchip watchdog timer, which can be found on some AT91 devices.
-config AT91_HW_WDT_TIMEOUT - bool "AT91 watchdog timeout specified" - depends on WDT_AT91 - config WDT_MT7621 bool "MediaTek MT7621 watchdog timer support" depends on WDT && ARCH_MT7620 diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index b0a3b4ed58..a9fd547e2f 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -117,10 +117,12 @@ static int at91_wdt_probe(struct udevice *dev) if (!priv->regs) return -EINVAL;
-#ifdef CONFIG_AT91_HW_WDT_TIMEOUT +#if CONFIG_IS_ENABLED(OF_CONTROL) priv->timeout = dev_read_u32_default(dev, "timeout-sec", WDT_DEFAULT_TIMEOUT); debug("%s: timeout %d", __func__, priv->timeout); +#else + priv->timeout = WDT_DEFAULT_TIMEOUT; #endif
debug("%s: Probing wdt%u\n", __func__, dev->seq);
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v3: - Move WDT struct and macros into arch header so that it can be used by the arch code to start the driver (timeout value) - This change now enables the use of the "timeout-sec" DT property to specifiy a board specific WD timeout value
v2: - Remove #ifdef to enable compilation also in SPL version
arch/arm/mach-at91/clock.c | 48 ++++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_wdt.h | 10 +++++ drivers/watchdog/at91sam9_wdt.c | 10 ----- 3 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 64cbc3d1ed..1d3df2c09d 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -5,12 +5,17 @@ */
#include <common.h> +#include <dm.h> +#include <wdt.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_wdt.h>
#define EN_UPLL_TIMEOUT 500
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; + void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; @@ -118,3 +123,46 @@ void at91_pllicpr_init(u32 icpr)
writel(icpr, &pmc->pllicpr); } + +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + static ulong next_reset; + ulong now; + + if (!watchdog_dev) + return; + + now = get_timer(0); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + next_reset = now + 1000; /* reset every 1000ms */ + wdt_reset(watchdog_dev); + } +} + +int arch_early_init_r(void) +{ + struct at91_wdt_priv *priv; + + /* Init watchdog */ + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { + debug("Watchdog: Not found by seq!\n"); + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { + puts("Watchdog: Not found!\n"); + return 0; + } + } + + priv = dev_get_priv(watchdog_dev); + if (!priv) { + printf("Watchdog: priv not available!\n"); + return 0; + } + + wdt_start(watchdog_dev, priv->timeout * 1000, 0); + printf("Watchdog: Started\n"); + + return 0; +} diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index cd2272367b..c977b090c8 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -43,4 +43,14 @@ typedef struct at91_wdt { #define AT91_WDT_MR_WDDBGHLT 0x10000000 #define AT91_WDT_MR_WDIDLEHLT 0x20000000
+/* Hardware timeout in seconds */ +#define WDT_MAX_TIMEOUT 16 +#define WDT_DEFAULT_TIMEOUT 2 + +struct at91_wdt_priv { + void __iomem *regs; + u32 regval; + u32 timeout; +}; + #endif diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 1c71778bdc..793425c8d2 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -31,16 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; */ #define WDT_SEC2TICKS(s) (((s) << 8) - 1)
-/* Hardware timeout in seconds */ -#define WDT_MAX_TIMEOUT 16 -#define WDT_DEFAULT_TIMEOUT 2 - -struct at91_wdt_priv { - void __iomem *regs; - u32 regval; - u32 timeout; -}; - /* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit.
On 02.04.2019 11:57, Stefan Roese wrote:
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v3:
- Move WDT struct and macros into arch header so that it can be used by the arch code to start the driver (timeout value)
- This change now enables the use of the "timeout-sec" DT property to specifiy a board specific WD timeout value
Hi Stefan,
This breaks pm9261_defconfig
AS arch/arm/mach-at91/arm926ejs/lowlevel_init.o ./arch/arm/include/asm/arch/at91_wdt.h: Assembler messages: ./arch/arm/include/asm/arch/at91_wdt.h:50: Error: bad instruction `struct at91_wdt_priv {' ./arch/arm/include/asm/arch/at91_wdt.h:51: Error: bad instruction `void __iomem*regs' ./arch/arm/include/asm/arch/at91_wdt.h:52: Error: bad instruction `u32 regval' ./arch/arm/include/asm/arch/at91_wdt.h:53: Error: bad instruction `u32 timeout' ./arch/arm/include/asm/arch/at91_wdt.h:54: Error: junk at end of line, first unrecognized character is `}' scripts/Makefile.build:314: recipe for target 'arch/arm/mach-at91/arm926ejs/lowlevel_init.o' failed
v2:
Remove #ifdef to enable compilation also in SPL version
arch/arm/mach-at91/clock.c | 48 ++++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_wdt.h | 10 +++++ drivers/watchdog/at91sam9_wdt.c | 10 ----- 3 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 64cbc3d1ed..1d3df2c09d 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -5,12 +5,17 @@ */
#include <common.h> +#include <dm.h> +#include <wdt.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_wdt.h>
#define EN_UPLL_TIMEOUT 500
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
- void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -118,3 +123,46 @@ void at91_pllicpr_init(u32 icpr)
writel(icpr, &pmc->pllicpr); }
+/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{
- static ulong next_reset;
- ulong now;
- if (!watchdog_dev)
return;- now = get_timer(0);
- /* Do not reset the watchdog too often */
- if (now > next_reset) {
next_reset = now + 1000; /* reset every 1000ms */wdt_reset(watchdog_dev);- }
+}
+int arch_early_init_r(void) +{
- struct at91_wdt_priv *priv;
- /* Init watchdog */
- if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
debug("Watchdog: Not found by seq!\n");if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {puts("Watchdog: Not found!\n");return 0;}- }
- priv = dev_get_priv(watchdog_dev);
- if (!priv) {
printf("Watchdog: priv not available!\n");return 0;- }
- wdt_start(watchdog_dev, priv->timeout * 1000, 0);
- printf("Watchdog: Started\n");
- return 0;
+} diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index cd2272367b..c977b090c8 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -43,4 +43,14 @@ typedef struct at91_wdt { #define AT91_WDT_MR_WDDBGHLT 0x10000000 #define AT91_WDT_MR_WDIDLEHLT 0x20000000
+/* Hardware timeout in seconds */ +#define WDT_MAX_TIMEOUT 16 +#define WDT_DEFAULT_TIMEOUT 2
+struct at91_wdt_priv {
- void __iomem *regs;
- u32 regval;
- u32 timeout;
+};
- #endif
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 1c71778bdc..793425c8d2 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -31,16 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; */ #define WDT_SEC2TICKS(s) (((s) << 8) - 1)
-/* Hardware timeout in seconds */ -#define WDT_MAX_TIMEOUT 16 -#define WDT_DEFAULT_TIMEOUT 2
-struct at91_wdt_priv {
- void __iomem *regs;
- u32 regval;
- u32 timeout;
-};
- /*
- Set the watchdog time interval in 1/256Hz (write-once)
- Counter is 12 bit.
On 02.04.19 13:26, Eugen.Hristev@microchip.com wrote:
On 02.04.2019 11:57, Stefan Roese wrote:
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com
v3:
- Move WDT struct and macros into arch header so that it can be used by the arch code to start the driver (timeout value)
- This change now enables the use of the "timeout-sec" DT property to specifiy a board specific WD timeout value
Hi Stefan,
This breaks pm9261_defconfig
AS arch/arm/mach-at91/arm926ejs/lowlevel_init.o ./arch/arm/include/asm/arch/at91_wdt.h: Assembler messages: ./arch/arm/include/asm/arch/at91_wdt.h:50: Error: bad instruction `struct at91_wdt_priv {' ./arch/arm/include/asm/arch/at91_wdt.h:51: Error: bad instruction `void __iomem*regs' ./arch/arm/include/asm/arch/at91_wdt.h:52: Error: bad instruction `u32 regval' ./arch/arm/include/asm/arch/at91_wdt.h:53: Error: bad instruction `u32 timeout' ./arch/arm/include/asm/arch/at91_wdt.h:54: Error: junk at end of line, first unrecognized character is `}' scripts/Makefile.build:314: recipe for target 'arch/arm/mach-at91/arm926ejs/lowlevel_init.o' failed
Sorry about these breakages. I'll fix this and will run the new patches through Travis and will only send the next version once this is compile clean.
Thanks, Stefan
Hi Eugen,
On 02.04.19 13:50, Stefan Roese wrote:
<snip>
This breaks pm9261_defconfig
AS arch/arm/mach-at91/arm926ejs/lowlevel_init.o./arch/arm/include/asm/arch/at91_wdt.h: Assembler messages: ./arch/arm/include/asm/arch/at91_wdt.h:50: Error: bad instruction `struct at91_wdt_priv {' ./arch/arm/include/asm/arch/at91_wdt.h:51: Error: bad instruction `void __iomem*regs' ./arch/arm/include/asm/arch/at91_wdt.h:52: Error: bad instruction `u32 regval' ./arch/arm/include/asm/arch/at91_wdt.h:53: Error: bad instruction `u32 timeout' ./arch/arm/include/asm/arch/at91_wdt.h:54: Error: junk at end of line, first unrecognized character is `}' scripts/Makefile.build:314: recipe for target 'arch/arm/mach-at91/arm926ejs/lowlevel_init.o' failed
Sorry about these breakages. I'll fix this and will run the new patches through Travis and will only send the next version once this is compile clean.
I've sent out 2 new patch versions and this series now compiles clean. Here the Travis build log:
https://travis-ci.org/stroese/u-boot/builds/514639947
Thanks, Stefan
This patch enables and starts the watchdog on the AT91 platform if configured. The WD timeout value is read in the AT91 WD device driver from the DT, using the "timeout-sec" DT property. If not provided in the DT, the default value of 2 seconds is used.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com --- v4: - Move struct in header into location not compiled in assembler files to remove the compile breakage
v3: - Move WDT struct and macros into arch header so that it can be used by the arch code to start the driver (timeout value) - This change now enables the use of the "timeout-sec" DT property to specifiy a board specific WD timeout value
v2: - Remove #ifdef to enable compilation also in SPL version
arch/arm/mach-at91/clock.c | 48 ++++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_wdt.h | 10 +++++ drivers/watchdog/at91sam9_wdt.c | 10 ----- 3 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 64cbc3d1ed..1d3df2c09d 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -5,12 +5,17 @@ */
#include <common.h> +#include <dm.h> +#include <wdt.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_wdt.h>
#define EN_UPLL_TIMEOUT 500
+static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; + void at91_periph_clk_enable(int id) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; @@ -118,3 +123,46 @@ void at91_pllicpr_init(u32 icpr)
writel(icpr, &pmc->pllicpr); } + +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + static ulong next_reset; + ulong now; + + if (!watchdog_dev) + return; + + now = get_timer(0); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + next_reset = now + 1000; /* reset every 1000ms */ + wdt_reset(watchdog_dev); + } +} + +int arch_early_init_r(void) +{ + struct at91_wdt_priv *priv; + + /* Init watchdog */ + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { + debug("Watchdog: Not found by seq!\n"); + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { + puts("Watchdog: Not found!\n"); + return 0; + } + } + + priv = dev_get_priv(watchdog_dev); + if (!priv) { + printf("Watchdog: priv not available!\n"); + return 0; + } + + wdt_start(watchdog_dev, priv->timeout * 1000, 0); + printf("Watchdog: Started\n"); + + return 0; +} diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index cd2272367b..a8fc73b3d1 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -25,6 +25,12 @@ typedef struct at91_wdt { u32 sr; } at91_wdt_t;
+struct at91_wdt_priv { + void __iomem *regs; + u32 regval; + u32 timeout; +}; + #endif
/* Watchdog Control Register */ @@ -43,4 +49,8 @@ typedef struct at91_wdt { #define AT91_WDT_MR_WDDBGHLT 0x10000000 #define AT91_WDT_MR_WDIDLEHLT 0x20000000
+/* Hardware timeout in seconds */ +#define WDT_MAX_TIMEOUT 16 +#define WDT_DEFAULT_TIMEOUT 2 + #endif diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index a9fd547e2f..000769d46d 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -31,16 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; */ #define WDT_SEC2TICKS(s) (((s) << 8) - 1)
-/* Hardware timeout in seconds */ -#define WDT_MAX_TIMEOUT 16 -#define WDT_DEFAULT_TIMEOUT 2 - -struct at91_wdt_priv { - void __iomem *regs; - u32 regval; - u32 timeout; -}; - /* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit.
This patch adds _image_binary_end to the SPL linker script. This will be used be the upcoming GARDENA AT91SAM based platform, which uses DT in SPL and configures CONFIGURE_SPL_SEPARATE_BSS.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds index f18b17dc93..3955bea23a 100644 --- a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -39,6 +39,8 @@ SECTIONS *(.__end) } >.sram
+ _image_binary_end = .; + .bss : { . = ALIGN(4);
This patch moves the AT91SAM NAND booting SPL image "boot.bin" which includes the ECC values from the root directory into the spl directory, where all SPL related images are located.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
scripts/Makefile.spl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 54b160d72b..56dbbe127b 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -179,10 +179,10 @@ MKIMAGEFLAGS_boot.bin = -T atmelimage ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y) MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params)
-boot.bin: $(obj)/../tools/atmel_pmecc_params +$(obj)/boot.bin: $(obj)/../tools/atmel_pmecc_params endif
-boot.bin: $(obj)/u-boot-spl.bin FORCE +$(obj)/boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) else ifdef CONFIG_ARCH_ZYNQ @@ -225,7 +225,7 @@ endif endif
ifeq ($(CONFIG_SYS_SOC),"at91") -ALL-y += boot.bin +ALL-y += $(obj)/boot.bin endif
ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND). For these build targets the combined image "u-boot-with-spl.bin" is now automatically generated and can be programmed into NAND as one single image (vs. SPL image and U-Boot as 2 separate images).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details.
+config SPL_IMAGE + string "SPL image filename that is generated" + default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT + default "spl/u-boot-spl.bin" + help + The SPL image filename that is generated by the build process. + This image might be used to generated a combined image with + SPL and main U-Boot proper as well. + config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 @@ -232,6 +241,7 @@ config BUILD_TARGET default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD + default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help Some SoCs need special image types (e.g. U-Boot binary with a special header) as build targets. By defining diff --git a/Makefile b/Makefile index c1af9307b3..077bb6634e 100644 --- a/Makefile +++ b/Makefile @@ -1225,9 +1225,11 @@ else SPL_PAYLOAD := u-boot.bin endif
+SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%) + OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) -u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE +u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat)
ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
On 02.04.2019 11:57, Stefan Roese wrote:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND). For these build targets the combined image "u-boot-with-spl.bin" is now automatically generated and can be programmed into NAND as one single image (vs. SPL image and U-Boot as 2 separate images).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
v3:
- No change
v2:
No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details.
+config SPL_IMAGE
- string "SPL image filename that is generated"
- default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
- default "spl/u-boot-spl.bin"
- help
The SPL image filename that is generated by the build process.This image might be used to generated a combined image withSPL and main U-Boot proper as well.
Hi Stefan,
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Eugen
config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 @@ -232,6 +241,7 @@ config BUILD_TARGET default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD
- default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help Some SoCs need special image types (e.g. U-Boot binary with a special header) as build targets. By defining
diff --git a/Makefile b/Makefile index c1af9307b3..077bb6634e 100644 --- a/Makefile +++ b/Makefile @@ -1225,9 +1225,11 @@ else SPL_PAYLOAD := u-boot.bin endif
+SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%)
- OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO)
-u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE +u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat)
ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
On 03.04.2019 14:03, Eugen Hristev wrote:
On 02.04.2019 11:57, Stefan Roese wrote:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND). For these build targets the combined image "u-boot-with-spl.bin" is now automatically generated and can be programmed into NAND as one single image (vs. SPL image and U-Boot as 2 separate images).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
v3:
- No change
v2:
- No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details. +config SPL_IMAGE + string "SPL image filename that is generated" + default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT + default "spl/u-boot-spl.bin" + help + The SPL image filename that is generated by the build process. + This image might be used to generated a combined image with + SPL and main U-Boot proper as well.
Hi Stefan,
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Ok, the commit message explains it pretty well, but the Kconfig help is totally different... hence the confusion sorry. So we need to either make a choice submenu in this Kconfig : either this or that; or, do exactly what the Kconfig says: rename the output binary into the value of this Kconfig.
Does this make sense ?
Eugen
config BUILD_TARGET string "Build target special images" default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 @@ -232,6 +241,7 @@ config BUILD_TARGET default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI default "u-boot.kwb" if KIRKWOOD + default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help Some SoCs need special image types (e.g. U-Boot binary with a special header) as build targets. By defining diff --git a/Makefile b/Makefile index c1af9307b3..077bb6634e 100644 --- a/Makefile +++ b/Makefile @@ -1225,9 +1225,11 @@ else SPL_PAYLOAD := u-boot.bin endif +SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%)
OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) -u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE +u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) ifeq ($(CONFIG_ARCH_LPC32XX)$(CONFIG_SPL),yy)
On 03.04.19 13:11, Eugen.Hristev@microchip.com wrote:
On 03.04.2019 14:03, Eugen Hristev wrote:
On 02.04.2019 11:57, Stefan Roese wrote:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND). For these build targets the combined image "u-boot-with-spl.bin" is now automatically generated and can be programmed into NAND as one single image (vs. SPL image and U-Boot as 2 separate images).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
v3:
- No change
v2:
- No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details. +config SPL_IMAGE + string "SPL image filename that is generated" + default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT + default "spl/u-boot-spl.bin" + help + The SPL image filename that is generated by the build process. + This image might be used to generated a combined image with + SPL and main U-Boot proper as well.
Hi Stefan,
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Ok, the commit message explains it pretty well, but the Kconfig help is totally different... hence the confusion sorry. So we need to either make a choice submenu in this Kconfig : either this or that; or, do exactly what the Kconfig says: rename the output binary into the value of this Kconfig.
Does this make sense ?
You are suggesting to add this SPL_IMAGE as choice instead of its current implementation? That might be better, yes. Let me look into this...
Thanks, Stefan
Hi Eugen,
On 03.04.19 13:21, Stefan Roese wrote:
<snip>
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Ok, the commit message explains it pretty well, but the Kconfig help is totally different... hence the confusion sorry. So we need to either make a choice submenu in this Kconfig : either this or that; or, do exactly what the Kconfig says: rename the output binary into the value of this Kconfig.
Does this make sense ?
You are suggesting to add this SPL_IMAGE as choice instead of its current implementation? That might be better, yes. Let me look into this...
I did look into this and I would prefer to stay with the original implementation of the defaults. Changing this into a Kconfig choice makes this a bit more complex in the Kconfig. Additionally and even more important (for my personal feeling), the original implementation is more in line with the BUILD_TARGET implemenation directly below this new implementation.
So if you don't object, I would like to send a new version with the original implementation but with a "better" (more correct) description in Kconfig.
What do you think?
Thanks, Stefan
On 03.04.2019 15:22, Stefan Roese wrote:
External E-Mail
Hi Eugen,
On 03.04.19 13:21, Stefan Roese wrote:
<snip>
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Ok, the commit message explains it pretty well, but the Kconfig help is totally different... hence the confusion sorry. So we need to either make a choice submenu in this Kconfig : either this or that; or, do exactly what the Kconfig says: rename the output binary into the value of this Kconfig.
Does this make sense ?
You are suggesting to add this SPL_IMAGE as choice instead of its current implementation? That might be better, yes. Let me look into this...
I did look into this and I would prefer to stay with the original implementation of the defaults. Changing this into a Kconfig choice makes this a bit more complex in the Kconfig. Additionally and even more important (for my personal feeling), the original implementation is more in line with the BUILD_TARGET implemenation directly below this new implementation.
So if you don't object, I would like to send a new version with the original implementation but with a "better" (more correct) description in Kconfig.
What do you think?
This would imply that your new description has to state that if an incorrect binary name is configured here, the build will fail (?)
Thanks, Stefan
On 03.04.19 14:31, Eugen.Hristev@microchip.com wrote:
On 03.04.2019 15:22, Stefan Roese wrote:
External E-Mail
Hi Eugen,
On 03.04.19 13:21, Stefan Roese wrote:
<snip>
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Ok, the commit message explains it pretty well, but the Kconfig help is totally different... hence the confusion sorry. So we need to either make a choice submenu in this Kconfig : either this or that; or, do exactly what the Kconfig says: rename the output binary into the value of this Kconfig.
Does this make sense ?
You are suggesting to add this SPL_IMAGE as choice instead of its current implementation? That might be better, yes. Let me look into this...
I did look into this and I would prefer to stay with the original implementation of the defaults. Changing this into a Kconfig choice makes this a bit more complex in the Kconfig. Additionally and even more important (for my personal feeling), the original implementation is more in line with the BUILD_TARGET implemenation directly below this new implementation.
So if you don't object, I would like to send a new version with the original implementation but with a "better" (more correct) description in Kconfig.
What do you think?
This would imply that your new description has to state that if an incorrect binary name is configured here, the build will fail (?)
No. My main reasoning here is, that this is also not included in the description of "BUILD_TARGET" below. Here you can also change the selected value (via Kconfig help, no user input needed) to a new value that is not supported, which also results in a build error.
I would like to not make this overly complex here. If a user wants to do something stupid by defining this (or some other Kconfig option) to an unsupported value, we can't really stop him.
If you really think this is necessary, I will add a sentence to the Kconfig text, to only select "supported" values here. But again, I would prefer to not do this.
Thanks, Stefan
On 03.04.2019 15:38, Stefan Roese wrote:
External E-Mail
On 03.04.19 14:31, Eugen.Hristev@microchip.com wrote:
On 03.04.2019 15:22, Stefan Roese wrote:
External E-Mail
Hi Eugen,
On 03.04.19 13:21, Stefan Roese wrote:
<snip>
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Ok, the commit message explains it pretty well, but the Kconfig help is totally different... hence the confusion sorry. So we need to either make a choice submenu in this Kconfig : either this or that; or, do exactly what the Kconfig says: rename the output binary into the value of this Kconfig.
Does this make sense ?
You are suggesting to add this SPL_IMAGE as choice instead of its current implementation? That might be better, yes. Let me look into this...
I did look into this and I would prefer to stay with the original implementation of the defaults. Changing this into a Kconfig choice makes this a bit more complex in the Kconfig. Additionally and even more important (for my personal feeling), the original implementation is more in line with the BUILD_TARGET implemenation directly below this new implementation.
So if you don't object, I would like to send a new version with the original implementation but with a "better" (more correct) description in Kconfig.
What do you think?
This would imply that your new description has to state that if an incorrect binary name is configured here, the build will fail (?)
No. My main reasoning here is, that this is also not included in the description of "BUILD_TARGET" below. Here you can also change the selected value (via Kconfig help, no user input needed) to a new value that is not supported, which also results in a build error.
I would like to not make this overly complex here. If a user wants to do something stupid by defining this (or some other Kconfig option) to an unsupported value, we can't really stop him.
If you really think this is necessary, I will add a sentence to the Kconfig text, to only select "supported" values here. But again, I would prefer to not do this.
Thanks, Stefan
Allright, but we have to make sure that everyone understands what this option does when they try to change it. So, a bit of rework of the help text is needed.
On 03.04.19 13:08, Eugen.Hristev@microchip.com wrote:
On 02.04.2019 11:57, Stefan Roese wrote:
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that shall be used to generate the combined SPL + U-Boot image. The default value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets which use SPL NAND support (boot from NAND). For these build targets the combined image "u-boot-with-spl.bin" is now automatically generated and can be programmed into NAND as one single image (vs. SPL image and U-Boot as 2 separate images).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de
v3:
- No change
v2:
No change
Kconfig | 10 ++++++++++ Makefile | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig index 305b265ed7..7c2b86f1f3 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,15 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details.
+config SPL_IMAGE
- string "SPL image filename that is generated"
- default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
- default "spl/u-boot-spl.bin"
- help
The SPL image filename that is generated by the build process.This image might be used to generated a combined image withSPL and main U-Boot proper as well.Hi Stefan,
If I try to just use menuconfig and change this value to something else, build fails. The purpose of this Kconfig is to name the SPL filename as per the config's desire ?
Or in fact is "which binary file to use to make the Combined SPL+U-BOOT mega image" ?
Its not meant to change the SPL image filename to an arbitrary name. Its meant to select one of the already supported values of the build system. I should probably re-phrase the Kconfig text to better reflect this.
Thanks, Stefan
This patch adds the necessary defines to the Siemens AT91SAM based boards (smartweb, corvus and taurus) to generate the combined binary image with SPL and main U-Boot image combined (u-boot-with-spl.bin).
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de Tested on the taurus board: Tested-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - No change
include/configs/corvus.h | 3 +++ include/configs/smartweb.h | 4 ++++ include/configs/taurus.h | 3 +++ 3 files changed, 10 insertions(+)
diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 5dd5c28e08..749a67d4b0 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -139,4 +139,7 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302
+#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + #endif diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 28af575bf2..f95b29480d 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -221,4 +221,8 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #endif + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + #endif /* __CONFIG_H */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 1d24577993..3582eb2edf 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -173,4 +173,7 @@ #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10193F05
+#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + #endif
This makes it possible to reference the watchdog DT node via "&watchdog" from board dts files.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de --- v3: - No change
v2: - New patch
arch/arm/dts/at91sam9x5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi index ea319cc18b..bd4abe00d6 100644 --- a/arch/arm/dts/at91sam9x5.dtsi +++ b/arch/arm/dts/at91sam9x5.dtsi @@ -1180,7 +1180,7 @@ }; };
- watchdog@fffffe40 { + watchdog: watchdog@fffffe40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffe40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage. This patch adds support for this board including SPL support. Therefore the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese sr@denx.de Cc: Heiko Schocher hs@denx.de Cc: Andreas Bießmann andreas@biessmann.org Cc: Eugen Hristev eugen.hristev@microchip.com Reviewed-by: Heiko Schocher hs@denx.de --- v3: - Add "timeout-sec" DT property
v2: - Add dtb build target in dts Makefile - Add gardena-smart-gateway-at91sam-u-boot.dtsi file with U-Boot specific DT properties - at91sam9x5ek.dtsi is not included in the dts file any more as this did enable too much unused devices
arch/arm/dts/Makefile | 3 + ...1sam9g25-gardena-smart-gateway-u-boot.dtsi | 5 + .../dts/at91sam9g25-gardena-smart-gateway.dts | 120 ++++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/gardena/smart-gateway-at91sam/Kconfig | 12 ++ .../gardena/smart-gateway-at91sam/MAINTAINERS | 7 + board/gardena/smart-gateway-at91sam/Makefile | 7 + board/gardena/smart-gateway-at91sam/board.c | 59 ++++++++ board/gardena/smart-gateway-at91sam/spl.c | 135 ++++++++++++++++++ .../gardena-smart-gateway-at91sam_defconfig | 83 +++++++++++ .../configs/gardena-smart-gateway-at91sam.h | 88 ++++++++++++ 11 files changed, 527 insertions(+) create mode 100644 arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi create mode 100644 arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts create mode 100644 board/gardena/smart-gateway-at91sam/Kconfig create mode 100644 board/gardena/smart-gateway-at91sam/MAINTAINERS create mode 100644 board/gardena/smart-gateway-at91sam/Makefile create mode 100644 board/gardena/smart-gateway-at91sam/board.c create mode 100644 board/gardena/smart-gateway-at91sam/spl.c create mode 100644 configs/gardena-smart-gateway-at91sam_defconfig create mode 100644 include/configs/gardena-smart-gateway-at91sam.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..ff2212ed47 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -607,6 +607,9 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
+dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \ + at91sam9g25-gardena-smart-gateway.dtb + dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb diff --git a/arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi b/arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi new file mode 100644 index 0000000000..732dee6c0e --- /dev/null +++ b/arch/arm/dts/at91sam9g25-gardena-smart-gateway-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&dbgu { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts new file mode 100644 index 0000000000..e2f8d8047e --- /dev/null +++ b/arch/arm/dts/at91sam9g25-gardena-smart-gateway.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the GARDENA smart Gateway (AT91SAM) + * + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre nicolas.ferre@atmel.com + */ + +/dts-v1/; + +#include "at91sam9g25.dtsi" + +/ { + model = "GARDENA smart Gateway (AT91SAM)"; + compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9"; + + aliases { + serial0 = &dbgu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_blue { + label = "smartgw:power:blue"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_green { + label = "smartgw:power:green"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + power_red { + label = "smartgw:power:red"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_blue { + label = "smartgw:radio:blue"; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_green { + label = "smartgw:radio:green"; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_red { + label = "smartgw:radio:red"; + gpios = <&pioC 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_blue { + label = "smartgw:internet:blue"; + gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_green { + label = "smartgw:internet:green"; + gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_red { + label = "smartgw:internet:red"; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&dbgu { + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&nand0 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; /* Enable PMECC */ + atmel,pmecc-cap = <2>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; +}; + +&watchdog { + status = "okay"; + timeout-sec = <16>; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a6329dc022..a089e9439e 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -147,6 +147,13 @@ config TARGET_AT91SAM9X5EK select BOARD_LATE_INIT select SUPPORT_SPL
+config TARGET_GARDENA_SMART_GATEWAY_AT91SAM + bool "GARDENA smart Gateway (AT91SAM)" + select AT91SAM9X5 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select SUPPORT_SPL + config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" select BOARD_EARLY_INIT_F @@ -283,6 +290,7 @@ source "board/bluewater/snapper9260/Kconfig" source "board/calao/usb_a9263/Kconfig" source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" +source "board/gardena/smart-gateway-at91sam/Kconfig" source "board/l+g/vinco/Kconfig" source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" diff --git a/board/gardena/smart-gateway-at91sam/Kconfig b/board/gardena/smart-gateway-at91sam/Kconfig new file mode 100644 index 0000000000..ea2b5ff4e6 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GARDENA_SMART_GATEWAY_AT91SAM + +config SYS_BOARD + default "smart-gateway-at91sam" + +config SYS_VENDOR + default "gardena" + +config SYS_CONFIG_NAME + default "gardena-smart-gateway-at91sam" + +endif diff --git a/board/gardena/smart-gateway-at91sam/MAINTAINERS b/board/gardena/smart-gateway-at91sam/MAINTAINERS new file mode 100644 index 0000000000..a5e4c71b82 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/MAINTAINERS @@ -0,0 +1,7 @@ +GARDENA_SMART_GATEWAY_AT91SAM BOARD +M: Stefan Roese sr@denx.de +S: Maintained +F: board/gardena/smart-gateway-at91sam/ +F: include/configs/gardena-smart-gateway-at91sam.h +F: configs/gardena-smart-gateway-at91sam_defconfig +F: arch/arm/dts/gardena-smart-gateway-at91sam.dts diff --git a/board/gardena/smart-gateway-at91sam/Makefile b/board/gardena/smart-gateway-at91sam/Makefile new file mode 100644 index 0000000000..a2ed79fd06 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c new file mode 100644 index 0000000000..6a1389eb05 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/board.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Atmel Corporation + * Copyright (C) 2019 Stefan Roese sr@denx.de + */ + +#include <common.h> +#include <debug_uart.h> +#include <led.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void at91_prepare_cpu_var(void) +{ + env_set("cpu", get_cpu_name()); +} + +int board_late_init(void) +{ + at91_prepare_cpu_var(); + + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + return 0; +} + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c new file mode 100644 index 0000000000..3ab6760df7 --- /dev/null +++ b/board/gardena/smart-gateway-at91sam/spl.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Atmel Corporation + * Copyright (C) 2019 Stefan Roese sr@denx.de + */ + +#include <common.h> +#include <nand.h> +#include <spl.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> + +static void at91sam9x5ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + + /* NAND flash on D16 */ + csa |= AT91_MATRIX_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + at91_periph_clk_enable(ATMEL_ID_PIOCD); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); +} + +void at91_spl_board_init(void) +{ + at91sam9x5ek_nand_hw_init(); +} + +static void ddr2_conf(struct atmel_mpddrc_config *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddrc_config ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* Enable DDR2 clock */ + writel(AT91_PMC_DDR, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); +} diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig new file mode 100644 index 0000000000..b395a5a175 --- /dev/null +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x22900000 +CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=132000000 +CONFIG_SMBIOS_PRODUCT_NAME="at91sam9x5ek" +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_TPL_BANNER_PRINT is not set +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand0" +CONFIG_MTDPARTS_DEFAULT="nand0:1536k(uboot),1024k(unused),512k(dtb_old),4608k(kernel_old),86528k(ubi),-(rootfs_old)" +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names" +CONFIG_ENV_IS_IN_UBI=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +# CONFIG_MMC is not set +CONFIG_NAND_ATMEL=y +CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y +# CONFIG_CONFIG_UBI_SILENCE_MSG is not set +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +# CONFIG_SYS_WHITE_ON_BLACK is not set +CONFIG_WATCHDOG=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y +# CONFIG_UBIFS_SILENCE_MSG is not set +CONFIG_USE_TINY_PRINTF=y diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h new file mode 100644 index 0000000000..e9a06e6d00 --- /dev/null +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2012 Atmel Corporation + * Copyright (C) 2019 Stefan Roese sr@denx.de + * + * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) + +/* NAND flash */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* environment organization */ +#define CONFIG_ENV_UBI_PART "ubi" +#define CONFIG_ENV_UBI_VOLUME "env" +#define CONFIG_ENV_UBI_VOLUME_REDUND "env_r" +#define CONFIG_ENV_SIZE (64 << 10) + +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x7000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_RAW_ONLY +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 + +#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO + +#endif
participants (2)
-
Eugen.Hristev＠microchip.com -
Stefan Roese