[PATCH 0/4] Remove addr parameter from reset_cpu()
Hi,
this is something I had on my mind for a longer time but never got around to actually do until now ... A while back, while working on the patchset that led to commit c5635a032a4b ("ARM: imx8m: Don't use the addr parameter of reset_cpu()"), I noticed that the `addr` parameter of reset_cpu() seems to not actually hold any meaningful value. All call-sites in the current tree just pass 0 and the vast majority of reset_cpu() implementations actually ignore the parameter.
I dug a bit deeper to find out why this `addr` parameter exists in the first place and found out that it's mostly a legacy artifact:
Historically, the reset_cpu() function had this `addr` parameter to pass an address of a reset vector location, where the CPU should reset to.
The times where this was used are long gone and the only trace it left is some (dead) code for the NDS32 arch. The `addr` parameter lived on and it looks like it was sometimes used as a way to indicate different types of resets (e.g. COLD vs WARM).
Today, however, reset_cpu() is only ever called with `addr` 0 in the mainline tree and as such, any code that gives a meaning to the `addr` value will only ever follow the `addr == 0` branch. This is probably not what the authors intended and as it seems quite unobvious to me, I think the best way forward is to remove the `addr` parameter entirely.
This removes any ambiguity in the "contract" of reset_cpu() and thus hopefully prevents more code being added which wrongly assumes that the parameter can be used for any meaningful purpose. Instead, code which wants to properly support multiple reset types needs to be implemented as a sysreset driver.
I did this API change via a coccinelle patch, see "reset: Remove addr parameter from reset_cpu()" for details. I also ran buildman for all boards I could, to verify that everything still compiles. One notable exception is NDS32 because I couldn't get the compiler to work there ...
Regards, Harald
Harald Seiler (4): nds32: Remove dead reset_cpu() implementation board: ns3: Remove superfluous reset logic Revert "lpc32xx: cpu: add support for soft reset" reset: Remove addr parameter from reset_cpu()
arch/arc/lib/reset.c | 4 ++-- arch/arm/cpu/arm920t/ep93xx/cpu.c | 2 +- arch/arm/cpu/arm920t/imx/timer.c | 2 +- arch/arm/cpu/arm926ejs/armada100/timer.c | 2 +- arch/arm/cpu/arm926ejs/mx25/reset.c | 2 +- arch/arm/cpu/arm926ejs/mx27/reset.c | 2 +- arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++-- arch/arm/cpu/arm926ejs/spear/reset.c | 2 +- arch/arm/cpu/arm946es/cpu.c | 2 +- arch/arm/cpu/armv7/bcm281xx/reset.c | 2 +- arch/arm/cpu/armv7/bcmcygnus/reset.c | 2 +- arch/arm/cpu/armv7/bcmnsp/reset.c | 2 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/s5p4418/cpu.c | 2 +- arch/arm/cpu/armv7/stv0991/reset.c | 2 +- arch/arm/cpu/armv7m/cpu.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++-- arch/arm/cpu/armv8/s32v234/generic.c | 2 +- arch/arm/cpu/pxa/pxa2xx.c | 4 ++-- arch/arm/cpu/sa1100/cpu.c | 2 +- arch/arm/lib/interrupts.c | 2 +- arch/arm/lib/interrupts_m.c | 2 +- arch/arm/lib/reset.c | 2 +- arch/arm/mach-at91/arm920t/reset.c | 2 +- arch/arm/mach-at91/arm926ejs/reset.c | 2 +- arch/arm/mach-at91/armv7/reset.c | 2 +- arch/arm/mach-bcm283x/reset.c | 2 +- arch/arm/mach-davinci/reset.c | 2 +- arch/arm/mach-exynos/soc.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/mx7ulp/soc.c | 2 +- arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-keystone/ddr3.c | 4 ++-- arch/arm/mach-keystone/init.c | 2 +- arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-lpc32xx/cpu.c | 23 +++++------------- arch/arm/mach-mediatek/mt7622/init.c | 2 +- arch/arm/mach-mediatek/mt8512/init.c | 2 +- arch/arm/mach-mediatek/mt8516/init.c | 2 +- arch/arm/mach-mediatek/mt8518/init.c | 2 +- arch/arm/mach-meson/board-common.c | 4 ++-- arch/arm/mach-mvebu/armada3700/cpu.c | 2 +- arch/arm/mach-mvebu/armada8k/cpu.c | 2 +- arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-octeontx/cpu.c | 2 +- arch/arm/mach-octeontx2/cpu.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- arch/arm/mach-omap2/reset.c | 2 +- arch/arm/mach-orion5x/cpu.c | 2 +- arch/arm/mach-owl/soc.c | 2 +- .../mach-socfpga/include/mach/reset_manager.h | 2 +- arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-tegra/cmd_enterrcm.c | 2 +- arch/arm/mach-tegra/pmc.c | 2 +- arch/arm/mach-uniphier/arm32/psci.c | 2 +- arch/arm/mach-uniphier/reset.c | 2 +- arch/arm/mach-zynq/cpu.c | 2 +- arch/arm/mach-zynqmp-r5/cpu.c | 2 +- arch/nds32/cpu/n1213/ag101/cpu.c | 2 +- arch/nds32/cpu/n1213/start.S | 22 ----------------- arch/nds32/lib/interrupts.c | 2 +- arch/sandbox/cpu/sdl.c | 4 ++-- arch/sh/cpu/sh4/cpu.c | 2 +- arch/sh/cpu/sh4/watchdog.c | 2 +- arch/x86/cpu/ivybridge/cpu.c | 2 +- board/BuR/brppt2/board.c | 2 +- board/abilis/tb100/tb100.c | 2 +- .../imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 2 +- board/armltd/total_compute/total_compute.c | 2 +- board/armltd/vexpress/vexpress_common.c | 2 +- board/armltd/vexpress64/vexpress64.c | 2 +- .../armadillo-800eva/armadillo-800eva.c | 2 +- board/beacon/beacon-rzg2m/beacon-rzg2m.c | 2 +- board/bosch/shc/board.c | 2 +- board/broadcom/bcmns2/northstar2.c | 2 +- board/broadcom/bcmns3/ns3.c | 24 +++---------------- board/broadcom/bcmstb/bcmstb.c | 2 +- board/cavium/thunderx/thunderx.c | 2 +- board/compulab/cm_t335/spl.c | 2 +- board/cortina/presidio-asic/presidio.c | 2 +- board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/freescale/mx6memcal/spl.c | 2 +- board/ge/b1x5v2/spl.c | 2 +- board/highbank/highbank.c | 2 +- board/hisilicon/hikey/hikey.c | 2 +- board/hisilicon/hikey960/hikey960.c | 2 +- board/hisilicon/poplar/poplar.c | 2 +- board/kmc/kzm9g/kzm9g.c | 2 +- board/liebherr/display5/spl.c | 2 +- board/phytium/durian/durian.c | 2 +- .../dragonboard410c/dragonboard410c.c | 2 +- .../dragonboard820c/dragonboard820c.c | 2 +- board/renesas/alt/alt.c | 2 +- board/renesas/alt/alt_spl.c | 2 +- board/renesas/blanche/blanche.c | 2 +- board/renesas/condor/condor.c | 2 +- board/renesas/draak/draak.c | 2 +- board/renesas/eagle/eagle.c | 2 +- board/renesas/ebisu/ebisu.c | 2 +- board/renesas/gose/gose.c | 2 +- board/renesas/gose/gose_spl.c | 2 +- board/renesas/grpeach/grpeach.c | 2 +- board/renesas/koelsch/koelsch.c | 2 +- board/renesas/koelsch/koelsch_spl.c | 2 +- board/renesas/lager/lager.c | 2 +- board/renesas/lager/lager_spl.c | 2 +- board/renesas/porter/porter.c | 2 +- board/renesas/porter/porter_spl.c | 2 +- board/renesas/rcar-common/gen3-spl.c | 2 +- board/renesas/salvator-x/salvator-x.c | 2 +- board/renesas/silk/silk.c | 2 +- board/renesas/silk/silk_spl.c | 2 +- board/renesas/stout/cpld.c | 2 +- board/renesas/stout/stout_spl.c | 2 +- board/siemens/capricorn/board.c | 2 +- board/synopsys/emsdp/emsdp.c | 2 +- board/synopsys/iot_devkit/iot_devkit.c | 2 +- board/technexion/pico-imx6ul/spl.c | 2 +- board/technexion/pico-imx7d/spl.c | 2 +- board/toradex/apalis-imx8/apalis-imx8.c | 2 +- board/toradex/apalis-imx8x/apalis-imx8x.c | 2 +- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri-imx8x/colibri-imx8x.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/toradex/colibri_imx7/colibri_imx7.c | 2 +- board/xen/xenguest_arm64/xenguest_arm64.c | 2 +- board/xilinx/versal/board.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- cmd/tpm_test.c | 2 +- drivers/sysreset/sysreset-uclass.c | 2 +- drivers/watchdog/imx_watchdog.c | 2 +- drivers/watchdog/ulp_wdog.c | 2 +- include/cpu_func.h | 4 ++-- include/sysreset.h | 2 +- 135 files changed, 149 insertions(+), 200 deletions(-)
nds32 is one of the only architectures which still have a reset_cpu() implementation that makes use of the `addr` parameter. The rest of U-Boot now ignores it and passes 0 everywhere. It turns out that even here, reset_cpu() is no longer referenced anywhere; reset is either not implemented (e.g. ae3xx) or realized using a WDT (e.g. ag101).
Remove this left-over implementation in preparation for the removal of the `addr` parameter in the entire tree.
Cc: Rick Chen rick@andestech.com Signed-off-by: Harald Seiler hws@denx.de --- arch/nds32/cpu/n1213/start.S | 22 ---------------------- 1 file changed, 22 deletions(-)
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 386c1998dcef..3395721552a3 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -500,25 +500,3 @@ software_interrupt: bal do_interruption
.align 5 - -/* - * void reset_cpu(ulong addr); - * $r0: input address to jump to - */ -.globl reset_cpu -reset_cpu: -/* No need to disable MMU because we never enable it */ - - bal invalidate_icac - bal invalidate_dcac - mfsr $p0, $MMU_CFG - andi $p0, $p0, 0x3 ! MMPS - li $p1, 0x2 ! TLB MMU - bne $p0, $p1, 1f - tlbop flushall ! Flush TLB -1: - mfsr $p0, MR_CAC_CTL ! Get the $CACHE_CTL reg - li $p1, DIS_DCAC - and $p0, $p0, $p1 ! Clear the DC_EN bit - mtsr $p0, MR_CAC_CTL ! Write back the $CACHE_CTL reg - br $r0 ! Jump to the input address
On Tue, 15 Dec 2020 at 08:48, Harald Seiler hws@denx.de wrote:
nds32 is one of the only architectures which still have a reset_cpu() implementation that makes use of the `addr` parameter. The rest of U-Boot now ignores it and passes 0 everywhere. It turns out that even here, reset_cpu() is no longer referenced anywhere; reset is either not implemented (e.g. ae3xx) or realized using a WDT (e.g. ag101).
Remove this left-over implementation in preparation for the removal of the `addr` parameter in the entire tree.
Cc: Rick Chen rick@andestech.com Signed-off-by: Harald Seiler hws@denx.de
arch/nds32/cpu/n1213/start.S | 22 ---------------------- 1 file changed, 22 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Tue, Dec 15, 2020 at 04:47:49PM +0100, Harald Seiler wrote:
nds32 is one of the only architectures which still have a reset_cpu() implementation that makes use of the `addr` parameter. The rest of U-Boot now ignores it and passes 0 everywhere. It turns out that even here, reset_cpu() is no longer referenced anywhere; reset is either not implemented (e.g. ae3xx) or realized using a WDT (e.g. ag101).
Remove this left-over implementation in preparation for the removal of the `addr` parameter in the entire tree.
Cc: Rick Chen rick@andestech.com Signed-off-by: Harald Seiler hws@denx.de Reviewed-by: Simon Glass sjg@chromium.org Reviewed-by: Rick Chen rick@andestech.com
Applied to u-boot/master, thanks!
The current implementation of reset_cpu() in the ns3 board code does not archieve what it is supposed to (according to the comments), due to a number of reasons:
1. The argument to reset_cpu() is _not_ actually passed from the `reset` command, but is set to 0 in all call-sites (in this specific case, see arch/arm/lib/reset.c). Thus, performing different kinds of resets based on its value will not work as expected.
2. Contrary to its documentation, the passed argument is not interpreted, but a static `L3_RESET` define is used. The other comment properly notes that this will always perform a L3 reset, though.
3. The "parsing" of the static `L3_RESET` value is not even using the upper and lower nibble as stated in the comment, but uses the last two decimal digits of the value.
This is currently one of the only implementations left in U-Boot, which make "use" of the value passed to reset_cpu(). As this is done under false assumption (the value does not have any meaning anymore), it makes sense to bring it into line with the rest and start ignoring the parameter.
This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch.
Fixes: b5a152e7ca0b ("board: ns3: default reset type to L3") Cc: Bharat Gooty bharat.gooty@broadcom.com Cc: Rayagonda Kokatanur rayagonda.kokatanur@broadcom.com Signed-off-by: Harald Seiler hws@denx.de --- board/broadcom/bcmns3/ns3.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index 10ae344a06df..13dbbb826b2f 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -14,9 +14,6 @@ #include <dt-bindings/memory/bcm-ns3-mc.h> #include <broadcom/chimp.h>
-/* Default reset-level = 3 and strap-val = 0 */ -#define L3_RESET 30 - #define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
/* @@ -189,23 +186,8 @@ ulong board_get_usable_ram_top(ulong total_size)
void reset_cpu(ulong level) { - u32 reset_level, strap_val; - - /* Default reset type is L3 reset */ - if (!level) { - /* - * Encoding: U-Boot reset command expects decimal argument, - * Boot strap val: Bits[3:0] - * reset level: Bits[7:4] - */ - strap_val = L3_RESET % 10; - level = L3_RESET / 10; - reset_level = level % 10; - psci_system_reset2(reset_level, strap_val); - } else { - /* U-Boot cmd "reset" with any arg will trigger L1 reset */ - psci_system_reset(); - } + /* Perform a level 3 reset */ + psci_system_reset2(3, 0); }
#ifdef CONFIG_OF_BOARD_SETUP
On Tue, 15 Dec 2020 at 08:48, Harald Seiler hws@denx.de wrote:
The current implementation of reset_cpu() in the ns3 board code does not archieve what it is supposed to (according to the comments), due to a number of reasons:
The argument to reset_cpu() is _not_ actually passed from the `reset` command, but is set to 0 in all call-sites (in this specific case, see arch/arm/lib/reset.c). Thus, performing different kinds of resets based on its value will not work as expected.
Contrary to its documentation, the passed argument is not interpreted, but a static `L3_RESET` define is used. The other comment properly notes that this will always perform a L3 reset, though.
The "parsing" of the static `L3_RESET` value is not even using the upper and lower nibble as stated in the comment, but uses the last two decimal digits of the value.
This is currently one of the only implementations left in U-Boot, which make "use" of the value passed to reset_cpu(). As this is done under false assumption (the value does not have any meaning anymore), it makes sense to bring it into line with the rest and start ignoring the parameter.
This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch.
Fixes: b5a152e7ca0b ("board: ns3: default reset type to L3") Cc: Bharat Gooty bharat.gooty@broadcom.com Cc: Rayagonda Kokatanur rayagonda.kokatanur@broadcom.com Signed-off-by: Harald Seiler hws@denx.de
board/broadcom/bcmns3/ns3.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Tue, Dec 15, 2020 at 04:47:50PM +0100, Harald Seiler wrote:
The current implementation of reset_cpu() in the ns3 board code does not archieve what it is supposed to (according to the comments), due to a number of reasons:
The argument to reset_cpu() is _not_ actually passed from the `reset` command, but is set to 0 in all call-sites (in this specific case, see arch/arm/lib/reset.c). Thus, performing different kinds of resets based on its value will not work as expected.
Contrary to its documentation, the passed argument is not interpreted, but a static `L3_RESET` define is used. The other comment properly notes that this will always perform a L3 reset, though.
The "parsing" of the static `L3_RESET` value is not even using the upper and lower nibble as stated in the comment, but uses the last two decimal digits of the value.
This is currently one of the only implementations left in U-Boot, which make "use" of the value passed to reset_cpu(). As this is done under false assumption (the value does not have any meaning anymore), it makes sense to bring it into line with the rest and start ignoring the parameter.
This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch.
Fixes: b5a152e7ca0b ("board: ns3: default reset type to L3") Cc: Bharat Gooty bharat.gooty@broadcom.com Cc: Rayagonda Kokatanur rayagonda.kokatanur@broadcom.com Signed-off-by: Harald Seiler hws@denx.de Reviewed-by: Simon Glass sjg@chromium.org
(Er, 1/4 had the wrong branch ...) Applied to u-boot/next, thanks!
This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.
The paramter passed to reset_cpu() no longer holds a meaning as all call-sites now pass the value 0. Thus, branching on it is essentially dead code and will just confuse future readers.
Revert soft-reset support and just always perform a hard-reset for now. This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch.
Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset") Cc: Sylvain Lemieux slemieux@tycoint.com Signed-off-by: Harald Seiler hws@denx.de --- arch/arm/mach-lpc32xx/cpu.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index 32af6206056b..7378192a33c2 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -22,23 +22,12 @@ void reset_cpu(ulong addr) /* Enable watchdog clock */ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
- /* To be compatible with the original U-Boot code: - * addr: - 0: perform hard reset. - * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */ - if (addr == 0) { - /* Reset pulse length is 13005 peripheral clock frames */ - writel(13000, &wdt->pulse); + /* Reset pulse length is 13005 peripheral clock frames */ + writel(13000, &wdt->pulse);
- /* Force WDOG_RESET2 and RESOUT_N signal active */ - writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 - | WDTIM_MCTRL_M_RES2, &wdt->mctrl); - } else { - /* Force match output active */ - writel(0x01, &wdt->emr); - - /* Internal reset on match output (no pulse on "RESOUT_N") */ - writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); - } + /* Force WDOG_RESET2 and RESOUT_N signal active */ + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, + &wdt->mctrl);
while (1) /* NOP */;
Hi,
This functionality (soft vs hard reset) is used in multiple LPC32xx products with our custom hardware.
If this support is remove from upstream, we will have to maintain this patch locally (out of tree).
Sylvain Lemieux
-----Original Message----- From: Harald Seiler hws@denx.de Sent: Tuesday, December 15, 2020 10:48 AM To: u-boot@lists.denx.de Cc: Harald Seiler hws@denx.de; Tom Rini trini@konsulko.com; Simon Glass sjg@chromium.org; Sylvain Lemieux sylvain.lemieux@jci.com Subject: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.
The paramter passed to reset_cpu() no longer holds a meaning as all call-sites now pass the value 0. Thus, branching on it is essentially dead code and will just confuse future readers.
Revert soft-reset support and just always perform a hard-reset for now. This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch.
Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset") Cc: Sylvain Lemieux slemieux@tycoint.com Signed-off-by: Harald Seiler hws@denx.de --- arch/arm/mach-lpc32xx/cpu.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index 32af6206056b..7378192a33c2 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -22,23 +22,12 @@ void reset_cpu(ulong addr) /* Enable watchdog clock */ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
- /* To be compatible with the original U-Boot code: - * addr: - 0: perform hard reset. - * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */ - if (addr == 0) { - /* Reset pulse length is 13005 peripheral clock frames */ - writel(13000, &wdt->pulse); + /* Reset pulse length is 13005 peripheral clock frames */ + writel(13000, &wdt->pulse);
- /* Force WDOG_RESET2 and RESOUT_N signal active */ - writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 - | WDTIM_MCTRL_M_RES2, &wdt->mctrl); - } else { - /* Force match output active */ - writel(0x01, &wdt->emr); - - /* Internal reset on match output (no pulse on "RESOUT_N") */ - writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); - } + /* Force WDOG_RESET2 and RESOUT_N signal active */ + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, + &wdt->mctrl);
while (1) /* NOP */; -- 2.26.2
Hello Sylvain,
On Tue, 2020-12-15 at 17:29 +0000, Sylvain Lemieux wrote:
Hi,
This functionality (soft vs hard reset) is used in multiple LPC32xx products with our custom hardware.
If this support is remove from upstream, we will have to maintain this patch locally (out of tree).
My intention with this series is of course not to break existing and useful functionality. Can you elaborate how you are making use of this differentiation in its current form? Does some board code call reset_cpu() directly, with different parameter values?
I would argue that at this time, the proper way to support both soft-reset and hard-reset is via a sysreset driver, see `drivers/sysreset/sysreset_psci.c` for a simple example. As I laid out in the cover letter of this series, the `addr` parameter to reset_cpu() does not really fit this purpose.
Regards,
Hi Harald,
Yes, we have board code that will call this function with a different value to generate a soft reset (i.e. no pulse on "RESOUT_N"). We have a need to be able to reset the processor (soft or hard) based on the need to generate or not a pulse on RESOUT_N signal.
We will be able to keep this patch local until somebody in the team look at a sysreset driver implementation.
Regards, Sylvain Lemieux
-----Original Message----- From: Harald Seiler hws@denx.de Sent: Thursday, December 17, 2020 5:09 AM To: Sylvain Lemieux sylvain.lemieux@jci.com; u-boot@lists.denx.de Cc: Tom Rini trini@konsulko.com; Simon Glass sjg@chromium.org Subject: Re: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
Hello Sylvain,
On Tue, 2020-12-15 at 17:29 +0000, Sylvain Lemieux wrote:
Hi,
This functionality (soft vs hard reset) is used in multiple LPC32xx products with our custom hardware.
If this support is remove from upstream, we will have to maintain this patch locally (out of tree).
My intention with this series is of course not to break existing and useful functionality. Can you elaborate how you are making use of this differentiation in its current form? Does some board code call reset_cpu() directly, with different parameter values?
I would argue that at this time, the proper way to support both soft-reset and hard-reset is via a sysreset driver, see `drivers/sysreset/sysreset_psci.c` for a simple example. As I laid out in the cover letter of this series, the `addr` parameter to reset_cpu() does not really fit this purpose.
Regards, -- Harald
Sylvain Lemieux
-----Original Message----- From: Harald Seiler hws@denx.de Sent: Tuesday, December 15, 2020 10:48 AM To: u-boot@lists.denx.de Cc: Harald Seiler hws@denx.de; Tom Rini trini@konsulko.com; Simon Glass sjg@chromium.org; Sylvain Lemieux sylvain.lemieux@jci.com Subject: [PATCH 3/4] Revert "lpc32xx: cpu: add support for soft reset"
This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.
The paramter passed to reset_cpu() no longer holds a meaning as all call-sites now pass the value 0. Thus, branching on it is essentially dead code and will just confuse future readers.
Revert soft-reset support and just always perform a hard-reset for now. This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch.
Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset") Cc: Sylvain Lemieux slemieux@tycoint.com Signed-off-by: Harald Seiler hws@denx.de
arch/arm/mach-lpc32xx/cpu.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index 32af6206056b..7378192a33c2 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -22,23 +22,12 @@ void reset_cpu(ulong addr) /* Enable watchdog clock */ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); - /* To be compatible with the original U-Boot code: - * addr: - 0: perform hard reset. - * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */ - if (addr == 0) { - /* Reset pulse length is 13005 peripheral clock frames */ - writel(13000, &wdt->pulse); + /* Reset pulse length is 13005 peripheral clock frames */ + writel(13000, &wdt->pulse); - /* Force WDOG_RESET2 and RESOUT_N signal active */ - writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 - | WDTIM_MCTRL_M_RES2, &wdt->mctrl); - } else { - /* Force match output active */ - writel(0x01, &wdt->emr);
- /* Internal reset on match output (no pulse on "RESOUT_N") */ - writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl); - } + /* Force WDOG_RESET2 and RESOUT_N signal active */ + writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | +WDTIM_MCTRL_M_RES2, + &wdt->mctrl); while (1) /* NOP */; -- 2.26.2
-- Harald
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-62 Fax: +49-8142-66989-80 Email: hws@denx.de
On Tue, Dec 15, 2020 at 04:47:51PM +0100, Harald Seiler wrote:
This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f.
The paramter passed to reset_cpu() no longer holds a meaning as all call-sites now pass the value 0. Thus, branching on it is essentially dead code and will just confuse future readers.
Revert soft-reset support and just always perform a hard-reset for now. This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch.
Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset") Cc: Sylvain Lemieux slemieux@tycoint.com Signed-off-by: Harald Seiler hws@denx.de Signed-off-by: Harald Seiler hws@denx.de
Applied to u-boot/next, thanks!
Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead.
This transformation was done with the following coccinelle patch:
@@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu()
@@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... }
Signed-off-by: Harald Seiler hws@denx.de --- arch/arc/lib/reset.c | 4 ++-- arch/arm/cpu/arm920t/ep93xx/cpu.c | 2 +- arch/arm/cpu/arm920t/imx/timer.c | 2 +- arch/arm/cpu/arm926ejs/armada100/timer.c | 2 +- arch/arm/cpu/arm926ejs/mx25/reset.c | 2 +- arch/arm/cpu/arm926ejs/mx27/reset.c | 2 +- arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++-- arch/arm/cpu/arm926ejs/spear/reset.c | 2 +- arch/arm/cpu/arm946es/cpu.c | 2 +- arch/arm/cpu/armv7/bcm281xx/reset.c | 2 +- arch/arm/cpu/armv7/bcmcygnus/reset.c | 2 +- arch/arm/cpu/armv7/bcmnsp/reset.c | 2 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/s5p4418/cpu.c | 2 +- arch/arm/cpu/armv7/stv0991/reset.c | 2 +- arch/arm/cpu/armv7m/cpu.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++-- arch/arm/cpu/armv8/s32v234/generic.c | 2 +- arch/arm/cpu/pxa/pxa2xx.c | 4 ++-- arch/arm/cpu/sa1100/cpu.c | 2 +- arch/arm/lib/interrupts.c | 2 +- arch/arm/lib/interrupts_m.c | 2 +- arch/arm/lib/reset.c | 2 +- arch/arm/mach-at91/arm920t/reset.c | 2 +- arch/arm/mach-at91/arm926ejs/reset.c | 2 +- arch/arm/mach-at91/armv7/reset.c | 2 +- arch/arm/mach-bcm283x/reset.c | 2 +- arch/arm/mach-davinci/reset.c | 2 +- arch/arm/mach-exynos/soc.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/mx7ulp/soc.c | 2 +- arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-keystone/ddr3.c | 4 ++-- arch/arm/mach-keystone/init.c | 2 +- arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-lpc32xx/cpu.c | 2 +- arch/arm/mach-mediatek/mt7622/init.c | 2 +- arch/arm/mach-mediatek/mt8512/init.c | 2 +- arch/arm/mach-mediatek/mt8516/init.c | 2 +- arch/arm/mach-mediatek/mt8518/init.c | 2 +- arch/arm/mach-meson/board-common.c | 4 ++-- arch/arm/mach-mvebu/armada3700/cpu.c | 2 +- arch/arm/mach-mvebu/armada8k/cpu.c | 2 +- arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-octeontx/cpu.c | 2 +- arch/arm/mach-octeontx2/cpu.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- arch/arm/mach-omap2/reset.c | 2 +- arch/arm/mach-orion5x/cpu.c | 2 +- arch/arm/mach-owl/soc.c | 2 +- arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +- arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-tegra/cmd_enterrcm.c | 2 +- arch/arm/mach-tegra/pmc.c | 2 +- arch/arm/mach-uniphier/arm32/psci.c | 2 +- arch/arm/mach-uniphier/reset.c | 2 +- arch/arm/mach-zynq/cpu.c | 2 +- arch/arm/mach-zynqmp-r5/cpu.c | 2 +- arch/nds32/cpu/n1213/ag101/cpu.c | 2 +- arch/nds32/lib/interrupts.c | 2 +- arch/sandbox/cpu/sdl.c | 4 ++-- arch/sh/cpu/sh4/cpu.c | 2 +- arch/sh/cpu/sh4/watchdog.c | 2 +- arch/x86/cpu/ivybridge/cpu.c | 2 +- board/BuR/brppt2/board.c | 2 +- board/abilis/tb100/tb100.c | 2 +- board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 2 +- board/armltd/total_compute/total_compute.c | 2 +- board/armltd/vexpress/vexpress_common.c | 2 +- board/armltd/vexpress64/vexpress64.c | 2 +- board/atmark-techno/armadillo-800eva/armadillo-800eva.c | 2 +- board/beacon/beacon-rzg2m/beacon-rzg2m.c | 2 +- board/bosch/shc/board.c | 2 +- board/broadcom/bcmns2/northstar2.c | 2 +- board/broadcom/bcmns3/ns3.c | 2 +- board/broadcom/bcmstb/bcmstb.c | 2 +- board/cavium/thunderx/thunderx.c | 2 +- board/compulab/cm_t335/spl.c | 2 +- board/cortina/presidio-asic/presidio.c | 2 +- board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/freescale/mx6memcal/spl.c | 2 +- board/ge/b1x5v2/spl.c | 2 +- board/highbank/highbank.c | 2 +- board/hisilicon/hikey/hikey.c | 2 +- board/hisilicon/hikey960/hikey960.c | 2 +- board/hisilicon/poplar/poplar.c | 2 +- board/kmc/kzm9g/kzm9g.c | 2 +- board/liebherr/display5/spl.c | 2 +- board/phytium/durian/durian.c | 2 +- board/qualcomm/dragonboard410c/dragonboard410c.c | 2 +- board/qualcomm/dragonboard820c/dragonboard820c.c | 2 +- board/renesas/alt/alt.c | 2 +- board/renesas/alt/alt_spl.c | 2 +- board/renesas/blanche/blanche.c | 2 +- board/renesas/condor/condor.c | 2 +- board/renesas/draak/draak.c | 2 +- board/renesas/eagle/eagle.c | 2 +- board/renesas/ebisu/ebisu.c | 2 +- board/renesas/gose/gose.c | 2 +- board/renesas/gose/gose_spl.c | 2 +- board/renesas/grpeach/grpeach.c | 2 +- board/renesas/koelsch/koelsch.c | 2 +- board/renesas/koelsch/koelsch_spl.c | 2 +- board/renesas/lager/lager.c | 2 +- board/renesas/lager/lager_spl.c | 2 +- board/renesas/porter/porter.c | 2 +- board/renesas/porter/porter_spl.c | 2 +- board/renesas/rcar-common/gen3-spl.c | 2 +- board/renesas/salvator-x/salvator-x.c | 2 +- board/renesas/silk/silk.c | 2 +- board/renesas/silk/silk_spl.c | 2 +- board/renesas/stout/cpld.c | 2 +- board/renesas/stout/stout_spl.c | 2 +- board/siemens/capricorn/board.c | 2 +- board/synopsys/emsdp/emsdp.c | 2 +- board/synopsys/iot_devkit/iot_devkit.c | 2 +- board/technexion/pico-imx6ul/spl.c | 2 +- board/technexion/pico-imx7d/spl.c | 2 +- board/toradex/apalis-imx8/apalis-imx8.c | 2 +- board/toradex/apalis-imx8x/apalis-imx8x.c | 2 +- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri-imx8x/colibri-imx8x.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/toradex/colibri_imx7/colibri_imx7.c | 2 +- board/xen/xenguest_arm64/xenguest_arm64.c | 2 +- board/xilinx/versal/board.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- cmd/tpm_test.c | 2 +- drivers/sysreset/sysreset-uclass.c | 2 +- drivers/watchdog/imx_watchdog.c | 2 +- drivers/watchdog/ulp_wdog.c | 2 +- include/cpu_func.h | 4 ++-- include/sysreset.h | 2 +- 134 files changed, 142 insertions(+), 142 deletions(-)
diff --git a/arch/arc/lib/reset.c b/arch/arc/lib/reset.c index fbb56ec83af0..b8589d0f0a47 100644 --- a/arch/arc/lib/reset.c +++ b/arch/arc/lib/reset.c @@ -7,7 +7,7 @@ #include <common.h> #include <cpu_func.h>
-__weak void reset_cpu(ulong addr) +__weak void reset_cpu(void) { /* Stop debug session here */ __builtin_arc_brk(); @@ -17,7 +17,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { printf("Resetting the board...\n");
- reset_cpu(0); + reset_cpu();
return 0; } diff --git a/arch/arm/cpu/arm920t/ep93xx/cpu.c b/arch/arm/cpu/arm920t/ep93xx/cpu.c index c9ea4e46a870..3435bdc748a2 100644 --- a/arch/arm/cpu/arm920t/ep93xx/cpu.c +++ b/arch/arm/cpu/arm920t/ep93xx/cpu.c @@ -14,7 +14,7 @@ #include <asm/io.h>
/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */ -extern void reset_cpu(ulong addr) +extern void reset_cpu(void) { struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; uint32_t value; diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c index e9d55779214b..0cd3a039810b 100644 --- a/arch/arm/cpu/arm920t/imx/timer.c +++ b/arch/arm/cpu/arm920t/imx/timer.c @@ -81,7 +81,7 @@ ulong get_tbclk(void) /* * Reset the cpu by setting up the watchdog timer and let him time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Disable watchdog and set Time-Out field to 0 */ WCR = 0x00000000; diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c index 0f1e68c8355f..d4d580b98d2a 100644 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c @@ -141,7 +141,7 @@ int timer_init(void) * 2. Write key value to TMP_WSAR reg. * 3. Perform write operation. */ -void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct armd1mpmu_registers *mpmu = (struct armd1mpmu_registers *) ARMD1_MPMU_BASE; diff --git a/arch/arm/cpu/arm926ejs/mx25/reset.c b/arch/arm/cpu/arm926ejs/mx25/reset.c index 38df1c940227..7844a99c1640 100644 --- a/arch/arm/cpu/arm926ejs/mx25/reset.c +++ b/arch/arm/cpu/arm926ejs/mx25/reset.c @@ -23,7 +23,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c index 320b0a65e70b..496fb30817db 100644 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ b/arch/arm/cpu/arm926ejs/mx27/reset.c @@ -23,7 +23,7 @@ /* * Reset the cpu by setting up the watchdog timer and let it time out */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 8243aeb2c0f6..ddc47b9659c5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -31,9 +31,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Lowlevel init isn't used on i.MX28, so just have a dummy here */ __weak void lowlevel_init(void) {}
-void reset_cpu(ulong ignored) __attribute__((noreturn)); +void reset_cpu(void) __attribute__((noreturn));
-void reset_cpu(ulong ignored) +void reset_cpu(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c index a316540d52a8..97a624e16cd0 100644 --- a/arch/arm/cpu/arm926ejs/spear/reset.c +++ b/arch/arm/cpu/arm926ejs/spear/reset.c @@ -11,7 +11,7 @@ #include <asm/arch/spr_syscntl.h> #include <linux/delay.h>
-void reset_cpu(ulong ignored) +void reset_cpu(void) { struct syscntl_regs *syscntl_regs_p = (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c index fb0ea5e817ff..334bb5427432 100644 --- a/arch/arm/cpu/arm946es/cpu.c +++ b/arch/arm/cpu/arm946es/cpu.c @@ -56,7 +56,7 @@ static void cache_flush (void)
#ifndef CONFIG_ARCH_INTEGRATOR
-__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +__attribute__((noreturn)) void reset_cpu(void) { writew(0x0, 0xfffece10); writew(0x8, 0xfffece10); diff --git a/arch/arm/cpu/armv7/bcm281xx/reset.c b/arch/arm/cpu/armv7/bcm281xx/reset.c index fda5a9527ec3..1491e5c88b20 100644 --- a/arch/arm/cpu/armv7/bcm281xx/reset.c +++ b/arch/arm/cpu/armv7/bcm281xx/reset.c @@ -13,7 +13,7 @@ #define CLKS_SHIFT 20 /* Clock period shift */ #define LD_SHIFT 0 /* Reload value shift */
-void reset_cpu(ulong ignored) +void reset_cpu(void) { /* * Set WD enable, RST enable, diff --git a/arch/arm/cpu/armv7/bcmcygnus/reset.c b/arch/arm/cpu/armv7/bcmcygnus/reset.c index 3bfed34533bd..63992fd87018 100644 --- a/arch/arm/cpu/armv7/bcmcygnus/reset.c +++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c @@ -10,7 +10,7 @@ #define CRMU_MAIL_BOX1 0x03024028 #define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
-void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Send soft reset command via Mailbox. */ writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1); diff --git a/arch/arm/cpu/armv7/bcmnsp/reset.c b/arch/arm/cpu/armv7/bcmnsp/reset.c index 675f99fe998f..a3137752e886 100644 --- a/arch/arm/cpu/armv7/bcmnsp/reset.c +++ b/arch/arm/cpu/armv7/bcmnsp/reset.c @@ -9,7 +9,7 @@
#define CRU_RESET_OFFSET 0x1803F184
-void reset_cpu(ulong ignored) +void reset_cpu(void) { /* Reset the cpu by setting software reset request bit */ writel(0x1, CRU_RESET_OFFSET); diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce472aa9bd54..ae7bc0fbbd55 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -372,7 +372,7 @@ void smp_kick_all_cpus(void) } #endif
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 8add9474ad23..256a803b14dd 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -87,7 +87,7 @@ int print_cpuinfo(void) } #endif
-void reset_cpu(ulong ignored) +void reset_cpu(void) { void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR; const u32 sw_rst_enb_bitpos = 3; diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c index fb67de10f483..77d4477c8dc5 100644 --- a/arch/arm/cpu/armv7/stv0991/reset.c +++ b/arch/arm/cpu/armv7/stv0991/reset.c @@ -9,7 +9,7 @@ #include <asm/io.h> #include <asm/arch/stv0991_wdru.h> #include <linux/delay.h> -void reset_cpu(ulong ignored) +void reset_cpu(void) { puts("System is going to reboot ...\n"); /* diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index 7f827da033bf..63721018c168 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -47,7 +47,7 @@ int cleanup_before_linux(void) /* * Perform the low-level reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* * Perform reset but keep priority group unchanged. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 1a5d26b5372e..2141edcd2460 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1230,7 +1230,7 @@ int timer_init(void)
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
-void __efi_runtime reset_cpu(ulong addr) +void __efi_runtime reset_cpu(void) { #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) /* clear the RST_REQ_MSK and SW_RST_REQ */ @@ -1259,7 +1259,7 @@ void __efi_runtime EFIAPI efi_reset_system( case EFI_RESET_COLD: case EFI_RESET_WARM: case EFI_RESET_PLATFORM_SPECIFIC: - reset_cpu(0); + reset_cpu(); break; case EFI_RESET_SHUTDOWN: /* Nothing we can do */ diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c index de5a098adb8f..ee676e44a8b0 100644 --- a/arch/arm/cpu/armv8/s32v234/generic.c +++ b/arch/arm/cpu/armv8/s32v234/generic.c @@ -318,7 +318,7 @@ static char *get_reset_cause(void)
#define SRC_SCR_SW_RST (1<<12)
-void reset_cpu(ulong addr) +void reset_cpu(void) { printf("Feature not supported.\n"); }; diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index ea91d8aaec2b..c7efb67754e6 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -267,9 +267,9 @@ void i2c_clk_enable(void) writel(readl(CKEN) | CKEN14_I2C, CKEN); }
-void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn)); +void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
-void reset_cpu(ulong ignored) +void reset_cpu(void) { uint32_t tmp;
diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c index 91e100af1b67..6f67f7fc2284 100644 --- a/arch/arm/cpu/sa1100/cpu.c +++ b/arch/arm/cpu/sa1100/cpu.c @@ -55,7 +55,7 @@ static void cache_flush (void) #define RSRR 0x00 #define RCSR 0x04
-__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused))) +__attribute__((noreturn)) void reset_cpu(void) { /* repeat endlessly */ while (1) { diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 703be5a3209c..1ca00e2ac11e 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -52,7 +52,7 @@ int disable_interrupts(void) void bad_mode (void) { panic ("Resetting CPU ...\n"); - reset_cpu(0); + reset_cpu(); }
static void show_efi_loaded_images(struct pt_regs *regs) diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c index 2ae1c5ba76c9..277854aa878c 100644 --- a/arch/arm/lib/interrupts_m.c +++ b/arch/arm/lib/interrupts_m.c @@ -59,7 +59,7 @@ void dump_regs(struct autosave_regs *regs) void bad_mode(void) { panic("Resetting CPU ...\n"); - reset_cpu(0); + reset_cpu(); }
void do_hard_fault(struct autosave_regs *autosave_regs) diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 4f1a768bfe13..95169bae1c13 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -39,7 +39,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) disable_interrupts();
reset_misc(); - reset_cpu(0); + reset_cpu();
/*NOTREACHED*/ return 0; diff --git a/arch/arm/mach-at91/arm920t/reset.c b/arch/arm/mach-at91/arm920t/reset.c index d92bc57d6690..91e375146ad7 100644 --- a/arch/arm/mach-at91/arm920t/reset.c +++ b/arch/arm/mach-at91/arm920t/reset.c @@ -24,7 +24,7 @@ void __attribute__((weak)) board_reset(void) /* true empty function for defining weak symbol */ }
-void reset_cpu(ulong ignored) +void reset_cpu(void) { at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
diff --git a/arch/arm/mach-at91/arm926ejs/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c index 56fbbd991e5d..6acbfa33011d 100644 --- a/arch/arm/mach-at91/arm926ejs/reset.c +++ b/arch/arm/mach-at91/arm926ejs/reset.c @@ -12,7 +12,7 @@ #include <asm/arch/at91_rstc.h>
/* Reset the cpu by telling the reset controller to do so */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
diff --git a/arch/arm/mach-at91/armv7/reset.c b/arch/arm/mach-at91/armv7/reset.c index 8f4c81d1afd5..1ea415ea9ef4 100644 --- a/arch/arm/mach-at91/armv7/reset.c +++ b/arch/arm/mach-at91/armv7/reset.c @@ -15,7 +15,7 @@ #include <asm/arch/at91_rstc.h>
/* Reset the cpu by telling the reset controller to do so */ -void reset_cpu(ulong ignored) +void reset_cpu(void) { at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index 2b4ccd47279f..f13ac0c63757 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -48,7 +48,7 @@ __reset_cpu(struct bcm2835_wdog_regs *wdog_regs, ulong ticks) writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc); }
-void reset_cpu(ulong ticks) +void reset_cpu(void) { struct bcm2835_wdog_regs *regs = (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR; diff --git a/arch/arm/mach-davinci/reset.c b/arch/arm/mach-davinci/reset.c index 4e6031a593b7..0d59eb6e3cef 100644 --- a/arch/arm/mach-davinci/reset.c +++ b/arch/arm/mach-davinci/reset.c @@ -12,7 +12,7 @@ #include <asm/arch/timer_defs.h> #include <asm/arch/hardware.h>
-void reset_cpu(unsigned long a) +void reset_cpu(void) { struct davinci_timer *const wdttimer = (struct davinci_timer *)DAVINCI_WDOG_BASE; diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index 810fa348eeaf..a07c87a2c8e2 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -20,7 +20,7 @@ extern void _main(void); void *secondary_boot_addr = (void *)_main; #endif /* CONFIG_TARGET_ESPRESSO7420 */
-void reset_cpu(ulong addr) +void reset_cpu(void) { #ifdef CONFIG_CPU_V7A writel(0x1, samsung_get_base_swreset()); diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5df8e175101d..7178b65b15e5 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -909,7 +909,7 @@ usb_modify_speed: #endif
#if !CONFIG_IS_ENABLED(SYSRESET) -void reset_cpu(ulong addr) +void reset_cpu(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 8dd6b4d40e77..320f24dd2969 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -197,7 +197,7 @@ void s_init(void) #endif
#ifndef CONFIG_ULP_WATCHDOG -void reset_cpu(ulong addr) +void reset_cpu(void) { setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET); while (1) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 8c903f14ff87..589c37ed28c8 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -319,7 +319,7 @@ int fdt_disable_node(void *blob, char *node_path) #endif
#ifndef CONFIG_SYSRESET -void reset_cpu(ulong ignored) +void reset_cpu(void) { } #endif diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 7dea600d509b..9ee328415682 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -345,7 +345,7 @@ void ddr3_check_ecc_int(u32 base)
if (!ecc_test) { puts("Reseting the device ...\n"); - reset_cpu(0); + reset_cpu(); } }
@@ -445,7 +445,7 @@ void ddr3_err_reset_workaround(void) tmp &= ~KS2_RSTYPE_PLL_SOFT; __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
- reset_cpu(0); + reset_cpu(); } } #endif diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 88e8912959fa..d893d3ccc163 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -192,7 +192,7 @@ int arch_cpu_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL); u32 tmp; diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 551c22a8ea1e..9c818fa45e8d 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -19,7 +19,7 @@ #include <asm/arch/soc.h> #include <mvebu_mmc.h>
-void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct kwcpu_registers *cpureg = (struct kwcpu_registers *)KW_CPU_REG_BASE; diff --git a/arch/arm/mach-lpc32xx/cpu.c b/arch/arm/mach-lpc32xx/cpu.c index 7378192a33c2..c2586d092956 100644 --- a/arch/arm/mach-lpc32xx/cpu.c +++ b/arch/arm/mach-lpc32xx/cpu.c @@ -17,7 +17,7 @@ static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
-void reset_cpu(ulong addr) +void reset_cpu(void) { /* Enable watchdog clock */ setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c index 7f6ce80f37b2..e501907b5351 100644 --- a/arch/arm/mach-mediatek/mt7622/init.c +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -27,7 +27,7 @@ int dram_init(void)
}
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index aa779f437663..0ac01ce41a17 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -42,7 +42,7 @@ int dram_init_banksize(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *watchdog_dev = NULL;
diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index 13be39122115..64b6ea6c5767 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -84,7 +84,7 @@ int mtk_soc_early_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c index 531a403da1b0..ffbef32550a5 100644 --- a/arch/arm/mach-mediatek/mt8518/init.c +++ b/arch/arm/mach-mediatek/mt8518/init.c @@ -41,7 +41,7 @@ int dram_init_banksize(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index 7ea0ed479474..dcbc2faf9c5c 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -166,7 +166,7 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct pt_regs regs;
@@ -181,7 +181,7 @@ void reset_cpu(ulong addr) ; } #else -void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index e438b4922e14..829527fa6f8f 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -313,7 +313,7 @@ int a3700_fdt_fix_pcie_regions(void *blob) return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len); }
-void reset_cpu(ulong ignored) +void reset_cpu(void) { /* * Write magic number of 0x1d1e to North Bridge Warm Reset register diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 529dac905951..474327a8e1c9 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -104,7 +104,7 @@ void enable_caches(void) dcache_enable(); }
-void reset_cpu(ulong ignored) +void reset_cpu(void) { u32 reg;
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 7dce11e77f36..0b935c46fb8a 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -42,7 +42,7 @@ void lowlevel_init(void) */ }
-void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct mvebu_system_registers *reg = (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE; diff --git a/arch/arm/mach-octeontx/cpu.c b/arch/arm/mach-octeontx/cpu.c index 9c29c31393cc..193b1a1296f5 100644 --- a/arch/arm/mach-octeontx/cpu.c +++ b/arch/arm/mach-octeontx/cpu.c @@ -71,6 +71,6 @@ u64 get_page_table_size(void) return 0x80000; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/arch/arm/mach-octeontx2/cpu.c b/arch/arm/mach-octeontx2/cpu.c index 2a6d5e86613c..76d0156d5a3e 100644 --- a/arch/arm/mach-octeontx2/cpu.c +++ b/arch/arm/mach-octeontx2/cpu.c @@ -67,6 +67,6 @@ u64 get_page_table_size(void) return 0x80000; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 47ac8656bfe1..edab9a92982e 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -417,7 +417,7 @@ void omap_die_id(unsigned int *die_id) die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); }
-void reset_cpu(ulong ignored) +void reset_cpu(void) { u32 omap_rev = omap_revision();
diff --git a/arch/arm/mach-omap2/reset.c b/arch/arm/mach-omap2/reset.c index 2bbd5fcb9b8e..1fd79c2e8a43 100644 --- a/arch/arm/mach-omap2/reset.c +++ b/arch/arm/mach-omap2/reset.c @@ -14,7 +14,7 @@ #include <asm/arch/cpu.h> #include <linux/compiler.h>
-void __weak reset_cpu(unsigned long ignored) +void __weak reset_cpu(void) { writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); } diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index beae7b84843b..ffae9a01e37c 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -20,7 +20,7 @@
#define BUFLEN 16
-void reset_cpu(unsigned long ignored) +void reset_cpu(void) { struct orion5x_cpu_registers *cpureg = (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index fd6ee7c1c0f2..d4cbc160e7cb 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -73,7 +73,7 @@ int board_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 7844ad14cb66..e1e46cba22dc 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -8,7 +8,7 @@
phys_addr_t socfpga_get_rstmgr_addr(void);
-void reset_cpu(ulong addr); +void reset_cpu(void);
void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index f40fccd8f8b9..ecba5c3ecd1d 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -315,7 +315,7 @@ void board_init_f(ulong dummy) } #endif
-void reset_cpu(ulong addr) +void reset_cpu(void) { #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) static const struct sunxi_wdog *wdog = diff --git a/arch/arm/mach-tegra/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index 25df31a3b858..92ff6cb1bf86 100644 --- a/arch/arm/mach-tegra/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c @@ -40,7 +40,7 @@ static int do_enterrcm(struct cmd_tbl *cmdtp, int flag, int argc,
tegra_pmc_writel(2, PMC_SCRATCH0); disable_interrupts(); - reset_cpu(0); + reset_cpu();
return 0; } diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index cdc8493efd8e..7b0110beb085 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -84,7 +84,7 @@ void tegra_pmc_writel(u32 value, unsigned long offset) writel(value, NV_PA_PMC_BASE + offset); }
-void reset_cpu(ulong addr) +void reset_cpu(void) { u32 value;
diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c index a4d260aecedc..fbb6ebca7740 100644 --- a/arch/arm/mach-uniphier/arm32/psci.c +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -158,5 +158,5 @@ s32 __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point,
void __secure psci_system_reset(void) { - reset_cpu(0); + reset_cpu(); } diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c index 5fffd23e9a5a..dddb48ec4a39 100644 --- a/arch/arm/mach-uniphier/reset.c +++ b/arch/arm/mach-uniphier/reset.c @@ -18,7 +18,7 @@ #define __SECURE #endif
-void __SECURE reset_cpu(unsigned long ignored) +void __SECURE reset_cpu(void) { u32 tmp;
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 3befc120289c..69b818f24b89 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -78,7 +78,7 @@ unsigned int zynq_get_silicon_version(void) >> ZYNQ_SILICON_VER_SHIFT; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { zynq_slcr_cpu_reset(); while (1) diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c index 87c1d75f9f3c..1eb934626b49 100644 --- a/arch/arm/mach-zynqmp-r5/cpu.c +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -29,7 +29,7 @@ int arch_cpu_init(void) /* * Perform the low-level reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { while (1) ; diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c index 9d99c83bf3af..91c3574bce6b 100644 --- a/arch/nds32/cpu/n1213/ag101/cpu.c +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -46,7 +46,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* * reset to the base addr of andesboot. * currently no ROM loader at addr 0. - * do not use reset_cpu(0); + * do not use reset_cpu(); */ #ifdef CONFIG_FTWDT010_WATCHDOG /* diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c index 1481e055007b..0ec72d157fb5 100644 --- a/arch/nds32/lib/interrupts.c +++ b/arch/nds32/lib/interrupts.c @@ -66,7 +66,7 @@ int disable_interrupts(void) void bad_mode(void) { panic("Resetting CPU ...\n"); - reset_cpu(0); + reset_cpu(); }
void show_regs(struct pt_regs *regs) diff --git a/arch/sandbox/cpu/sdl.c b/arch/sandbox/cpu/sdl.c index d4dab3698161..8102649be3a4 100644 --- a/arch/sandbox/cpu/sdl.c +++ b/arch/sandbox/cpu/sdl.c @@ -69,14 +69,14 @@ static void sandbox_sdl_poll_events(void) * We don't want to include common.h in this file since it uses * system headers. So add a declation here. */ - extern void reset_cpu(unsigned long addr); + extern void reset_cpu(void); SDL_Event event;
while (SDL_PollEvent(&event)) { switch (event.type) { case SDL_QUIT: puts("LCD window closed - quitting\n"); - reset_cpu(1); + reset_cpu(); break; } } diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c index 801102fc7d5d..1b2f50dbe6e4 100644 --- a/arch/sh/cpu/sh4/cpu.c +++ b/arch/sh/cpu/sh4/cpu.c @@ -32,7 +32,7 @@ int cleanup_before_linux (void) int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { disable_interrupts(); - reset_cpu(0); + reset_cpu(); return 0; }
diff --git a/arch/sh/cpu/sh4/watchdog.c b/arch/sh/cpu/sh4/watchdog.c index 1de32cd419fd..bf403d3c520e 100644 --- a/arch/sh/cpu/sh4/watchdog.c +++ b/arch/sh/cpu/sh4/watchdog.c @@ -51,7 +51,7 @@ int watchdog_disable(void) } #endif
-void reset_cpu(unsigned long ignored) +void reset_cpu(void) { /* Address error with SR.BL=1 first. */ trigger_address_error(); diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index cb6eded9c98d..c6dee94c534c 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -142,7 +142,7 @@ int checkcpu(void)
/* System is not happy after keyboard reset... */ debug("Issuing CF9 warm reset\n"); - reset_cpu(0); + reset_cpu(); }
ret = cpu_common_init(); diff --git a/board/BuR/brppt2/board.c b/board/BuR/brppt2/board.c index f156b552a761..192ab1dfac47 100644 --- a/board/BuR/brppt2/board.c +++ b/board/BuR/brppt2/board.c @@ -539,7 +539,7 @@ void board_init_f(ulong dummy) spl_dram_init(); }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } #endif /* CONFIG_SPL_BUILD */ diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c index 52dc5b8d8673..89e73225a7df 100644 --- a/board/abilis/tb100/tb100.c +++ b/board/abilis/tb100/tb100.c @@ -9,7 +9,7 @@ #include <netdev.h> #include <asm/io.h>
-void reset_cpu(ulong addr) +void reset_cpu(void) { #define CRM_SWRESET 0xff101044 writel(0x1, (void *)CRM_SWRESET); diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index ea057d27cf35..5036762a45af 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -114,7 +114,7 @@ int board_init(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* TODO */ } diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 0be6435fe3ba..98988dad9b53 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -62,6 +62,6 @@ int dram_init_banksize(void) }
/* Nothing to be done here as handled by PSCI interface */ -void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 8fea8ff35294..7ab77ce58d74 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -173,7 +173,7 @@ int v2m_cfg_write(u32 devfn, u32 data) }
/* Use the ARM Watchdog System to cause reset */ -void reset_cpu(ulong addr) +void reset_cpu(void) { if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) printf("Unable to reboot\n"); diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 52ada0f6bce7..0ea53ccf4379 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -142,7 +142,7 @@ void *board_fdt_blob_setup(void) #endif
/* Actual reset is done via PSCI. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c index a18fb275d9f5..8c8bef210833 100644 --- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c +++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c @@ -321,6 +321,6 @@ int board_late_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/beacon/beacon-rzg2m/beacon-rzg2m.c b/board/beacon/beacon-rzg2m/beacon-rzg2m.c index 86a24dd0658f..9561956fc725 100644 --- a/board/beacon/beacon-rzg2m/beacon-rzg2m.c +++ b/board/beacon/beacon-rzg2m/beacon-rzg2m.c @@ -46,7 +46,7 @@ int dram_init_banksize(void) #define RST_CA57RESCNT (RST_BASE + 0x40) #define RST_CODE 0xA5A5000F
-void reset_cpu(ulong addr) +void reset_cpu(void) { writel(RST_CODE, RST_CA57RESCNT); } diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index b8f1b56502e6..f3a926f581d8 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -485,7 +485,7 @@ static void bosch_check_reset_pin(void) printf("Resetting ...\n"); writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); disable_interrupts(); - reset_cpu(0); + reset_cpu(); /*NOTREACHED*/ } } diff --git a/board/broadcom/bcmns2/northstar2.c b/board/broadcom/bcmns2/northstar2.c index 91f489aad3f2..a8e0cd5dd587 100644 --- a/board/broadcom/bcmns2/northstar2.c +++ b/board/broadcom/bcmns2/northstar2.c @@ -56,7 +56,7 @@ int dram_init_banksize(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index 13dbbb826b2f..411e6dcf8aaf 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -184,7 +184,7 @@ ulong board_get_usable_ram_top(ulong total_size) return BCM_NS3_MEM_END; }
-void reset_cpu(ulong level) +void reset_cpu(void) { /* Perform a level 3 reset */ psci_system_reset2(3, 0); diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index add4285db31d..a2dcdd24b228 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -42,7 +42,7 @@ u32 get_board_rev(void) return 0; }
-void reset_cpu(ulong ignored) +void reset_cpu(void) { }
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index f8c2913eace0..f3541f183d6a 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -109,7 +109,7 @@ int dram_init(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c index 8662632a7e39..33264dfa71fc 100644 --- a/board/compulab/cm_t335/spl.c +++ b/board/compulab/cm_t335/spl.c @@ -96,7 +96,7 @@ static void probe_sdram_size(long size) break; default: puts("Failed configuring DRAM, resetting...\n\n"); - reset_cpu(0); + reset_cpu(); } debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); config_ddr(303, &ioregs, &ddr3_data, diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c index 3c132f127179..64461266d2d6 100644 --- a/board/cortina/presidio-asic/presidio.c +++ b/board/cortina/presidio-asic/presidio.c @@ -114,7 +114,7 @@ int dram_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); } diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index fba3baa1267e..2f96cde74cd7 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -104,7 +104,7 @@ int board_init(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* TODO */ } diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index da55933e21b2..131f7f55bf7a 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -128,7 +128,7 @@ int board_init(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* TODO */ } diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c index c11eee51b612..0eb247a3537c 100644 --- a/board/freescale/mx6memcal/spl.c +++ b/board/freescale/mx6memcal/spl.c @@ -424,7 +424,7 @@ void board_init_f(ulong dummy) is_cpu_type(MXC_CPU_MX6SL)) { printf("cpu type 0x%x doesn't support 64-bit bus\n", get_cpu_type()); - reset_cpu(0); + reset_cpu(); } } #ifdef CONFIG_MX6SL diff --git a/board/ge/b1x5v2/spl.c b/board/ge/b1x5v2/spl.c index 2e6f905219fe..52c80f792d3c 100644 --- a/board/ge/b1x5v2/spl.c +++ b/board/ge/b1x5v2/spl.c @@ -436,7 +436,7 @@ static int get_boardmem_size(struct spi_flash *spi) return 1024; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index e07295c7b5c0..d740f5ddab05 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -127,7 +127,7 @@ static int is_highbank(void) return (midr & 0xfff0) == 0xc090; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); if (is_highbank()) diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index e89ff1a43deb..d8212cd58d1b 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -485,7 +485,7 @@ int dram_init_banksize(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { writel(0x48698284, &ao_sc->stat0); wfi(); diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index db485db10a95..cca3cc1aaf1c 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -184,7 +184,7 @@ int board_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index 371c3c33fc88..41522d4212d8 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -59,7 +59,7 @@ int checkboard(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 4b406042180c..66682030c507 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -365,7 +365,7 @@ int board_eth_init(struct bd_info *bis) return ret; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { /* Soft Power On Reset */ writel((1 << 31), RESCNT2); diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c index 23959c255731..e798ab868775 100644 --- a/board/liebherr/display5/spl.c +++ b/board/liebherr/display5/spl.c @@ -375,7 +375,7 @@ void board_boot_order(u32 *spl_boot_list) #endif }
-void reset_cpu(ulong addr) {} +void reset_cpu(void) {}
#ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index b80688ae864c..771fa133dfbc 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -41,7 +41,7 @@ int board_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct arm_smccc_res res;
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index 4d1dbd696dcf..3f36efbea083 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -202,7 +202,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index c1ade5ce43a6..651c7c07320a 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -126,7 +126,7 @@ int board_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { psci_system_reset(); } diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 279ed4872165..b43946a77fbd 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -110,7 +110,7 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev; const u8 pmic_bus = 7; diff --git a/board/renesas/alt/alt_spl.c b/board/renesas/alt/alt_spl.c index 2de236fc2989..cdaa04e4f4ca 100644 --- a/board/renesas/alt/alt_spl.c +++ b/board/renesas/alt/alt_spl.c @@ -408,6 +408,6 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_NONE; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index 2450fca7a58b..0c8b2f64aa39 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -359,7 +359,7 @@ int dram_init_banksize(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev; const u8 pmic_bus = 6; diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c index 8054511d9d6c..1058f32bf792 100644 --- a/board/renesas/condor/condor.c +++ b/board/renesas/condor/condor.c @@ -33,7 +33,7 @@ int board_init(void) #define RST_CA57_CODE 0xA5A5000F #define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr) +void reset_cpu(void) { unsigned long midr, cputype;
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 9993f5bbe321..4a86a83056c6 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -74,7 +74,7 @@ int board_init(void) #define RST_CA53RESCNT (RST_BASE + 0x44) #define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr) +void reset_cpu(void) { writel(RST_CA53_CODE, RST_CA53RESCNT); } diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c index 6228f22e0103..157ee9d1025b 100644 --- a/board/renesas/eagle/eagle.c +++ b/board/renesas/eagle/eagle.c @@ -77,7 +77,7 @@ int board_init(void) #define RST_CA57_CODE 0xA5A5000F #define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr) +void reset_cpu(void) { unsigned long midr, cputype;
diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c index c8d180566d43..e433792da196 100644 --- a/board/renesas/ebisu/ebisu.c +++ b/board/renesas/ebisu/ebisu.c @@ -41,7 +41,7 @@ int board_init(void) #define RST_CA53RESCNT (RST_BASE + 0x44) #define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr) +void reset_cpu(void) { writel(RST_CA53_CODE, RST_CA53RESCNT); } diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index c6a93c25e6d2..5ff2950c368e 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -116,7 +116,7 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev; const u8 pmic_bus = 6; diff --git a/board/renesas/gose/gose_spl.c b/board/renesas/gose/gose_spl.c index 624ba5db04e5..c0bf72044394 100644 --- a/board/renesas/gose/gose_spl.c +++ b/board/renesas/gose/gose_spl.c @@ -405,6 +405,6 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_NONE; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index b92e01ca9847..49af58d7764d 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -39,7 +39,7 @@ int dram_init_banksize(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ readb(RZA1_WDT_BASE + WRCSR); diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 1b3acc8fd1f1..5af09ce9f18a 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -118,7 +118,7 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev; const u8 pmic_bus = 6; diff --git a/board/renesas/koelsch/koelsch_spl.c b/board/renesas/koelsch/koelsch_spl.c index 449bbfa7b81a..b377f7071580 100644 --- a/board/renesas/koelsch/koelsch_spl.c +++ b/board/renesas/koelsch/koelsch_spl.c @@ -407,6 +407,6 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_NONE; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 36a35a9a9cfb..7ac6c5adb145 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -127,7 +127,7 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev; const u8 pmic_bus = 2; diff --git a/board/renesas/lager/lager_spl.c b/board/renesas/lager/lager_spl.c index 1ca857c2c3d8..d3d397e8f0a5 100644 --- a/board/renesas/lager/lager_spl.c +++ b/board/renesas/lager/lager_spl.c @@ -393,6 +393,6 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_NONE; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index 793e02cb440a..f0ad5ae38cab 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -116,7 +116,7 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev; const u8 pmic_bus = 6; diff --git a/board/renesas/porter/porter_spl.c b/board/renesas/porter/porter_spl.c index f10c6cffc2b8..8595770c3648 100644 --- a/board/renesas/porter/porter_spl.c +++ b/board/renesas/porter/porter_spl.c @@ -488,6 +488,6 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_NONE; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/renesas/rcar-common/gen3-spl.c b/board/renesas/rcar-common/gen3-spl.c index fd6e5054a6d1..b02a946a21dc 100644 --- a/board/renesas/rcar-common/gen3-spl.c +++ b/board/renesas/rcar-common/gen3-spl.c @@ -55,6 +55,6 @@ void s_init(void) { }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index c78c2a42b02a..ac29a0e03b5f 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -75,7 +75,7 @@ int board_init(void) #define RST_RSTOUTCR (RST_BASE + 0x58) #define RST_CODE 0xA5A5000F
-void reset_cpu(ulong addr) +void reset_cpu(void) { #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 171d06f3175c..b942a694a114 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -111,7 +111,7 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev; const u8 pmic_bus = 1; diff --git a/board/renesas/silk/silk_spl.c b/board/renesas/silk/silk_spl.c index f10f84a3cce0..afb9f85ffc28 100644 --- a/board/renesas/silk/silk_spl.c +++ b/board/renesas/silk/silk_spl.c @@ -422,6 +422,6 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_NONE; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/renesas/stout/cpld.c b/board/renesas/stout/cpld.c index b56ed1703f5f..ac8048c81c50 100644 --- a/board/renesas/stout/cpld.c +++ b/board/renesas/stout/cpld.c @@ -163,7 +163,7 @@ U_BOOT_CMD( "cpld write addr val\n" );
-void reset_cpu(ulong addr) +void reset_cpu(void) { cpld_write(CPLD_ADDR_RESET, 1); } diff --git a/board/renesas/stout/stout_spl.c b/board/renesas/stout/stout_spl.c index 57c1fabaf3a8..c37c05571325 100644 --- a/board/renesas/stout/stout_spl.c +++ b/board/renesas/stout/stout_spl.c @@ -474,6 +474,6 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[2] = BOOT_DEVICE_NONE; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c index 56973a109087..dcbab8e4d21e 100644 --- a/board/siemens/capricorn/board.c +++ b/board/siemens/capricorn/board.c @@ -232,7 +232,7 @@ static int setup_fec(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c index 91fa94a638ef..3993efa85d18 100644 --- a/board/synopsys/emsdp/emsdp.c +++ b/board/synopsys/emsdp/emsdp.c @@ -97,7 +97,7 @@ int board_early_init_r(void) /* Bits in CREG_BOOT register */ #define CREG_BOOT_WP_BIT BIT(8)
-void reset_cpu(ulong addr) +void reset_cpu(void) { writel(1, CREG_IP_SW_RESET); while (1) diff --git a/board/synopsys/iot_devkit/iot_devkit.c b/board/synopsys/iot_devkit/iot_devkit.c index 497ea186d3a8..11a4f59c81c9 100644 --- a/board/synopsys/iot_devkit/iot_devkit.c +++ b/board/synopsys/iot_devkit/iot_devkit.c @@ -150,7 +150,7 @@ int mach_cpu_init(void)
#define IOTDK_RESET_SEQ 0x55AA6699
-void reset_cpu(ulong addr) +void reset_cpu(void) { writel(IOTDK_RESET_SEQ, RESET_REG); } diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index 380777954422..251f5a1b7d04 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -147,7 +147,7 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); }
-void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index bed0f21f44d3..df5f058577f3 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -127,7 +127,7 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); }
-void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index 2ed66261d286..32fc2d1ba3d0 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -116,7 +116,7 @@ int board_init(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* TODO */ } diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c index 739d2e51554d..10af413812cd 100644 --- a/board/toradex/apalis-imx8x/apalis-imx8x.c +++ b/board/toradex/apalis-imx8x/apalis-imx8x.c @@ -126,7 +126,7 @@ int board_init(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* TODO */ } diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 3961c4df9e24..4106cc0bf9d5 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -1138,7 +1138,7 @@ int board_fit_config_name_match(const char *name) } #endif
-void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index da081e30bec7..9f0b92f29a8c 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -128,7 +128,7 @@ int board_init(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { /* TODO */ } diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index a416b5e54b37..a71c67b04c03 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -1080,7 +1080,7 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); }
-void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 8afe1bfd5ebb..1e13b7ac4e82 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -236,7 +236,7 @@ int power_init_board(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct udevice *dev;
diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 4660f3fff20d..f529677931ff 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -170,7 +170,7 @@ int dram_init_banksize(void) /* * Board specific reset that is system reset. */ -void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 912c1143a8ad..7fe8fc4a5374 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -241,6 +241,6 @@ int dram_init(void) return 0; }
-void reset_cpu(ulong addr) +void reset_cpu(void) { } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 731285a73674..cd0338deebd8 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -434,7 +434,7 @@ int dram_init(void) } #endif
-void reset_cpu(ulong addr) +void reset_cpu(void) { }
diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c index ebfb25cab0a3..3fb964c37190 100644 --- a/cmd/tpm_test.c +++ b/cmd/tpm_test.c @@ -146,7 +146,7 @@ static int test_enable(struct udevice *dev)
#define reboot() do { \ printf("\trebooting...\n"); \ - reset_cpu(0); \ + reset_cpu(); \ } while (0)
static int test_fast_enable(struct udevice *dev) diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index 3f5414ed1f8a..69c4ed5abc5a 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -108,7 +108,7 @@ void sysreset_walk_halt(enum sysreset_t type) /** * reset_cpu() - calls sysreset_walk(SYSRESET_WARM) */ -void reset_cpu(ulong addr) +void reset_cpu(void) { sysreset_walk_halt(SYSRESET_WARM); } diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index b90c2daecee6..80ad9dfaa02c 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -44,7 +44,7 @@ static void imx_watchdog_expire_now(struct watchdog_regs *wdog, bool ext_reset)
#if !defined(CONFIG_IMX_WATCHDOG) || \ (defined(CONFIG_IMX_WATCHDOG) && !CONFIG_IS_ENABLED(WDT)) -void __attribute__((weak)) reset_cpu(ulong addr) +void __attribute__((weak)) reset_cpu(void) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 7533fc612c79..6f63b11b9ff0 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -77,7 +77,7 @@ void hw_watchdog_init(void) hw_watchdog_reset(); }
-void reset_cpu(ulong addr) +void reset_cpu(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
diff --git a/include/cpu_func.h b/include/cpu_func.h index 8aa825daa472..c3a66f04059d 100644 --- a/include/cpu_func.h +++ b/include/cpu_func.h @@ -84,6 +84,6 @@ enum { */ int cleanup_before_linux_select(int flags);
-void reset_cpu(ulong addr); -; +void reset_cpu(void); + #endif diff --git a/include/sysreset.h b/include/sysreset.h index 61295e3fcbb7..0b3aa0ac5e38 100644 --- a/include/sysreset.h +++ b/include/sysreset.h @@ -114,6 +114,6 @@ void sysreset_walk_halt(enum sysreset_t type); /** * reset_cpu() - calls sysreset_walk(SYSRESET_WARM) */ -void reset_cpu(ulong addr); +void reset_cpu(void);
#endif
On Tue, 15 Dec 2020 at 08:48, Harald Seiler hws@denx.de wrote:
Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead.
This transformation was done with the following coccinelle patch:
@@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... }Signed-off-by: Harald Seiler hws@denx.de
arch/arc/lib/reset.c | 4 ++-- arch/arm/cpu/arm920t/ep93xx/cpu.c | 2 +- arch/arm/cpu/arm920t/imx/timer.c | 2 +- arch/arm/cpu/arm926ejs/armada100/timer.c | 2 +- arch/arm/cpu/arm926ejs/mx25/reset.c | 2 +- arch/arm/cpu/arm926ejs/mx27/reset.c | 2 +- arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++-- arch/arm/cpu/arm926ejs/spear/reset.c | 2 +- arch/arm/cpu/arm946es/cpu.c | 2 +- arch/arm/cpu/armv7/bcm281xx/reset.c | 2 +- arch/arm/cpu/armv7/bcmcygnus/reset.c | 2 +- arch/arm/cpu/armv7/bcmnsp/reset.c | 2 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/s5p4418/cpu.c | 2 +- arch/arm/cpu/armv7/stv0991/reset.c | 2 +- arch/arm/cpu/armv7m/cpu.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++-- arch/arm/cpu/armv8/s32v234/generic.c | 2 +- arch/arm/cpu/pxa/pxa2xx.c | 4 ++-- arch/arm/cpu/sa1100/cpu.c | 2 +- arch/arm/lib/interrupts.c | 2 +- arch/arm/lib/interrupts_m.c | 2 +- arch/arm/lib/reset.c | 2 +- arch/arm/mach-at91/arm920t/reset.c | 2 +- arch/arm/mach-at91/arm926ejs/reset.c | 2 +- arch/arm/mach-at91/armv7/reset.c | 2 +- arch/arm/mach-bcm283x/reset.c | 2 +- arch/arm/mach-davinci/reset.c | 2 +- arch/arm/mach-exynos/soc.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/mx7ulp/soc.c | 2 +- arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-keystone/ddr3.c | 4 ++-- arch/arm/mach-keystone/init.c | 2 +- arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-lpc32xx/cpu.c | 2 +- arch/arm/mach-mediatek/mt7622/init.c | 2 +- arch/arm/mach-mediatek/mt8512/init.c | 2 +- arch/arm/mach-mediatek/mt8516/init.c | 2 +- arch/arm/mach-mediatek/mt8518/init.c | 2 +- arch/arm/mach-meson/board-common.c | 4 ++-- arch/arm/mach-mvebu/armada3700/cpu.c | 2 +- arch/arm/mach-mvebu/armada8k/cpu.c | 2 +- arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-octeontx/cpu.c | 2 +- arch/arm/mach-octeontx2/cpu.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- arch/arm/mach-omap2/reset.c | 2 +- arch/arm/mach-orion5x/cpu.c | 2 +- arch/arm/mach-owl/soc.c | 2 +- arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +- arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-tegra/cmd_enterrcm.c | 2 +- arch/arm/mach-tegra/pmc.c | 2 +- arch/arm/mach-uniphier/arm32/psci.c | 2 +- arch/arm/mach-uniphier/reset.c | 2 +- arch/arm/mach-zynq/cpu.c | 2 +- arch/arm/mach-zynqmp-r5/cpu.c | 2 +- arch/nds32/cpu/n1213/ag101/cpu.c | 2 +- arch/nds32/lib/interrupts.c | 2 +- arch/sandbox/cpu/sdl.c | 4 ++-- arch/sh/cpu/sh4/cpu.c | 2 +- arch/sh/cpu/sh4/watchdog.c | 2 +- arch/x86/cpu/ivybridge/cpu.c | 2 +- board/BuR/brppt2/board.c | 2 +- board/abilis/tb100/tb100.c | 2 +- board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 2 +- board/armltd/total_compute/total_compute.c | 2 +- board/armltd/vexpress/vexpress_common.c | 2 +- board/armltd/vexpress64/vexpress64.c | 2 +- board/atmark-techno/armadillo-800eva/armadillo-800eva.c | 2 +- board/beacon/beacon-rzg2m/beacon-rzg2m.c | 2 +- board/bosch/shc/board.c | 2 +- board/broadcom/bcmns2/northstar2.c | 2 +- board/broadcom/bcmns3/ns3.c | 2 +- board/broadcom/bcmstb/bcmstb.c | 2 +- board/cavium/thunderx/thunderx.c | 2 +- board/compulab/cm_t335/spl.c | 2 +- board/cortina/presidio-asic/presidio.c | 2 +- board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/freescale/mx6memcal/spl.c | 2 +- board/ge/b1x5v2/spl.c | 2 +- board/highbank/highbank.c | 2 +- board/hisilicon/hikey/hikey.c | 2 +- board/hisilicon/hikey960/hikey960.c | 2 +- board/hisilicon/poplar/poplar.c | 2 +- board/kmc/kzm9g/kzm9g.c | 2 +- board/liebherr/display5/spl.c | 2 +- board/phytium/durian/durian.c | 2 +- board/qualcomm/dragonboard410c/dragonboard410c.c | 2 +- board/qualcomm/dragonboard820c/dragonboard820c.c | 2 +- board/renesas/alt/alt.c | 2 +- board/renesas/alt/alt_spl.c | 2 +- board/renesas/blanche/blanche.c | 2 +- board/renesas/condor/condor.c | 2 +- board/renesas/draak/draak.c | 2 +- board/renesas/eagle/eagle.c | 2 +- board/renesas/ebisu/ebisu.c | 2 +- board/renesas/gose/gose.c | 2 +- board/renesas/gose/gose_spl.c | 2 +- board/renesas/grpeach/grpeach.c | 2 +- board/renesas/koelsch/koelsch.c | 2 +- board/renesas/koelsch/koelsch_spl.c | 2 +- board/renesas/lager/lager.c | 2 +- board/renesas/lager/lager_spl.c | 2 +- board/renesas/porter/porter.c | 2 +- board/renesas/porter/porter_spl.c | 2 +- board/renesas/rcar-common/gen3-spl.c | 2 +- board/renesas/salvator-x/salvator-x.c | 2 +- board/renesas/silk/silk.c | 2 +- board/renesas/silk/silk_spl.c | 2 +- board/renesas/stout/cpld.c | 2 +- board/renesas/stout/stout_spl.c | 2 +- board/siemens/capricorn/board.c | 2 +- board/synopsys/emsdp/emsdp.c | 2 +- board/synopsys/iot_devkit/iot_devkit.c | 2 +- board/technexion/pico-imx6ul/spl.c | 2 +- board/technexion/pico-imx7d/spl.c | 2 +- board/toradex/apalis-imx8/apalis-imx8.c | 2 +- board/toradex/apalis-imx8x/apalis-imx8x.c | 2 +- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri-imx8x/colibri-imx8x.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/toradex/colibri_imx7/colibri_imx7.c | 2 +- board/xen/xenguest_arm64/xenguest_arm64.c | 2 +- board/xilinx/versal/board.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- cmd/tpm_test.c | 2 +- drivers/sysreset/sysreset-uclass.c | 2 +- drivers/watchdog/imx_watchdog.c | 2 +- drivers/watchdog/ulp_wdog.c | 2 +- include/cpu_func.h | 4 ++-- include/sysreset.h | 2 +- 134 files changed, 142 insertions(+), 142 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Tue, Dec 15, 2020 at 04:47:52PM +0100, Harald Seiler wrote:
Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead.
This transformation was done with the following coccinelle patch:
@@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... }Signed-off-by: Harald Seiler hws@denx.de Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot/next, thanks!
Hi,
On Tue, 2020-12-15 at 16:47 +0100, Harald Seiler wrote:
Hi,
this is something I had on my mind for a longer time but never got around to actually do until now ... A while back, while working on the patchset that led to commit c5635a032a4b ("ARM: imx8m: Don't use the addr parameter of reset_cpu()"), I noticed that the `addr` parameter of reset_cpu() seems to not actually hold any meaningful value. All call-sites in the current tree just pass 0 and the vast majority of reset_cpu() implementations actually ignore the parameter.
I dug a bit deeper to find out why this `addr` parameter exists in the first place and found out that it's mostly a legacy artifact:
Historically, the reset_cpu() function had this `addr` parameter to pass an address of a reset vector location, where the CPU should reset to.
The times where this was used are long gone and the only trace it left is some (dead) code for the NDS32 arch. The `addr` parameter lived on and it looks like it was sometimes used as a way to indicate different types of resets (e.g. COLD vs WARM).
Today, however, reset_cpu() is only ever called with `addr` 0 in the mainline tree and as such, any code that gives a meaning to the `addr` value will only ever follow the `addr == 0` branch. This is probably not what the authors intended and as it seems quite unobvious to me, I think the best way forward is to remove the `addr` parameter entirely.
This removes any ambiguity in the "contract" of reset_cpu() and thus hopefully prevents more code being added which wrongly assumes that the parameter can be used for any meaningful purpose. Instead, code which wants to properly support multiple reset types needs to be implemented as a sysreset driver.
I did this API change via a coccinelle patch, see "reset: Remove addr parameter from reset_cpu()" for details. I also ran buildman for all boards I could, to verify that everything still compiles. One notable exception is NDS32 because I couldn't get the compiler to work there ...
I wanted to ask what the current state regarding this patchset is. Is there anything I should still take care of?
I am a bit worried about it going stale if it stays lying around for too long and new call-sites get introduced. So far everything is still fine though, I just applied the patchset to v2021.04-rc3 and ran a worldbuild - I do not see any builds regressing.
Hi Harald,
On Tue, 2 Mar 2021 at 06:35, Harald Seiler hws@denx.de wrote:
Hi,
On Tue, 2020-12-15 at 16:47 +0100, Harald Seiler wrote:
Hi,
this is something I had on my mind for a longer time but never got around to actually do until now ... A while back, while working on the patchset that led to commit c5635a032a4b ("ARM: imx8m: Don't use the addr parameter of reset_cpu()"), I noticed that the `addr` parameter of reset_cpu() seems to not actually hold any meaningful value. All call-sites in the current tree just pass 0 and the vast majority of reset_cpu() implementations actually ignore the parameter.
I dug a bit deeper to find out why this `addr` parameter exists in the first place and found out that it's mostly a legacy artifact:
Historically, the reset_cpu() function had this `addr` parameter to pass an address of a reset vector location, where the CPU should reset to.The times where this was used are long gone and the only trace it left is some (dead) code for the NDS32 arch. The `addr` parameter lived on and it looks like it was sometimes used as a way to indicate different types of resets (e.g. COLD vs WARM).
Today, however, reset_cpu() is only ever called with `addr` 0 in the mainline tree and as such, any code that gives a meaning to the `addr` value will only ever follow the `addr == 0` branch. This is probably not what the authors intended and as it seems quite unobvious to me, I think the best way forward is to remove the `addr` parameter entirely.
This removes any ambiguity in the "contract" of reset_cpu() and thus hopefully prevents more code being added which wrongly assumes that the parameter can be used for any meaningful purpose. Instead, code which wants to properly support multiple reset types needs to be implemented as a sysreset driver.
I did this API change via a coccinelle patch, see "reset: Remove addr parameter from reset_cpu()" for details. I also ran buildman for all boards I could, to verify that everything still compiles. One notable exception is NDS32 because I couldn't get the compiler to work there ...
I wanted to ask what the current state regarding this patchset is. Is there anything I should still take care of?
I am a bit worried about it going stale if it stays lying around for too long and new call-sites get introduced. So far everything is still fine though, I just applied the patchset to v2021.04-rc3 and ran a worldbuild
- I do not see any builds regressing.
This series seems like a good idea to me.
Regards, Simon
participants (4)
-
Harald Seiler -
Simon Glass -
Sylvain Lemieux -
Tom Rini