[U-Boot] [PATCH 1/3] ARM: tegra: fix USB ULPI PHY reset signal inversion confusion
From: Stephen Warren swarren@nvidia.com
USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot.
This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW.
Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/dts/tegra20-colibri.dts | 3 ++- arch/arm/dts/tegra20-harmony.dts | 3 ++- drivers/usb/host/ehci-tegra.c | 13 +++++++++++-- 3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index a291d93c7d01..777f63e5bdb6 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -39,7 +39,8 @@ usb@c5004000 { statuc = "okay"; /* VBUS_LAN */ - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; };
diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index cace74339483..5aec150b5e61 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -626,7 +626,8 @@
usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; };
usb-phy@c5004000 { diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 31d54ab285bf..c10597861873 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -600,9 +600,18 @@ static int init_ulpi_usb_controller(struct fdt_usb *config,
/* reset ULPI phy */ if (dm_gpio_is_valid(&config->phy_reset_gpio)) { - dm_gpio_set_value(&config->phy_reset_gpio, 0); - mdelay(5); + /* + * This GPIO is typically active-low, and marked as such in + * device tree. dm_gpio_set_value() takes this into account + * and inverts the value we pass here if required. In other + * words, this first call logically asserts the reset signal, + * which typically results in driving the physical GPIO low, + * and the second call logically de-asserts the reset signal, + * which typically results in driver the GPIO high. + */ dm_gpio_set_value(&config->phy_reset_gpio, 1); + mdelay(5); + dm_gpio_set_value(&config->phy_reset_gpio, 0); }
/* Reset the usb controller */
From: Stephen Warren swarren@nvidia.com
Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2.
USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000'
This didn't affect USB operation in any way though.
Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later.
This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that.
Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/dts/tegra20-harmony.dts | 3 ++- arch/arm/dts/tegra20-seaboard.dts | 5 +++-- arch/arm/dts/tegra20-trimslice.dts | 3 +-- arch/arm/dts/tegra20-ventana.dts | 4 +++- 4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index 5aec150b5e61..dcbde7c2ed7e 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -15,8 +15,9 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd; - usb0 = "/usb@c5008000"; + usb0 = "/usb@c5000000"; usb1 = "/usb@c5004000"; + usb2 = "/usb@c5008000"; mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000200"; }; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 14210519a6c2..77f5bb51b027 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -9,8 +9,9 @@
aliases { /* This defines the order of our ports */ - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; + usb0 = "/usb@c5000000"; + usb1 = "/usb@c5004000"; + usb2 = "/usb@c5008000"; i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index be64e667cd5b..7fb7dd0b5815 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -11,8 +11,7 @@ };
aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; + usb0 = "/usb@c5000000"; mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000000"; spi0 = "/spi@7000c380"; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 371445622c1e..85cd1e39bda7 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -15,7 +15,9 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd; - usb0 = "/usb@c5008000"; + usb0 = "/usb@c5000000"; + usb1 = "/usb@c5004000"; + usb2 = "/usb@c5008000"; mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000400"; };
On 15 September 2016 at 12:19, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2.
USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000'
This didn't affect USB operation in any way though.
Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later.
This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that.
Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra20-harmony.dts | 3 ++- arch/arm/dts/tegra20-seaboard.dts | 5 +++-- arch/arm/dts/tegra20-trimslice.dts | 3 +-- arch/arm/dts/tegra20-ventana.dts | 4 +++- 4 files changed, 9 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Hi Stephen
Cool, it's all working again. You saved my day!
Tegra20 (Harmony) # usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (12 Mb/s, 94mA) | Broadcom BCM2046B1 | +-3 Human Interface (12 Mb/s, 2mA) | +-4 Human Interface (12 Mb/s, 2mA) 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 2mA) | +-3 Mass Storage (480 Mb/s, 500mA) | T1204020000702 | +-4 Vendor specific (480 Mb/s, 0mA) | SMSC LAN9514 12345678 | +-5 Mass Storage (480 Mb/s, 200mA) | Generic Mass Storage CAF6AFF4 | +-6 Mass Storage (480 Mb/s, 300mA) Kingston DataTraveler 3.0 001D0F1FEBFDBE51C741753F
Tegra20 (Ventana) # usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (12 Mb/s, 94mA) | Broadcom BCM2046B1 | +-3 Human Interface (12 Mb/s, 2mA) 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Mass Storage (480 Mb/s, 500mA) T1204020000702
More feedback below.
On Thu, 2016-09-15 at 18:19 +0000, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2.
USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000'
This didn't affect USB operation in any way though.
Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later.
This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that.
Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra20-harmony.dts | 3 ++- arch/arm/dts/tegra20-seaboard.dts | 5 +++-- arch/arm/dts/tegra20-trimslice.dts | 3 +-- arch/arm/dts/tegra20-ventana.dts | 4 +++- 4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20- harmony.dts index 5aec150b5e61..dcbde7c2ed7e 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -15,8 +15,9 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd;
usb0 = "/usb@c5008000";
usb0 = "/usb@c5000000";usb1 = "/usb@c5004000";
usb2 = "/usb@c5008000";mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000200";
Aren't those called sdhci in mainline? Ah, I guess I missed that one:
http://git.denx.de/?p=u-boot/u-boot-tegra.git;a=commitdiff;h=dacb893017 c20ebaaca2138b281c87c0d8977065
}; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 14210519a6c2..77f5bb51b027 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -9,8 +9,9 @@ aliases { /* This defines the order of our ports */
usb0 = "/usb@c5008000";usb1 = "/usb@c5000000";
usb0 = "/usb@c5000000";usb1 = "/usb@c5004000";usb2 = "/usb@c5008000";i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index be64e667cd5b..7fb7dd0b5815 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -11,8 +11,7 @@ }; aliases {
usb0 = "/usb@c5008000";usb1 = "/usb@c5000000";
usb0 = "/usb@c5000000";mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000000"; spi0 = "/spi@7000c380"; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20- ventana.dts index 371445622c1e..85cd1e39bda7 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -15,7 +15,9 @@ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uartd;
usb0 = "/usb@c5008000";
usb0 = "/usb@c5000000";usb1 = "/usb@c5004000";usb2 = "/usb@c5008000";mmc0 = "/sdhci@c8000600"; mmc1 = "/sdhci@c8000400"; };
For the whole series you may add:
Tested-by: Marcel Ziswiler marcel.ziswiler@toradex.com Tested-on: Harmony and Ventana
Cheers
Marcel
From: Stephen Warren swarren@nvidia.com
Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana.
Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig.
Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/dts/tegra20-seaboard.dts | 2 +- board/nvidia/seaboard/seaboard.c | 8 +++++++- configs/seaboard_defconfig | 2 ++ configs/ventana_defconfig | 2 ++ 4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 77f5bb51b027..341c7f35836a 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -784,7 +784,7 @@ };
usb@c5004000 { - status = "disabled"; + status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; }; diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index fc9c1c9b34dc..4e01deb02fb0 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -44,6 +44,12 @@ void pin_mux_mmc(void)
void pin_mux_usb(void) { - /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */ + /* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */ pinmux_tristate_disable(PMUX_PINGRP_SLXK); + /* For USB1's ULPI signals */ + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); + /* USB1 PHY reset GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_UAC); } diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 12cc9b62e7fe..806caca1226a 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -35,6 +35,8 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 8288c860067b..56e7ba367d60 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -34,6 +34,8 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y
On 15 September 2016 at 12:19, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana.
Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig.
Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra20-seaboard.dts | 2 +- board/nvidia/seaboard/seaboard.c | 8 +++++++- configs/seaboard_defconfig | 2 ++ configs/ventana_defconfig | 2 ++ 4 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On 15 September 2016 at 12:19, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot.
This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW.
Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Signed-off-by: Stephen Warren swarren@nvidia.com
arch/arm/dts/tegra20-colibri.dts | 3 ++- arch/arm/dts/tegra20-harmony.dts | 3 ++- drivers/usb/host/ehci-tegra.c | 13 +++++++++++-- 3 files changed, 15 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
participants (3)
-
Marcel Ziswiler -
Simon Glass -
Stephen Warren