[U-Boot] [PATCH v2 00/18] x86: acpi: Support installation of Ubuntu/Windows and boot Windows
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. But till now this is broken. The installation either hangs forever or just crashes.
This series fixed a bunch of issues that affect the installation of Ubuntu and Windows, and booting Windows.
Testing was performed on MinnowMax by: - Install Ubuntu 14.04 and boot - Install Windows 8.1 and boot - Install Windows 10 and boot
This series is available at u-boot-x86/acpi2-working.
Changes in v2: - New patch to remove the unnecessary checksum calculation of DSDT - New patch to remove header length check when writing tables - New patch to enable SeaBIOS on all boards - New patch to add GPIO ASL description
Bin Meng (18): x86: minnowmax: Adjust U-Boot environment address in SPI flash x86: Call board_final_cleanup() in last_stage_init() x86: Fix up PIRQ routing table checksum earlier x86: Compile coreboot_table.c only for SeaBIOS x86: Prepare configuration tables in dedicated high memory region x86: Unify reserve_arch() for all x86 boards x86: Reserve configuration tables in high memory x86: Use high_table_malloc() for tables passing to SeaBIOS x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPM x86: acpi: Remove the unnecessary checksum calculation of DSDT x86: acpi: Remove header length check when writing tables x86: doc: Update information about IGD with SeaBIOS x86: baytrail: Enable SeaBIOS on all boards x86: doc: Mention Ubuntu/Windows installation and boot support acpi: Quieten IASL output when 'make -s' is used x86: baytrail: Add internal UART ASL description x86: baytrail: Add GPIO ASL description x86: doc: Add porting hints for ACPI with Windows
arch/x86/Kconfig | 14 ++++ arch/x86/cpu/baytrail/valleyview.c | 8 -- arch/x86/cpu/broadwell/sdram.c | 5 -- arch/x86/cpu/coreboot/coreboot.c | 20 +++-- arch/x86/cpu/cpu.c | 27 ++++++ arch/x86/cpu/irq.c | 4 + arch/x86/cpu/ivybridge/sdram.c | 5 -- arch/x86/cpu/quark/quark.c | 9 -- arch/x86/include/asm/acpi_table.h | 3 + arch/x86/include/asm/arch-baytrail/acpi/gpio.asl | 95 ++++++++++++++++++++++ .../include/asm/arch-baytrail/acpi/irqlinks.asl | 4 + arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 60 ++++++++++++++ .../include/asm/arch-baytrail/acpi/platform.asl | 3 + arch/x86/include/asm/coreboot_tables.h | 19 +++++ arch/x86/include/asm/global_data.h | 4 + arch/x86/lib/Makefile | 2 +- arch/x86/lib/acpi_table.c | 58 ++++++++----- arch/x86/lib/bootm.c | 9 -- arch/x86/lib/coreboot_table.c | 31 +++++++ arch/x86/lib/pirq_routing.c | 4 - arch/x86/lib/tables.c | 4 +- configs/bayleybay_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/minnowmax_defconfig | 1 + doc/README.x86 | 44 ++++++++-- include/configs/minnowmax.h | 2 +- scripts/Makefile.lib | 2 +- 27 files changed, 357 insertions(+), 82 deletions(-) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
Currently U-Boot environment address is at offset 0x7fe00 of a 8MB SPI flash. When creating a partial u-boot.rom image without flash descriptor and ME firmware, U-Boot actually occupies the last 1MB of the flash, and reprograming U-Boot causes previous environment settings get lost which is not convenient during testing.
Adjust the environment address to 0x6ef000 instead (before the MRC cache data region in the flash).
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Stefan Roese sr@denx.de ---
Changes in v2: None
doc/README.x86 | 2 +- include/configs/minnowmax.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/README.x86 b/doc/README.x86 index ce806ee..25cb218 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -304,12 +304,12 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 <spare> +6ef000 Environment CONFIG_ENV_OFFSET 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE 790000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 <spare> (depends on size of fsp.bin) -7fe000 Environment CONFIG_ENV_OFFSET 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
Overall ROM image size is controlled by CONFIG_ROM_SIZE. diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 674d1f6..95ad128 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -40,6 +40,6 @@ #define CONFIG_X86EMU_RAW_IO
#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x007fe000 +#define CONFIG_ENV_OFFSET 0x006ef000
#endif /* __CONFIG_H */
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
Currently U-Boot environment address is at offset 0x7fe00 of a 8MB SPI flash. When creating a partial u-boot.rom image without flash descriptor and ME firmware, U-Boot actually occupies the last 1MB of the flash, and reprograming U-Boot causes previous environment settings get lost which is not convenient during testing.
Adjust the environment address to 0x6ef000 instead (before the MRC cache data region in the flash).
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Stefan Roese sr@denx.de
Changes in v2: None
doc/README.x86 | 2 +- include/configs/minnowmax.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
Currently U-Boot environment address is at offset 0x7fe00 of a 8MB SPI flash. When creating a partial u-boot.rom image without flash descriptor and ME firmware, U-Boot actually occupies the last 1MB of the flash, and reprograming U-Boot causes previous environment settings get lost which is not convenient during testing.
Adjust the environment address to 0x6ef000 instead (before the MRC cache data region in the flash).
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Stefan Roese sr@denx.de
Changes in v2: None
doc/README.x86 | 2 +- include/configs/minnowmax.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows.
Move the call to last_stage_init() instead.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 20 +++++++++++--------- arch/x86/cpu/cpu.c | 10 ++++++++++ arch/x86/lib/bootm.c | 9 --------- 3 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 845f86a..1b04203 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -39,15 +39,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); }
-int last_stage_init(void) -{ - if (gd->flags & GD_FLG_COLD_BOOT) - timestamp_add_to_bootstage(); - - return 0; -} - -void board_final_cleanup(void) +static void board_final_cleanup(void) { /* * Un-cache the ROM so the kernel has one @@ -79,6 +71,16 @@ void board_final_cleanup(void) } }
+int last_stage_init(void) +{ + if (gd->flags & GD_FLG_COLD_BOOT) + timestamp_add_to_bootstage(); + + board_final_cleanup(); + + return 0; +} + int misc_init_r(void) { return 0; diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 233a6c8..1482153 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -661,10 +661,20 @@ void show_boot_progress(int val) }
#ifndef CONFIG_SYS_COREBOOT +/* + * Implement a weak default function for boards that optionally + * need to clean up the system before jumping to the kernel. + */ +__weak void board_final_cleanup(void) +{ +} + int last_stage_init(void) { write_tables();
+ board_final_cleanup(); + return 0; } #endif diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 783be69..7cf9de4 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -26,14 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define COMMAND_LINE_OFFSET 0x9000
-/* - * Implement a weak default function for boards that optionally - * need to clean up the system before jumping to the kernel. - */ -__weak void board_final_cleanup(void) -{ -} - void bootm_announce_and_cleanup(void) { printf("\nStarting kernel ...\n\n"); @@ -45,7 +37,6 @@ void bootm_announce_and_cleanup(void) #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); #endif - board_final_cleanup(); }
#if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows.
Move the call to last_stage_init() instead.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 20 +++++++++++--------- arch/x86/cpu/cpu.c | 10 ++++++++++ arch/x86/lib/bootm.c | 9 --------- 3 files changed, 21 insertions(+), 18 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows.
Move the call to last_stage_init() instead.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/coreboot/coreboot.c | 20 +++++++++++--------- arch/x86/cpu/cpu.c | 10 ++++++++++ arch/x86/lib/bootm.c | 9 --------- 3 files changed, 21 insertions(+), 18 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(), which is fine if we only write the configuration table once. But with the SeaBIOS case, when we write the table for the second time, the checksum will be fixed up to zero per the checksum algorithm, which is caused by the checksum field not being zero before fix up, since the checksum has already been calculated in the first run.
To fix this, move the checksum fixup to create_pirq_routing_table(), so that copy_pirq_routing_table() only does what its function name suggests: copy the table to somewhere else.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/irq.c | 4 ++++ arch/x86/lib/pirq_routing.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 86183b0..df3cd0a 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -13,6 +13,7 @@ #include <asm/irq.h> #include <asm/pci.h> #include <asm/pirq_routing.h> +#include <asm/tables.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -214,6 +215,9 @@ static int create_pirq_routing_table(struct udevice *dev)
rt->size = irq_entries * sizeof(struct irq_info) + 32;
+ /* Fix up the table checksum */ + rt->checksum = table_compute_checksum(rt, rt->size); + pirq_routing_table = rt;
return 0; diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index 3cc6adb..a93d355 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -10,7 +10,6 @@ #include <pci.h> #include <asm/pci.h> #include <asm/pirq_routing.h> -#include <asm/tables.h>
static bool irq_already_routed[16];
@@ -111,9 +110,6 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) { struct irq_routing_table *rom_rt;
- /* Fix up the table checksum */ - rt->checksum = table_compute_checksum(rt, rt->size); - /* Align the table to be 16 byte aligned */ addr = ALIGN(addr, 16);
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(), which is fine if we only write the configuration table once. But with the SeaBIOS case, when we write the table for the second time, the checksum will be fixed up to zero per the checksum algorithm, which is caused by the checksum field not being zero before fix up, since the checksum has already been calculated in the first run.
To fix this, move the checksum fixup to create_pirq_routing_table(), so that copy_pirq_routing_table() only does what its function name suggests: copy the table to somewhere else.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/irq.c | 4 ++++ arch/x86/lib/pirq_routing.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(), which is fine if we only write the configuration table once. But with the SeaBIOS case, when we write the table for the second time, the checksum will be fixed up to zero per the checksum algorithm, which is caused by the checksum field not being zero before fix up, since the checksum has already been calculated in the first run.
To fix this, move the checksum fixup to create_pirq_routing_table(), so that copy_pirq_routing_table() only does what its function name suggests: copy the table to somewhere else.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/irq.c | 4 ++++ arch/x86/lib/pirq_routing.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
coreboot_table.c only needs to be built when SeaBIOS is used.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index dc90df2..73e3e52 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -10,7 +10,7 @@ obj-y += bios_asm.o obj-y += bios_interrupts.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o -obj-y += coreboot_table.o +obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-$(CONFIG_EFI) += efi/ obj-y += e820.o obj-y += gcc.o
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
coreboot_table.c only needs to be built when SeaBIOS is used.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
coreboot_table.c only needs to be built when SeaBIOS is used.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration tables via normal malloc(). To simplify, use a dedicated memory region which is reserved on the stack before relocation for this purpose. Add functions for reserve and malloc.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/include/asm/coreboot_tables.h | 19 +++++++++++++++++++ arch/x86/include/asm/global_data.h | 4 ++++ arch/x86/lib/coreboot_table.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 4ef27dc..d304e29 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -536,6 +536,20 @@ config SEABIOS
Check http://www.seabios.org/SeaBIOS for details.
+config HIGH_TABLE_SIZE + hex "Size of configuration tables which reside in high memory" + default 0x10000 + depends on SEABIOS + help + SeaBIOS itself resides in E seg and F seg, where U-Boot puts all + configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot + puts a copy of configuration tables in high memory region which + is reserved on the stack before relocation. The region size is + determined by this option. + + Increse it if the default size does not fit the board's needs. + This is most likely due to a large ACPI DSDT table is used. + source "arch/x86/lib/efi/Kconfig"
endmenu diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 15ccf9b..e036f74 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -295,6 +295,25 @@ struct cbmem_entry { #define CBMEM_ID_NONE 0x00000000
/** + * high_table_reserve() - reserve configuration table in high memory + * + * This reserves configuration table in high memory. + * + * @return: always 0 + */ +int high_table_reserve(void); + +/** + * high_table_malloc() - allocate configuration table in high memory + * + * This allocates configuration table in high memory. + * + * @bytes: size of configuration table to be allocated + * @return: pointer to configuration table in high memory + */ +void *high_table_malloc(size_t bytes); + +/** * write_coreboot_table() - write coreboot table * * This writes coreboot table at a given address. diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 3bc2ac2..7434f77 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -93,6 +93,10 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; ulong table; /* Table pointer from previous loader */ +#ifdef CONFIG_SEABIOS + u32 high_table_ptr; + u32 high_table_limit; +#endif };
#endif diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index cb45a79..ceab3cf 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -9,6 +9,37 @@ #include <asm/coreboot_tables.h> #include <asm/e820.h>
+DECLARE_GLOBAL_DATA_PTR; + +int high_table_reserve(void) +{ + /* adjust stack pointer to reserve space for configuration tables */ + gd->arch.high_table_limit = gd->start_addr_sp; + gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE; + gd->arch.high_table_ptr = gd->start_addr_sp; + + /* clear the memory */ + memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE); + + gd->start_addr_sp &= ~0xf; + + return 0; +} + +void *high_table_malloc(size_t bytes) +{ + u32 new_ptr; + void *ptr; + + new_ptr = gd->arch.high_table_ptr + bytes; + if (new_ptr >= gd->arch.high_table_limit) + return NULL; + ptr = (void *)gd->arch.high_table_ptr; + gd->arch.high_table_ptr = new_ptr; + + return ptr; +} + /** * cb_table_init() - initialize a coreboot table header *
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration tables via normal malloc(). To simplify, use a dedicated memory region which is reserved on the stack before relocation for this purpose. Add functions for reserve and malloc.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/include/asm/coreboot_tables.h | 19 +++++++++++++++++++ arch/x86/include/asm/global_data.h | 4 ++++ arch/x86/lib/coreboot_table.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:44, Bin Meng bmeng.cn@gmail.com wrote:
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration tables via normal malloc(). To simplify, use a dedicated memory region which is reserved on the stack before relocation for this purpose. Add functions for reserve and malloc.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/Kconfig | 14 ++++++++++++++ arch/x86/include/asm/coreboot_tables.h | 19 +++++++++++++++++++ arch/x86/include/asm/global_data.h | 4 ++++ arch/x86/lib/coreboot_table.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Instead of asking each platform to provide reserve_arch(), supply it in arch/x86/cpu/cpu.c in a unified way.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/baytrail/valleyview.c | 8 -------- arch/x86/cpu/broadwell/sdram.c | 5 ----- arch/x86/cpu/cpu.c | 12 ++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 5 ----- arch/x86/cpu/quark/quark.c | 9 --------- 5 files changed, 12 insertions(+), 27 deletions(-)
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 25382f9..b31f24e 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -53,14 +53,6 @@ int arch_misc_init(void) return 0; }
-int reserve_arch(void) -{ -#ifdef CONFIG_ENABLE_MRC_CACHE - return mrccache_reserve(); -#else - return 0; -#endif -} #endif
void reset_cpu(ulong addr) diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c index 4bf5d15..e7befde 100644 --- a/arch/x86/cpu/broadwell/sdram.c +++ b/arch/x86/cpu/broadwell/sdram.c @@ -190,11 +190,6 @@ static int prepare_mrc_cache(struct pei_data *pei_data) return 0; }
-int reserve_arch(void) -{ - return mrccache_reserve(); -} - int dram_init(void) { struct pei_data _pei_data __aligned(8); diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 1482153..2e27d78 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -29,6 +29,7 @@ #include <asm/lapic.h> #include <asm/microcode.h> #include <asm/mp.h> +#include <asm/mrccache.h> #include <asm/msr.h> #include <asm/mtrr.h> #include <asm/post.h> @@ -751,3 +752,14 @@ int cpu_init_r(void)
return 0; } + +#ifndef CONFIG_EFI_STUB +int reserve_arch(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + return mrccache_reserve(); +#else + return 0; +#endif +} +#endif diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index e35e543..9d9f63d 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -201,11 +201,6 @@ static int recovery_mode_enabled(void) return false; }
-int reserve_arch(void) -{ - return mrccache_reserve(); -} - static int copy_spd(struct udevice *dev, struct pei_data *peid) { const void *data; diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index afb3463..cf3fe7f 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -360,12 +360,3 @@ void board_final_cleanup(void)
return; } - -int reserve_arch(void) -{ -#ifdef CONFIG_ENABLE_MRC_CACHE - return mrccache_reserve(); -#else - return 0; -#endif -}
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Instead of asking each platform to provide reserve_arch(), supply it in arch/x86/cpu/cpu.c in a unified way.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/baytrail/valleyview.c | 8 -------- arch/x86/cpu/broadwell/sdram.c | 5 ----- arch/x86/cpu/cpu.c | 12 ++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 5 ----- arch/x86/cpu/quark/quark.c | 9 --------- 5 files changed, 12 insertions(+), 27 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Instead of asking each platform to provide reserve_arch(), supply it in arch/x86/cpu/cpu.c in a unified way.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/baytrail/valleyview.c | 8 -------- arch/x86/cpu/broadwell/sdram.c | 5 ----- arch/x86/cpu/cpu.c | 12 ++++++++++++ arch/x86/cpu/ivybridge/sdram.c | 5 ----- arch/x86/cpu/quark/quark.c | 9 --------- 5 files changed, 12 insertions(+), 27 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
When SeaBIOS is on, reserve configuration tables in reserve_arch().
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/cpu/cpu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 2e27d78..e522ff3 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -25,6 +25,7 @@ #include <errno.h> #include <malloc.h> #include <asm/control_regs.h> +#include <asm/coreboot_tables.h> #include <asm/cpu.h> #include <asm/lapic.h> #include <asm/microcode.h> @@ -757,9 +758,13 @@ int cpu_init_r(void) int reserve_arch(void) { #ifdef CONFIG_ENABLE_MRC_CACHE - return mrccache_reserve(); -#else - return 0; + mrccache_reserve(); +#endif + +#ifdef CONFIG_SEABIOS + high_table_reserve(); #endif + + return 0; } #endif
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
When SeaBIOS is on, reserve configuration tables in reserve_arch().
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/cpu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
When SeaBIOS is on, reserve configuration tables in reserve_arch().
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/cpu/cpu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Now that we already reserved high memory for configuration tables, call high_table_malloc() to allocate tables from the region.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/lib/tables.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 1213a9c..f92111e 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -5,7 +5,6 @@ */
#include <common.h> -#include <malloc.h> #include <asm/sfi.h> #include <asm/mpspec.h> #include <asm/smbios.h> @@ -81,9 +80,8 @@ void write_tables(void)
#ifdef CONFIG_SEABIOS table_size = rom_table_end - rom_table_start; - high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size); + high_table = (u32)high_table_malloc(table_size); if (high_table) { - memset((void *)high_table, 0, table_size); table_write_funcs[i](high_table);
cfg_tables[i].start = high_table;
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Now that we already reserved high memory for configuration tables, call high_table_malloc() to allocate tables from the region.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/lib/tables.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Now that we already reserved high memory for configuration tables, call high_table_malloc() to allocate tables from the region.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/lib/tables.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Per ACPI spec, during ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit in the PM1_CNT register), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers.
However since U-Boot does not support SMI, we report all 3 fields in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following the spec who says: these fields are reserved and must be zero on system that does not support System Management mode.
U-Boot seems to behave in a correct way that the ACPI spec allows, at least Linux does not complain, but apparently Windows does not think so. During Windows bring up debugging, it is observed that even these 3 fields are zero, Windows are still trying to issue SMI with hardcoded SMI port address and commands, and expecting SCI_EN to be changed by the firmware. Eventually Windows gives us a BSOD (Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start.
To fix this, turn on the SCI_EN bit by ourselves. With this patch, now U-Boot can install and boot Windows 8.1/10 successfully with the help of SeaBIOS using legacy interface (non-UEFI mode).
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/x86/include/asm/acpi_table.h | 3 +++ arch/x86/lib/acpi_table.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+)
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index ff4802a..56aa282 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -296,6 +296,9 @@ struct acpi_mcfg_mmconfig { u8 reserved[4]; };
+/* PM1_CNT bit defines */ +#define PM1_CNT_SCI_EN (1 << 0) + /* These can be used by the target port */
void acpi_fill_header(struct acpi_table_header *header, char *signature); diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 989cf7d..a9fe243 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -12,6 +12,7 @@ #include <dm.h> #include <dm/uclass-internal.h> #include <asm/acpi_table.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/tables.h>
@@ -301,6 +302,25 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) header->checksum = table_compute_checksum((void *)mcfg, header->length); }
+static void enter_acpi_mode(int pm1_cnt) +{ + /* + * PM1_CNT register bit0 selects the power management event to be + * either an SCI or SMI interrupt. When this bit is set, then power + * management events will generate an SCI interrupt. When this bit + * is reset power management events will generate an SMI interrupt. + * + * Per ACPI spec, it is the responsibility of the hardware to set + * or reset this bit. OSPM always preserves this bit position. + * + * U-Boot does not support SMI. And we don't have plan to support + * anything running in SMM within U-Boot. To create a legacy-free + * system, and expose ourselves to OSPM as working under ACPI mode + * already, turn this bit on. + */ + outw(PM1_CNT_SCI_EN, pm1_cnt); +} + /* * QEMU's version of write_acpi_tables is defined in * arch/x86/cpu/qemu/fw_cfg.c @@ -400,5 +420,11 @@ u32 write_acpi_tables(u32 start)
debug("ACPI: done\n");
+ /* + * Other than waiting for OSPM to request us to switch to ACPI mode, + * do it by ourselves, since SMI will not be triggered. + */ + enter_acpi_mode(fadt->pm1a_cnt_blk); + return current; }
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Per ACPI spec, during ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit in the PM1_CNT register), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers.
However since U-Boot does not support SMI, we report all 3 fields in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following the spec who says: these fields are reserved and must be zero on system that does not support System Management mode.
U-Boot seems to behave in a correct way that the ACPI spec allows, at least Linux does not complain, but apparently Windows does not think so. During Windows bring up debugging, it is observed that even these 3 fields are zero, Windows are still trying to issue SMI with hardcoded SMI port address and commands, and expecting SCI_EN to be changed by the firmware. Eventually Windows gives us a BSOD (Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start.
To fix this, turn on the SCI_EN bit by ourselves. With this patch, now U-Boot can install and boot Windows 8.1/10 successfully with the help of SeaBIOS using legacy interface (non-UEFI mode).
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/include/asm/acpi_table.h | 3 +++ arch/x86/lib/acpi_table.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Per ACPI spec, during ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit in the PM1_CNT register), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers.
However since U-Boot does not support SMI, we report all 3 fields in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following the spec who says: these fields are reserved and must be zero on system that does not support System Management mode.
U-Boot seems to behave in a correct way that the ACPI spec allows, at least Linux does not complain, but apparently Windows does not think so. During Windows bring up debugging, it is observed that even these 3 fields are zero, Windows are still trying to issue SMI with hardcoded SMI port address and commands, and expecting SCI_EN to be changed by the firmware. Eventually Windows gives us a BSOD (Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start.
To fix this, turn on the SCI_EN bit by ourselves. With this patch, now U-Boot can install and boot Windows 8.1/10 successfully with the help of SeaBIOS using legacy interface (non-UEFI mode).
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
arch/x86/include/asm/acpi_table.h | 3 +++ arch/x86/lib/acpi_table.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
The generated AmlCode[] from IASL already has the calculated DSDT table checksum in place. No need for us to calculate it again.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - New patch to remove the unnecessary checksum calculation of DSDT
arch/x86/lib/acpi_table.c | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index a9fe243..05c958d 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -382,12 +382,6 @@ u32 write_acpi_tables(u32 start) (char *)&AmlCode + sizeof(struct acpi_table_header), dsdt->length - sizeof(struct acpi_table_header)); current += dsdt->length - sizeof(struct acpi_table_header); - - /* (Re)calculate length and checksum */ - dsdt->length = current - (u32)dsdt; - dsdt->checksum = 0; - dsdt->checksum = table_compute_checksum((void *)dsdt, - dsdt->length); } current = ALIGN(current, 16);
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
The generated AmlCode[] from IASL already has the calculated DSDT table checksum in place. No need for us to calculate it again.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to remove the unnecessary checksum calculation of DSDT
arch/x86/lib/acpi_table.c | 6 ------ 1 file changed, 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
The generated AmlCode[] from IASL already has the calculated DSDT table checksum in place. No need for us to calculate it again.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to remove the unnecessary checksum calculation of DSDT
arch/x86/lib/acpi_table.c | 6 ------ 1 file changed, 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Before moving 'current' pointer during ACPI table writing, we always check the table length to see if it is larger than the table header. Since our purpose is to generate valid tables, the check logic is always true, which can be avoided.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - New patch to remove header length check when writing tables
arch/x86/lib/acpi_table.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 05c958d..f959f5d 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -376,13 +376,11 @@ u32 write_acpi_tables(u32 start) debug("ACPI: * DSDT\n"); dsdt = (struct acpi_table_header *)current; memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header)); - if (dsdt->length >= sizeof(struct acpi_table_header)) { - current += sizeof(struct acpi_table_header); - memcpy((char *)current, - (char *)&AmlCode + sizeof(struct acpi_table_header), - dsdt->length - sizeof(struct acpi_table_header)); - current += dsdt->length - sizeof(struct acpi_table_header); - } + current += sizeof(struct acpi_table_header); + memcpy((char *)current, + (char *)&AmlCode + sizeof(struct acpi_table_header), + dsdt->length - sizeof(struct acpi_table_header)); + current += dsdt->length - sizeof(struct acpi_table_header); current = ALIGN(current, 16);
debug("ACPI: * FADT\n"); @@ -395,20 +393,16 @@ u32 write_acpi_tables(u32 start) debug("ACPI: * MADT\n"); madt = (struct acpi_madt *)current; acpi_create_madt(madt); - if (madt->header.length > sizeof(struct acpi_madt)) { - current += madt->header.length; - acpi_add_table(rsdp, madt); - } + current += madt->header.length; + acpi_add_table(rsdp, madt); current = ALIGN(current, 16);
debug("ACPI: * MCFG\n"); mcfg = (struct acpi_mcfg *)current; acpi_create_mcfg(mcfg); - if (mcfg->header.length > sizeof(struct acpi_mcfg)) { - current += mcfg->header.length; - current = ALIGN(current, 16); - acpi_add_table(rsdp, mcfg); - } + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + current = ALIGN(current, 16);
debug("current = %x\n", current);
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Before moving 'current' pointer during ACPI table writing, we always check the table length to see if it is larger than the table header. Since our purpose is to generate valid tables, the check logic is always true, which can be avoided.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to remove header length check when writing tables
arch/x86/lib/acpi_table.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Before moving 'current' pointer during ACPI table writing, we always check the table length to see if it is larger than the table header. Since our purpose is to generate valid tables, the check logic is always true, which can be avoided.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to remove header length check when writing tables
arch/x86/lib/acpi_table.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Document how to make SeaBIOS load and run the VGA ROM of Intel IGD device when loaded by U-Boot.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
doc/README.x86 | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/doc/README.x86 b/doc/README.x86 index 25cb218..250d5a3 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -807,6 +807,30 @@ to install/boot a Windows XP OS (below for example command to install Windows). This is also tested on Intel Crown Bay board with a PCIe graphics card, booting SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
+If you are using Intel Integrated Graphics Device (IGD) as the primary display +device on your board, SeaBIOS needs to be patched manually to get its VGA ROM +loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM +register, but IGD device does not have its VGA ROM mapped by this register. +Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address +which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below: + +diff --git a/src/optionroms.c b/src/optionroms.c +index 65f7fe0..c7b6f5e 100644 +--- a/src/optionroms.c ++++ b/src/optionroms.c +@@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources) + rom = deploy_romfile(file); + else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga)) + rom = map_pcirom(pci); ++ if (pci->bdf == pci_to_bdf(0, 2, 0)) ++ rom = (struct rom_header *)0xfff90000; + if (! rom) + // No ROM present. + return; + +Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM +is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX. +Change these two accordingly if this is not the case on your board.
Development Flow ----------------
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Document how to make SeaBIOS load and run the VGA ROM of Intel IGD device when loaded by U-Boot.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
doc/README.x86 | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:00 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Document how to make SeaBIOS load and run the VGA ROM of Intel IGD device when loaded by U-Boot.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
doc/README.x86 | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. Enable it on all BayTrail boards.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - New patch to enable SeaBIOS on all boards
configs/bayleybay_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/minnowmax_defconfig | 1 + 3 files changed, 3 insertions(+)
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 7758c11..9f1d7fb 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -10,6 +10,7 @@ CONFIG_VGA_BIOS_ADDR=0xfffa0000 CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 26f416c..64fd7c9 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 5daa648..28b837d 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. Enable it on all BayTrail boards.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to enable SeaBIOS on all boards
configs/bayleybay_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/minnowmax_defconfig | 1 + 3 files changed, 3 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:01 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. Enable it on all BayTrail boards.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to enable SeaBIOS on all boards
configs/bayleybay_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/minnowmax_defconfig | 1 + 3 files changed, 3 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
As of now, U-Boot can support installing and booting Ubuntu/Windows with the help of SeaBIOS. Update the documentation.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
doc/README.x86 | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/doc/README.x86 b/doc/README.x86 index 250d5a3..75762de 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -1004,12 +1004,14 @@ in the future. The status as of today is: * Support one static DSDT table only, compiled by Intel ACPI compiler. * Support S0/S5, reboot and shutdown from OS. * Support booting a pre-installed Ubuntu distribution via 'zboot' command. + * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with + the help of SeaBIOS using legacy interface (non-UEFI mode). + * Support installing and booting Windows 8.1/10 from U-Boot with the help + of SeaBIOS using legacy interface (non-UEFI mode). * Support ACPI interrupts with SCI only.
Features not supported so far (to make it a complete ACPI solution): * S3 (Suspend to RAM), S4 (Suspend to Disk). - * Install and boot Ubuntu 14.04 (or above) from U-Boot with legacy interface. - * Install and boot Windows 8.1/10 from U-Boot with legacy interface.
Features that are optional: * ACPI global NVS support. We may need it to simplify ASL code logic if @@ -1021,8 +1023,10 @@ Features that are optional: support SMI (a legacy-free system).
So far ACPI is enabled on BayTrail based boards. Testing was done by booting -a pre-installed Ubuntu 14.04 from a SATA drive. Most devices seem to work -correctly and the board can respond a reboot/shutdown command from Ubuntu. +a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and +Windows 8.1/10 to a SATA drive and booting from there is also tested. Most +devices seem to work correctly and the board can respond a reboot/shutdown +command from the OS.
TODO List ---------
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
As of now, U-Boot can support installing and booting Ubuntu/Windows with the help of SeaBIOS. Update the documentation.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
doc/README.x86 | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:01 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
As of now, U-Boot can support installing and booting Ubuntu/Windows with the help of SeaBIOS. Update the documentation.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
doc/README.x86 | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
IASL compiler does not provide a command line option to turn off its non-warning message. To quieten the output when 'make -s', redirect its output to /dev/null.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 44534e1..97a09a2 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -326,7 +326,7 @@ $(obj)/%.S: $(src)/%.ttf quiet_cmd_acpi_c_asl= ASL $< cmd_acpi_c_asl= \ $(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \ - iasl -p $< -tc $<.tmp; \ + iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \ mv $(patsubst %.asl,%.hex,$<) $@
$(obj)/dsdt.c: $(src)/dsdt.asl
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
IASL compiler does not provide a command line option to turn off its non-warning message. To quieten the output when 'make -s', redirect its output to /dev/null.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:01 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
IASL compiler does not provide a command line option to turn off its non-warning message. To quieten the output when 'make -s', redirect its output to /dev/null.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
BayTrail integrates an internal ns15550 compatible UART (PNP0501). Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer revision one IRQ4 is being used for ISA compatibility. Handle this correctly in the ASL file.
Linux does not need this ASL, but Windows need this to correctly discover a COM port existing in the system so that Windows can show it in the 'Device Manager' window, and expose this COM port to any terminal emulation application.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
.../include/asm/arch-baytrail/acpi/irqlinks.asl | 4 ++ arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 60 ++++++++++++++++++++++ 2 files changed, 64 insertions(+)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl index aa72085..0affa23 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl @@ -21,6 +21,10 @@ Scope () PRTF, 8, PRTG, 8, PRTH, 8, + Offset (0x88), + , 3, + UI3E, 1, + UI4E, 1 } }
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl index 1dca977..385671c 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl @@ -14,6 +14,15 @@ Device (LPCB) { Name(_ADR, 0x001f0000)
+ OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + Field(LPC0, AnyAcc, NoLock, Preserve) { + Offset(0x08), + SRID, 8, + Offset(0x80), + C1EN, 1, + Offset(0x84) + } + #include "irqlinks.asl"
/* Firmware Hub */ @@ -81,6 +90,57 @@ Device (LPCB) } }
+ /* Internal UART */ + Device (IURT) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + + Method(_STA, 0, Serialized) + { + /* + * TODO: + * + * Need to hide the internal UART depending on whether + * internal UART is enabled or not so that external + * SuperIO UART can be exposed to system. + */ + Store(1, UI3E) + Store(1, UI4E) + Store(1, C1EN) + Return (STA_VISIBLE) + + } + + Method(_DIS, 0, Serialized) + { + Store(0, UI3E) + Store(0, UI4E) + Store(0, C1EN) + } + + Method(_CRS, 0, Serialized) + { + Name(BUF0, ResourceTemplate() + { + IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) + IRQNoFlags() { 3 } + }) + + Name(BUF1, ResourceTemplate() + { + IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) + IRQNoFlags() { 4 } + }) + + If (LLessEqual(SRID, 0x04)) { + Return (BUF0) + } Else { + Return (BUF1) + } + } + } + /* Real Time Clock */ Device (RTC) {
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
BayTrail integrates an internal ns15550 compatible UART (PNP0501). Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer revision one IRQ4 is being used for ISA compatibility. Handle this correctly in the ASL file.
Linux does not need this ASL, but Windows need this to correctly discover a COM port existing in the system so that Windows can show it in the 'Device Manager' window, and expose this COM port to any terminal emulation application.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
.../include/asm/arch-baytrail/acpi/irqlinks.asl | 4 ++ arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 60 ++++++++++++++++++++++ 2 files changed, 64 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:01 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
BayTrail integrates an internal ns15550 compatible UART (PNP0501). Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer revision one IRQ4 is being used for ISA compatibility. Handle this correctly in the ASL file.
Linux does not need this ASL, but Windows need this to correctly discover a COM port existing in the system so that Windows can show it in the 'Device Manager' window, and expose this COM port to any terminal emulation application.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
.../include/asm/arch-baytrail/acpi/irqlinks.asl | 4 ++ arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 60 ++++++++++++++++++++++ 2 files changed, 64 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - New patch to add GPIO ASL description
arch/x86/include/asm/arch-baytrail/acpi/gpio.asl | 95 ++++++++++++++++++++++ .../include/asm/arch-baytrail/acpi/platform.asl | 3 + 2 files changed, 98 insertions(+) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl new file mode 100644 index 0000000..ef340f3 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* SouthCluster GPIO */ +Device (GPSC) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 1) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_SC_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} + +/* NorthCluster GPIO */ +Device (GPNC) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 2) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_NC_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} + +/* SUS GPIO */ +Device (GPSS) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 3) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_SUS_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index bd72842..6bc82ec 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -27,6 +27,9 @@ Method(_WAK, 1) Scope (_SB) { #include "southcluster.asl" + + /* ACPI devices */ + #include "gpio.asl" }
/* Chipset specific sleep states */
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to add GPIO ASL description
arch/x86/include/asm/arch-baytrail/acpi/gpio.asl | 95 ++++++++++++++++++++++ .../include/asm/arch-baytrail/acpi/platform.asl | 3 + 2 files changed, 98 insertions(+) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:01 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- New patch to add GPIO ASL description
arch/x86/include/asm/arch-baytrail/acpi/gpio.asl | 95 ++++++++++++++++++++++ .../include/asm/arch-baytrail/acpi/platform.asl | 3 + 2 files changed, 98 insertions(+) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Windows might cache system information and only detect ACPI changes if you modify the ACPI table versions.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: None
doc/README.x86 | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/doc/README.x86 b/doc/README.x86 index 75762de..4d50feb 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -982,6 +982,12 @@ transformations. Remember to add attribution to coreboot for new files added to U-Boot. This should go at the top of each file and list the coreboot filename where the code originated.
+Debugging ACPI issues with Windows: + +Windows might cache system information and only detect ACPI changes if you +modify the ACPI table versions. So tweak them liberally when debugging ACPI +issues with Windows. + ACPI Support Status ------------------- Advanced Configuration and Power Interface (ACPI) [16] aims to establish
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Windows might cache system information and only detect ACPI changes if you modify the ACPI table versions.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
doc/README.x86 | 6 ++++++ 1 file changed, 6 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Thu, May 19, 2016 at 12:01 PM, Simon Glass sjg@chromium.org wrote:
On 11 May 2016 at 08:45, Bin Meng bmeng.cn@gmail.com wrote:
Windows might cache system information and only detect ACPI changes if you modify the ACPI table versions.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2: None
doc/README.x86 | 6 ++++++ 1 file changed, 6 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
Hi Simon,
On Wed, May 11, 2016 at 10:44 PM, Bin Meng bmeng.cn@gmail.com wrote:
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. But till now this is broken. The installation either hangs forever or just crashes.
This series fixed a bunch of issues that affect the installation of Ubuntu and Windows, and booting Windows.
Testing was performed on MinnowMax by:
- Install Ubuntu 14.04 and boot
- Install Windows 8.1 and boot
- Install Windows 10 and boot
This series is available at u-boot-x86/acpi2-working.
Changes in v2:
- New patch to remove the unnecessary checksum calculation of DSDT
- New patch to remove header length check when writing tables
- New patch to enable SeaBIOS on all boards
- New patch to add GPIO ASL description
Do you want to review and test this series, before I apply?
Regards, Bin
Hi Bin,
On 17 May 2016 at 20:14, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, May 11, 2016 at 10:44 PM, Bin Meng bmeng.cn@gmail.com wrote:
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. But till now this is broken. The installation either hangs forever or just crashes.
This series fixed a bunch of issues that affect the installation of Ubuntu and Windows, and booting Windows.
Testing was performed on MinnowMax by:
- Install Ubuntu 14.04 and boot
- Install Windows 8.1 and boot
- Install Windows 10 and boot
This series is available at u-boot-x86/acpi2-working.
Changes in v2:
- New patch to remove the unnecessary checksum calculation of DSDT
- New patch to remove header length check when writing tables
- New patch to enable SeaBIOS on all boards
- New patch to add GPIO ASL description
Do you want to review and test this series, before I apply?
It looks good, please go ahead. I will test it at some point but not soon unfortunately. Looks like what I have been waiting for to get the Ubuntu installer running properly.
Regards, Simon
participants (2)
-
Bin Meng -
Simon Glass