[U-Boot] [PATCH 0/3] ARM: DRA74x: Add support for ES2.0
Hi,
This series add detection and basic support for DRA74x/DRA75x support, and adds support for dra74x-evm platform.
Nishanth Menon (3): ARM: DRA7: Add detection of ES2.0 ARM: DRA74-evm: Add iodelay values for SR2.0 ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0
arch/arm/cpu/armv7/omap5/hw_data.c | 2 + arch/arm/cpu/armv7/omap5/hwinit.c | 3 ++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 9 ++++ arch/arm/cpu/armv7/omap5/sdram.c | 4 ++ arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 4 ++ arch/arm/include/asm/arch-omap5/omap.h | 3 ++ arch/arm/include/asm/omap_common.h | 2 + board/ti/dra7xx/evm.c | 39 ++++++++++++---- board/ti/dra7xx/mux_data.h | 58 +++++++++++++++++++++++- 9 files changed, 113 insertions(+), 11 deletions(-)
Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp
[ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com Acked-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 2 ++ arch/arm/cpu/armv7/omap5/hwinit.c | 3 +++ arch/arm/cpu/armv7/omap5/sdram.c | 4 ++++ arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/omap_common.h | 1 + 5 files changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 3a723cace71a..3fe8268f7508 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -643,6 +643,7 @@ void __weak hw_data_init(void)
case DRA752_ES1_0: case DRA752_ES1_1: + case DRA752_ES2_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; *omap_vcores = &dra752_volts; @@ -678,6 +679,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA752_ES2_0: *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 39f8d0d5e200..57a3644ad82b 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -365,6 +365,9 @@ void init_omap_revision(void) case DRA752_CONTROL_ID_CODE_ES1_1: *omap_si_rev = DRA752_ES1_1; break; + case DRA752_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = DRA752_ES2_0; + break; case DRA722_CONTROL_ID_CODE_ES1_0: *omap_si_rev = DRA722_ES1_0; break; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index cf4452d260f3..a8d63c23c8c6 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -284,6 +284,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA752_ES2_0: switch (emif_nr) { case 1: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; @@ -316,6 +317,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA752_ES2_0: *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; break; case DRA722_ES1_0: @@ -569,6 +571,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA752_ES2_0: if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; *size = @@ -792,6 +795,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA752_ES2_0: case DRA722_ES1_0: bug_00339_regs_ptr = dra_bug_00339_regs; *iterations = sizeof(dra_bug_00339_regs)/ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 524fae4bb9c6..ddf5c7a8eae7 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -52,6 +52,7 @@ #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F +#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
/* UART */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 056affc3fabd..2f2001d3253f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -672,6 +672,7 @@ static inline u8 is_dra72x(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 #define DRA752_ES1_1 0x07520110 +#define DRA752_ES2_0 0x07520200 #define DRA722_ES1_0 0x07220100
/*
On Thu, Aug 13, 2015 at 09:50:58AM -0500, Nishanth Menon wrote:
Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following:
- reset logic fixes
- few assymetric aging logic fixes
- MMC clock rate fixes
- Ethernet speed fixes
- edma fixes for mcasp
[ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com Acked-by: Lokesh Vutla lokeshvutla@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Thu, Aug 13, 2015 at 09:50:58AM -0500, Nishanth Menon wrote:
Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following:
- reset logic fixes
- few assymetric aging logic fixes
- MMC clock rate fixes
- Ethernet speed fixes
- edma fixes for mcasp
[ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu ravibabu@ti.com Signed-off-by: Nishanth Menon nm@ti.com Acked-by: Lokesh Vutla lokeshvutla@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same.
Based on data from VayuES2_EVM_Base_Config-20150807.
NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification.
Signed-off-by: Nishanth Menon nm@ti.com --- board/ti/dra7xx/evm.c | 36 ++++++++++++++++++++-------- board/ti/dra7xx/mux_data.h | 58 +++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 94a1a8c25656..9603f10f8ade 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -80,17 +80,33 @@ void set_muxconf_regs_essential(void) #ifdef CONFIG_IODELAY_RECALIBRATION void recalibrate_iodelay(void) { - if (is_dra72x()) { - __recalibrate_iodelay(core_padconf_array_essential, - ARRAY_SIZE(core_padconf_array_essential), - iodelay_cfg_array, - ARRAY_SIZE(iodelay_cfg_array)); - } else { - __recalibrate_iodelay(dra74x_core_padconf_array, - ARRAY_SIZE(dra74x_core_padconf_array), - dra742_iodelay_cfg_array, - ARRAY_SIZE(dra742_iodelay_cfg_array)); + struct pad_conf_entry const *pads; + struct iodelay_cfg_entry const *iodelay; + int npads, niodelays; + + switch (omap_revision()) { + case DRA722_ES1_0: + pads = core_padconf_array_essential; + npads = ARRAY_SIZE(core_padconf_array_essential); + iodelay = iodelay_cfg_array; + niodelays = ARRAY_SIZE(iodelay_cfg_array); + break; + case DRA752_ES1_0: + case DRA752_ES1_1: + pads = dra74x_core_padconf_array; + npads = ARRAY_SIZE(dra74x_core_padconf_array); + iodelay = dra742_es1_1_iodelay_cfg_array; + niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); + break; + default: + case DRA752_ES2_0: + pads = dra74x_core_padconf_array; + npads = ARRAY_SIZE(dra74x_core_padconf_array); + iodelay = dra742_es2_0_iodelay_cfg_array; + niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); + break; } + __recalibrate_iodelay(pads, npads, iodelay, niodelays); } #endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index ea8ee9fb3a63..bf401443e465 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -376,7 +376,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { };
#ifdef CONFIG_IODELAY_RECALIBRATION -const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = { +const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ @@ -431,6 +431,62 @@ const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = { {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ }; + +const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { + {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */ + {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */ + {0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */ + {0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */ + {0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */ + {0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */ + {0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */ + {0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */ + {0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */ + {0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */ + {0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */ + {0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */ + {0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */ + {0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */ + {0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */ + {0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */ + {0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */ + {0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */ + {0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */ + {0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */ + {0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */ + {0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */ + {0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */ + {0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */ + {0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */ + {0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */ + {0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */ + {0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */ + {0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */ + {0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */ + {0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */ +}; #endif
#endif /* _MUX_DATA_DRA7XX_H_ */
On Thu, Aug 13, 2015 at 09:50:59AM -0500, Nishanth Menon wrote:
Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same.
Based on data from VayuES2_EVM_Base_Config-20150807.
NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Thu, Aug 13, 2015 at 09:50:59AM -0500, Nishanth Menon wrote:
Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same.
Based on data from VayuES2_EVM_Base_Config-20150807.
NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work.
Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform.
NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 9 +++++++++ arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 4 ++++ arch/arm/include/asm/arch-omap5/omap.h | 2 ++ arch/arm/include/asm/omap_common.h | 1 + board/ti/dra7xx/evm.c | 3 +++ 5 files changed, 19 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index cd51fe7678be..251e0af9fc6f 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -11,6 +11,7 @@ */
#include <asm/omap_common.h> +#include <asm/io.h>
struct prcm_regs const omap5_es1_prcm = { /* cm1.ckgen */ @@ -379,6 +380,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_phy_power_usb = 0x4A002370, .control_phy_power_sata = 0x4A002374, .ctrl_core_sma_sw_0 = 0x4A0023FC, + .ctrl_core_sma_sw_1 = 0x4A002534, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, .control_core_mac_id_1_lo = 0x4A00251C, @@ -990,3 +992,10 @@ struct prcm_regs const dra7xx_prcm = { .prm_abbldo_mpu_setup = 0x4AE07DDC, .prm_abbldo_mpu_ctrl = 0x4AE07DE0, }; + +void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits) +{ + u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 : + (*ctrl)->ctrl_core_sma_sw_0; + clrsetbits_le32(reg, clear_bits, set_bits); +} diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index 2f53d85283b8..4cd0a3cc80d0 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -49,6 +49,10 @@ #define ISOLATE_IO 1 #define DEISOLATE_IO 0
+/* CTRL_CORE_SMA_SW_1 */ +#define RGMII2_ID_MODE_N_MASK (1 << 26) +#define RGMII1_ID_MODE_N_MASK (1 << 25) + /* PRM_IO_PMCTRL */ #define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 #define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index ddf5c7a8eae7..c3296412adeb 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -235,6 +235,8 @@ struct ctrl_ioregs { u32 ctrl_ddr_ctrl_ext_0; };
+void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); + #endif /* __ASSEMBLY__ */
/* Boot parameters */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2f2001d3253f..7be29a682ba0 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -462,6 +462,7 @@ struct omap_sys_ctrl_regs { u32 control_padconf_wkup_base; u32 iodelay_config_base; u32 ctrl_core_sma_sw_0; + u32 ctrl_core_sma_sw_1; };
struct dpll_params { diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9603f10f8ade..6e3c85513f89 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -104,6 +104,9 @@ void recalibrate_iodelay(void) npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); + /* Setup port1 and port2 for rgmii with 'no-id' mode */ + clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | + RGMII1_ID_MODE_N_MASK); break; } __recalibrate_iodelay(pads, npads, iodelay, niodelays);
On Thu, Aug 13, 2015 at 09:51:00AM -0500, Nishanth Menon wrote:
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work.
Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform.
NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Thu, Aug 13, 2015 at 09:51:00AM -0500, Nishanth Menon wrote:
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work.
Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform.
NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
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