[PATCH v2 0/2] arm: zynqmp: Initialize some registers at boot
These patches are independent in intent, but they modify adjacent lines so I have sent them as a series.
Changes in v2: - Don't set reserved bits in AXI_RPRTCN, since QSPI doesn't use ARPROT
Sean Anderson (2): zynqmp: Disable secure access for boot devices arm: zynqmp: Enable non-invasive CCI-400 PMU debug
arch/arm/mach-zynqmp/include/mach/hardware.h | 5 +++++ board/xilinx/zynqmp/zynqmp.c | 8 ++++++++ 2 files changed, 13 insertions(+)
Boot devices (QSPI, MMC, NAND, and Ethernet) use secure access for DMA by default. As this causes problems when using the SMMU [1], configure them for normal access instead.
[1] https://support.xilinx.com/s/article/72164
Signed-off-by: Sean Anderson sean.anderson@linux.dev ---
Changes in v2: - Don't set reserved bits in AXI_RPRTCN, since QSPI doesn't use ARPROT
arch/arm/mach-zynqmp/include/mach/hardware.h | 2 ++ board/xilinx/zynqmp/zynqmp.c | 4 ++++ 2 files changed, 6 insertions(+)
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 8cb6494e52c..f1514d6a869 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -63,6 +63,8 @@ struct crlapb_regs {
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
+#define ZYNQMP_IOU_SECURE_SLCR 0xFF240000 + #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index e6331c0e4d8..56e3b36ca99 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -72,6 +72,10 @@ int __maybe_unused psu_uboot_init(void) writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL, ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
+ /* Disable secure access for boot devices */ + writel(0x04920492, ZYNQMP_IOU_SECURE_SLCR); + writel(0x00920492, ZYNQMP_IOU_SECURE_SLCR + 4); + /* Delay is required for clocks to be propagated */ udelay(1000000);
Set NIDEN, enabling non-invasive debug for the CCI-400 PMU. Otherwise, the PMU is effectively disabled.
Signed-off-by: Sean Anderson sean.anderson@linux.dev Reviewed-by: Michal Simek michal.simek@amd.com ---
(no changes since v1)
arch/arm/mach-zynqmp/include/mach/hardware.h | 3 +++ board/xilinx/zynqmp/zynqmp.c | 4 ++++ 2 files changed, 7 insertions(+)
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index f1514d6a869..51eab3509b8 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -128,6 +128,9 @@ struct crfapb_regs {
#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
+#define ZYNQMP_CCI_REG_CCI_MISC_CTRL 0xFD5E0040 +#define ZYNQMP_CCI_REG_CCI_MISC_CTRL_NIDEN BIT(1) + #define ZYNQMP_APU_BASEADDR 0xFD5C0000
struct apu_regs { diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 56e3b36ca99..20a675c010d 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -76,6 +76,10 @@ int __maybe_unused psu_uboot_init(void) writel(0x04920492, ZYNQMP_IOU_SECURE_SLCR); writel(0x00920492, ZYNQMP_IOU_SECURE_SLCR + 4);
+ /* Enable CCI PMU events */ + writel(ZYNQMP_CCI_REG_CCI_MISC_CTRL_NIDEN, + ZYNQMP_CCI_REG_CCI_MISC_CTRL); + /* Delay is required for clocks to be propagated */ udelay(1000000);
On 9/5/24 19:18, Sean Anderson wrote:
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These patches are independent in intent, but they modify adjacent lines so I have sent them as a series.
Changes in v2:
- Don't set reserved bits in AXI_RPRTCN, since QSPI doesn't use ARPROT
Sean Anderson (2): zynqmp: Disable secure access for boot devices arm: zynqmp: Enable non-invasive CCI-400 PMU debug
arch/arm/mach-zynqmp/include/mach/hardware.h | 5 +++++ board/xilinx/zynqmp/zynqmp.c | 8 ++++++++ 2 files changed, 13 insertions(+)
-- 2.35.1.1320.gc452695387.dirty
Applied. M
participants (2)
-
Michal Simek -
Sean Anderson