This board has not been converted to DM_SERIAL by the deadline. Remove it.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: None

arch/arm/Kconfig | 5 - board/mpl/common/common_util.c | 23 -- board/mpl/vcma9/Kconfig | 15 -- board/mpl/vcma9/MAINTAINERS | 6 - board/mpl/vcma9/Makefile | 11 - board/mpl/vcma9/cmd_vcma9.c | 119 ---------- board/mpl/vcma9/lowlevel_init.S | 500 ---------------------------------------- board/mpl/vcma9/vcma9.c | 209 ----------------- board/mpl/vcma9/vcma9.h | 28 --- configs/VCMA9_defconfig | 17 -- include/configs/VCMA9.h | 205 ---------------- scripts/config_whitelist.txt | 1 - 12 files changed, 1139 deletions(-) delete mode 100644 board/mpl/vcma9/Kconfig delete mode 100644 board/mpl/vcma9/MAINTAINERS delete mode 100644 board/mpl/vcma9/Makefile delete mode 100644 board/mpl/vcma9/cmd_vcma9.c delete mode 100644 board/mpl/vcma9/lowlevel_init.S delete mode 100644 board/mpl/vcma9/vcma9.c delete mode 100644 board/mpl/vcma9/vcma9.h delete mode 100644 configs/VCMA9_defconfig delete mode 100644 include/configs/VCMA9.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 398dbe0..993485a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -142,10 +142,6 @@ config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T

-config TARGET_VCMA9 - bool "Support VCMA9" - select CPU_ARM920T - config TARGET_ASPENITE bool "Support aspenite" select CPU_ARM926EJS @@ -971,7 +967,6 @@ source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" -source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/phytec/pcm052/Kconfig" diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index a6edb6d..101b6ef 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -273,29 +273,6 @@ mpl_prg(uchar *src, ulong size) return (1); } #endif /* defined(CONFIG_PATI) */ - -#elif defined(CONFIG_VCMA9) - start = 0; - - /* search end sector */ - for (i = 0; i < info->sector_count; i++) - if (size < info->start[i]) - break; - - flash_protect(FLAG_PROTECT_CLEAR, - start, - size, - info); - - /* now erase flash */ - printf("Erasing at %lx (sector %d) (start %lx)\n", - start,0,info->start[0]); - if ((rc = flash_erase (info, 0, i)) != 0) { - puts("ERROR "); - flash_perror(rc); - return (1); - } - #endif printf("flash erased, programming from 0x%lx 0x%lx Bytes\n", (ulong)src, size); diff --git a/board/mpl/vcma9/Kconfig b/board/mpl/vcma9/Kconfig deleted file mode 100644 index a156452..0000000 --- a/board/mpl/vcma9/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_VCMA9 - -config SYS_BOARD - default "vcma9" - -config SYS_VENDOR - default "mpl" - -config SYS_SOC - default "s3c24x0" - -config SYS_CONFIG_NAME - default "VCMA9" - -endif diff --git a/board/mpl/vcma9/MAINTAINERS b/board/mpl/vcma9/MAINTAINERS deleted file mode 100644 index 3817436..0000000 --- a/board/mpl/vcma9/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -VCMA9 BOARD -M: David Müller d.mueller@elsoft.ch -S: Maintained -F: board/mpl/vcma9/ -F: include/configs/VCMA9.h -F: configs/VCMA9_defconfig diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile deleted file mode 100644 index 175a19f..0000000 --- a/board/mpl/vcma9/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ../common/common_util.o -obj-y += vcma9.o cmd_vcma9.o - -obj-y += lowlevel_init.o diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c deleted file mode 100644 index c2d62e4..0000000 --- a/board/mpl/vcma9/cmd_vcma9.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2002 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * adapted for VCMA9 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <net.h> -#include "vcma9.h" -#include "../common/common_util.h" - -#if defined(CONFIG_CS8900) -#include <../drivers/net/cs8900.h> - -static uchar cs8900_chksum(ushort data) -{ - return((data >> 8) & 0x00FF) + (data & 0x00FF); -} - -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct eth_device *dev; - char cs8900_name[10]; - if (strcmp(argv[1], "info") == 0) - { - vcma9_print_info(); - return 0; - } -#if defined(CONFIG_CS8900) - if (strcmp(argv[1], "cs8900") == 0) { - sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME); - dev = eth_get_dev_by_name(cs8900_name); - if (!dev) { - printf("Couldn't find CS8900 driver"); - return 0; - } - if (strcmp(argv[2], "read") == 0) { - uchar addr; ushort data; - - addr = simple_strtoul(argv[3], NULL, 16); - cs8900_e2prom_read(dev, addr, &data); - printf("0x%2.2X: 0x%4.4X\n", addr, data); - } else if (strcmp(argv[2], "write") == 0) { - uchar addr; ushort data; - - addr = simple_strtoul(argv[3], NULL, 16); - data = simple_strtoul(argv[4], NULL, 16); - cs8900_e2prom_write(dev, addr, data); - } else if (strcmp(argv[2], "setaddr") == 0) { - uchar addr, i, csum; ushort data; - uchar ethaddr[6]; - - /* check for valid ethaddr */ - if (eth_getenv_enetaddr("ethaddr", ethaddr)) { - addr = 1; - data = 0x2158; - cs8900_e2prom_write(dev, addr, data); - csum = cs8900_chksum(data); - addr++; - for (i = 0; i < 6; i+=2) { - data = ethaddr[i+1] << 8 | - ethaddr[i]; - cs8900_e2prom_write(dev, addr, data); - csum += cs8900_chksum(data); - addr++; - } - /* calculate header link byte */ - data = 0xA100 | (addr * 2); - cs8900_e2prom_write(dev, 0, data); - csum += cs8900_chksum(data); - /* write checksum word */ - cs8900_e2prom_write(dev, addr, (0 - csum) << 8); - } else { - puts("\nplease defined 'ethaddr'\n"); - } - } else if (strcmp(argv[2], "dump") == 0) { - uchar addr = 0, endaddr, csum; ushort data; - - puts("Dump of CS8900 config device: "); - cs8900_e2prom_read(dev, addr, &data); - if ((data & 0xE000) == 0xA000) { - endaddr = (data & 0x00FF) / 2; - csum = cs8900_chksum(data); - for (addr = 1; addr <= endaddr; addr++) { - cs8900_e2prom_read(dev, addr, &data); - printf("\n0x%2.2X: 0x%4.4X", addr, data); - csum += cs8900_chksum(data); - } - printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong"); - } else { - puts("no valid config found"); - } - puts("\n"); - } - - return 0; - } -#endif - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} - -U_BOOT_CMD( - vcma9, 6, 1, do_vcma9, - "VCMA9 specific commands", - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" - "vcma9 info - displays board information" -); diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S deleted file mode 100644 index c0d6cc8..0000000 --- a/board/mpl/vcma9/lowlevel_init.S +++ /dev/null @@ -1,500 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for MPL VCMA9 by - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * (C) Copyright 2002, 2003, 2004, 2005 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <config.h> - -/* register definitions */ - -#define PLD_BASE 0x28000000 -#define MISC_REG 0x103 -#define SDRAM_REG 0x106 -#define BWSCON 0x48000000 -#define CLKBASE 0x4C000000 -#define LOCKTIME 0x0 -#define MPLLCON 0x4 -#define UPLLCON 0x8 -#define GPIOBASE 0x56000000 -#define GSTATUS1 0xB0 -#define FASTCPU 0x02 - -/* some parameters for the board */ -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -/* BANKSIZE */ -#define BURST_EN (0x1<<7) - -/* BANK0CON 200 */ -#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ -#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ -#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ -#define B0_Tcoh_200 0x0 /* 0clk */ -#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ -#define B0_Tacp_200 0x0 /* page mode is not used */ -#define B0_PMC_200 0x0 /* page mode disabled */ - -/* BANK0CON 250 */ -#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ -#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ -#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ -#define B0_Tcoh_250 0x0 /* 0clk */ -#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ -#define B0_Tacp_250 0x0 /* page mode is not used */ -#define B0_PMC_250 0x0 /* page mode disabled */ - -/* BANK0CON 266 */ -#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ -#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ -#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ -#define B0_Tcoh_266 0x0 /* 0clk */ -#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ -#define B0_Tacp_266 0x0 /* page mode is not used */ -#define B0_PMC_266 0x0 /* page mode disabled */ - -/* BANK1CON 200 */ -#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ -#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ -#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ -#define B1_Tcoh_200 0x0 /* 0clk */ -#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ -#define B1_Tacp_200 0x0 /* page mode is not used */ -#define B1_PMC_200 0x0 /* page mode disabled */ - -/* BANK1CON 250 */ -#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ -#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ -#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ -#define B1_Tcoh_250 0x0 /* 0clk */ -#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ -#define B1_Tacp_250 0x0 /* page mode is not used */ -#define B1_PMC_250 0x0 /* page mode disabled */ - -/* BANK1CON 266 */ -#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ -#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ -#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ -#define B1_Tcoh_266 0x0 /* 0clk */ -#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ -#define B1_Tacp_266 0x0 /* page mode is not used */ -#define B1_PMC_266 0x0 /* page mode disabled */ - -/* BANK2CON 200 + 250 + 266 */ -#define B2_Tacs 0x3 /* 4clk */ -#define B2_Tcos 0x3 /* 4clk */ -#define B2_Tacc 0x7 /* 14clk */ -#define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tcah 0x3 /* 4clk */ -#define B2_Tacp 0x0 /* page mode is not used */ -#define B2_PMC 0x0 /* page mode disabled */ - -/* BANK3CON 200 + 250 + 266 */ -#define B3_Tacs 0x3 /* 4clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tcah 0x3 /* 4clk */ -#define B3_Tacp 0x0 /* page mode is not used */ -#define B3_PMC 0x0 /* page mode disabled */ - -/* BANK4CON 200 */ -#define B4_Tacs_200 0x1 /* 1clk */ -#define B4_Tcos_200 0x3 /* 4clk */ -#define B4_Tacc_200 0x7 /* 14clk */ -#define B4_Tcoh_200 0x3 /* 4clk */ -#define B4_Tcah_200 0x2 /* 2clk */ -#define B4_Tacp_200 0x0 /* page mode is not used */ -#define B4_PMC_200 0x0 /* page mode disabled */ - -/* BANK4CON 250 */ -#define B4_Tacs_250 0x1 /* 1clk */ -#define B4_Tcos_250 0x3 /* 4clk */ -#define B4_Tacc_250 0x7 /* 14clk */ -#define B4_Tcoh_250 0x3 /* 4clk */ -#define B4_Tcah_250 0x2 /* 2clk */ -#define B4_Tacp_250 0x0 /* page mode is not used */ -#define B4_PMC_250 0x0 /* page mode disabled */ - -/* BANK4CON 266 */ -#define B4_Tacs_266 0x1 /* 1clk */ -#define B4_Tcos_266 0x3 /* 4clk */ -#define B4_Tacc_266 0x7 /* 14clk */ -#define B4_Tcoh_266 0x3 /* 4clk */ -#define B4_Tcah_266 0x2 /* 2clk */ -#define B4_Tacp_266 0x0 /* page mode is not used */ -#define B4_PMC_266 0x0 /* page mode disabled */ - -/* BANK5CON 200 */ -#define B5_Tacs_200 0x0 /* 0clk */ -#define B5_Tcos_200 0x3 /* 4clk */ -#define B5_Tacc_200 0x4 /* 6clk */ -#define B5_Tcoh_200 0x3 /* 4clk */ -#define B5_Tcah_200 0x1 /* 1clk */ -#define B5_Tacp_200 0x0 /* page mode is not used */ -#define B5_PMC_200 0x0 /* page mode disabled */ - -/* BANK5CON 250 */ -#define B5_Tacs_250 0x0 /* 0clk */ -#define B5_Tcos_250 0x3 /* 4clk */ -#define B5_Tacc_250 0x5 /* 8clk */ -#define B5_Tcoh_250 0x3 /* 4clk */ -#define B5_Tcah_250 0x1 /* 1clk */ -#define B5_Tacp_250 0x0 /* page mode is not used */ -#define B5_PMC_250 0x0 /* page mode disabled */ - -/* BANK5CON 266 */ -#define B5_Tacs_266 0x0 /* 0clk */ -#define B5_Tcos_266 0x3 /* 4clk */ -#define B5_Tacc_266 0x5 /* 8clk */ -#define B5_Tcoh_266 0x3 /* 4clk */ -#define B5_Tcah_266 0x1 /* 1clk */ -#define B5_Tacp_266 0x0 /* page mode is not used */ -#define B5_PMC_266 0x0 /* page mode disabled */ - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd_200 0x0 /* 2clk */ -#define B6_Trcd_250 0x1 /* 3clk */ -#define B6_Trcd_266 0x1 /* 3clk */ -#define B6_SCAN 0x2 /* 10bit */ - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd_200 0x0 /* 2clk */ -#define B7_Trcd_250 0x1 /* 3clk */ -#define B7_Trcd_266 0x1 /* 3clk */ -#define B7_SCAN 0x2 /* 10bit */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp_200 0x0 /* 2clk */ -#define Trp_250 0x1 /* 3clk */ -#define Trp_266 0x1 /* 3clk */ -#define Tsrc_200 0x1 /* 5clk */ -#define Tsrc_250 0x2 /* 6clk */ -#define Tsrc_266 0x3 /* 7clk */ - -/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ -#define REFCNT_200 489 -/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ -#define REFCNT_250 99 -/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ -#define REFCNT_266 0 -/**************************************/ - -.globl lowlevel_init -lowlevel_init: - /* use r0 to relocate DATA read/write to flash rather than memory ! */ - ldr r0, =CONFIG_SYS_TEXT_BASE - ldr r13, =BWSCON - - /* enable minimal access to PLD */ - ldr r1, [r13] /* load default BWSCON */ - orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ - str r1, [r13] /* set BWSCON */ - ldr r1, =0x7FF0 /* select slowest timing */ - str r1, [r13, #0x18] /* set BANKCON5 */ - - ldr r1, =PLD_BASE - ldr r2, =SETUPDATA - ldrb r1, [r1, #MISC_REG] - sub r2, r2, r0 - tst r1, #FASTCPU /* FASTCPU available ? */ - addeq r2, r2, #SETUPENTRY_SIZE - - /* memory control configuration */ - /* r2 = pointer into timing table */ - /* r13 = pointer to MEM controller regs (starting with BWSCON) */ - add r3, r2, #CSDATA_OFFSET - add r4, r3, #CSDATAENTRY_SIZE -0: - ldr r1, [r3], #4 - str r1, [r13], #4 - cmp r3, r4 - bne 0b - - /* PLD access is now possible */ - /* r3 = SDRAMDATA */ - /* r13 = pointer to MEM controller regs */ - ldr r1, =PLD_BASE - mov r4, #SDRAMENTRY_SIZE - ldrb r1, [r1, #SDRAM_REG] - /* calculate start and end point */ - mla r3, r4, r1, r3 - add r4, r3, r4 -0: - ldr r1, [r3], #4 - str r1, [r13], #4 - cmp r3, r4 - bne 0b - - /* setup MPLL registers */ - ldr r1, =CLKBASE - ldr r4, =0xFFFFFF - add r3, r2, #4 /* r3 points to PLL values */ - str r4, [r1, #LOCKTIME] - ldmia r3, {r4,r5} - str r5, [r1, #UPLLCON] /* writing PLL register */ - /* !! order seems to be important !! */ - /* a little delay */ - ldr r3, =0x4000 -0: - subs r3, r3, #1 - bne 0b - - str r4, [r1, #MPLLCON] /* writing PLL register */ - /* !! order seems to be important !! */ - /* a little delay */ - ldr r3, =0x4000 -0: - subs r3, r3, #1 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ - ((bws1) << 4) + \ - ((bws2) << 8) + \ - ((bws3) << 12) + \ - ((bws4) << 16) + \ - ((bws5) << 20) + \ - ((bws6) << 24) + \ - ((bws7) << 28) - -#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ - ((tacs) << 13) + \ - ((tcos) << 11) + \ - ((tacc) << 8) + \ - ((tcoh) << 6) + \ - ((tcah) << 4) + \ - ((tacp) << 2) + \ - (pmc) - -#define MK_BANKCON_SDRAM(trcd, scan) \ - ((0x03) << 15) + \ - ((trcd) << 2) + \ - (scan) - -#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ - ((enable) << 23) + \ - ((trefmd) << 22) + \ - ((trp) << 20) + \ - ((tsrc) << 18) + \ - (cnt) - -SETUPDATA: - .word 0x32410002 - /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ - .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) - /* PLL values for USB clock */ - .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) - - /* timing for 250 MHz*/ -0: - .equiv CSDATA_OFFSET, (. - SETUPDATA) - .word MK_BWSCON(DW16, \ - DW32, \ - DW32, \ - DW16 + WAIT + UBLB, \ - DW8 + UBLB, \ - DW32, \ - DW32) - - .word MK_BANKCON(B0_Tacs_250, \ - B0_Tcos_250, \ - B0_Tacc_250, \ - B0_Tcoh_250, \ - B0_Tcah_250, \ - B0_Tacp_250, \ - B0_PMC_250) - - .word MK_BANKCON(B1_Tacs_250, \ - B1_Tcos_250, \ - B1_Tacc_250, \ - B1_Tcoh_250, \ - B1_Tcah_250, \ - B1_Tacp_250, \ - B1_PMC_250) - - .word MK_BANKCON(B2_Tacs, \ - B2_Tcos, \ - B2_Tacc, \ - B2_Tcoh, \ - B2_Tcah, \ - B2_Tacp, \ - B2_PMC) - - .word MK_BANKCON(B3_Tacs, \ - B3_Tcos, \ - B3_Tacc, \ - B3_Tcoh, \ - B3_Tcah, \ - B3_Tacp, \ - B3_PMC) - - .word MK_BANKCON(B4_Tacs_250, \ - B4_Tcos_250, \ - B4_Tacc_250, \ - B4_Tcoh_250, \ - B4_Tcah_250, \ - B4_Tacp_250, \ - B4_PMC_250) - - .word MK_BANKCON(B5_Tacs_250, \ - B5_Tcos_250, \ - B5_Tacc_250, \ - B5_Tcoh_250, \ - B5_Tcah_250, \ - B5_Tacp_250, \ - B5_PMC_250) - - .equiv CSDATAENTRY_SIZE, (. - 0b) - /* 4Mx8x4 */ -0: - .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - .equiv SDRAMENTRY_SIZE, (. - 0b) - - /* 8Mx8x4 */ - .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - - /* 2Mx8x4 */ - .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - - /* 4Mx8x2 */ - .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - - .equiv SETUPENTRY_SIZE, (. - SETUPDATA) - - .word 0x32410000 - /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ - .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) - /* PLL values for USB clock */ - .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) - - /* timing for 200 MHz and default*/ - .word MK_BWSCON(DW16, \ - DW32, \ - DW32, \ - DW16 + WAIT + UBLB, \ - DW8 + UBLB, \ - DW32, \ - DW32) - - .word MK_BANKCON(B0_Tacs_200, \ - B0_Tcos_200, \ - B0_Tacc_200, \ - B0_Tcoh_200, \ - B0_Tcah_200, \ - B0_Tacp_200, \ - B0_PMC_200) - - .word MK_BANKCON(B1_Tacs_200, \ - B1_Tcos_200, \ - B1_Tacc_200, \ - B1_Tcoh_200, \ - B1_Tcah_200, \ - B1_Tacp_200, \ - B1_PMC_200) - - .word MK_BANKCON(B2_Tacs, \ - B2_Tcos, \ - B2_Tacc, \ - B2_Tcoh, \ - B2_Tcah, \ - B2_Tacp, \ - B2_PMC) - - .word MK_BANKCON(B3_Tacs, \ - B3_Tcos, \ - B3_Tacc, \ - B3_Tcoh, \ - B3_Tcah, \ - B3_Tacp, \ - B3_PMC) - - .word MK_BANKCON(B4_Tacs_200, \ - B4_Tcos_200, \ - B4_Tacc_200, \ - B4_Tcoh_200, \ - B4_Tcah_200, \ - B4_Tacp_200, \ - B4_PMC_200) - - .word MK_BANKCON(B5_Tacs_200, \ - B5_Tcos_200, \ - B5_Tacc_200, \ - B5_Tcoh_200, \ - B5_Tcah_200, \ - B5_Tacp_200, \ - B5_PMC_200) - - /* 4Mx8x4 */ - .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - - /* 8Mx8x4 */ - .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - - /* 2Mx8x4 */ - .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - - /* 4Mx8x2 */ - .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) - .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) - .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - - .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c deleted file mode 100644 index 43a3d47..0000000 --- a/board/mpl/vcma9/vcma9.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002, 2010 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <i2c.h> -#include <asm/io.h> -#include <asm/arch/s3c24x0_cpu.h> - -#include "vcma9.h" -#include "../common/common_util.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_early_init_f(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* set up the I/O ports */ - writel(0x007FFFFF, &gpio->gpacon); - writel(0x002AAAAA, &gpio->gpbcon); - writel(0x000002BF, &gpio->gpbup); - writel(0xAAAAAAAA, &gpio->gpccon); - writel(0x0000FFFF, &gpio->gpcup); - writel(0xAAAAAAAA, &gpio->gpdcon); - writel(0x0000FFFF, &gpio->gpdup); - writel(0xAAAAAAAA, &gpio->gpecon); - writel(0x000037F7, &gpio->gpeup); - writel(0x00000000, &gpio->gpfcon); - writel(0x00000000, &gpio->gpfup); - writel(0xFFEAFF5A, &gpio->gpgcon); - writel(0x0000F0DC, &gpio->gpgup); - writel(0x0028AAAA, &gpio->gphcon); - writel(0x00000656, &gpio->gphup); - - /* setup correct IRQ modes for NIC (rising edge mode) */ - writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); - - /* select USB port 2 to be host or device (setup as host for now) */ - writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); - - return 0; -} - -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x30000100; - - icache_enable(); - dcache_enable(); - - return 0; -} - -/* - * Get some Board/PLD Info - */ - -static u8 get_pld_reg(enum vcma9_pld_regs reg) -{ - return readb(VCMA9_PLD_BASE + reg); -} - -static u8 get_pld_version(void) -{ - return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; -} - -static u8 get_pld_revision(void) -{ - return get_pld_reg(VCMA9_PLD_ID) & 0x0F; -} - -static uchar get_board_pcb(void) -{ - return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; -} - -static u8 get_nr_chips(void) -{ - switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { - case 0: return 4; - case 1: return 1; - case 2: return 2; - default: return 0; - } -} - -static ulong get_chip_size(void) -{ - switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { - case 0: return 16 * (1024*1024); - case 1: return 32 * (1024*1024); - case 2: return 8 * (1024*1024); - case 3: return 8 * (1024*1024); - default: return 0; - } -} - -static const char *get_chip_geom(void) -{ - switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { - case 0: return "4Mx8x4"; - case 1: return "8Mx8x4"; - case 2: return "2Mx8x4"; - case 3: return "4Mx8x2"; - default: return "unknown"; - } -} - -static void vcma9_show_info(char *board_name, char *serial) -{ - printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, - get_board_pcb(), get_pld_version(), get_pld_revision()); - printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_chip_size() * get_nr_chips(); - return 0; -} - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - char s[50]; - int i; - backup_t *b = (backup_t *) s; - - i = getenv_f("serial#", s, 32); - if ((i < 0) || strncmp (s, "VCMA9", 5)) { - get_backup_values (b); - if (strncmp (b->signature, "MPL\0", 4) != 0) { - puts ("### No HW ID - assuming VCMA9"); - } else { - b->serial_name[5] = 0; - vcma9_show_info(b->serial_name, &b->serial_name[6]); - } - } else { - s[5] = 0; - vcma9_show_info(s, &s[6]); - } - - return 0; -} - -int board_late_init(void) -{ - /* - * check if environment is healthy, otherwise restore values - * from shadow copy - */ - check_env(); - return 0; -} - -void vcma9_print_info(void) -{ - char *s = getenv("serial#"); - - if (!s) { - puts ("### No HW ID - assuming VCMA9"); - } else { - s[5] = 0; - vcma9_show_info(s, &s[6]); - } -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif - -/* - * Hardcoded flash setup: - * Flash 0 is a non-CFI AMD AM29F400BB flash. - */ -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; -} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h deleted file mode 100644 index c585c8e..0000000 --- a/board/mpl/vcma9/vcma9.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2002, 2003 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - /**************************************************************************** - * Global routines used for VCMA9 - *****************************************************************************/ - -#include <asm/arch/s3c24x0_cpu.h> - -extern void vcma9_print_info(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, - int argc, char *const argv[]); - -/* VCMA9 PLD registers */ -enum vcma9_pld_regs { - VCMA9_PLD_ID, - VCMA9_PLD_NIC, - VCMA9_PLD_CAN, - VCMA9_PLD_MISC, - VCMA9_PLD_GPCD, - VCMA9_PLD_BOARD, - VCMA9_PLD_SDRAM -}; - -#define VCMA9_PLD_BASE (0x2C000100) diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig deleted file mode 100644 index e464c21..0000000 --- a/configs/VCMA9_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VCMA9=y -CONFIG_IDENT_STRING="\n(c) 2003 - 2011 by MPL AG Switzerland, MEV-10080-001 unstable" -CONFIG_BOOTDELAY=5 -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="VCMA9 # " -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_UBI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h deleted file mode 100644 index bb26261..0000000 --- a/include/configs/VCMA9.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2002, 2003 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * Gary Jennejohn garyj@denx.de - * David Mueller d.mueller@elsoft.ch - * - * Configuation settings for the MPL VCMA9 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define MACH_TYPE_MPL_VCMA9 227 - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SYS_THUMB_BUILD - -#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ -#define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ - -#define CONFIG_SYS_TEXT_BASE 0x0 - -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - -/* input clock of PLL (VCMA9 has 12MHz input clock) */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BSP -#define CONFIG_CMD_NAND - -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_CMDLINE_EDITING - -/* - * I2C stuff: - * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at - * address 0x50 with 16bit addressing - */ -#define CONFIG_SYS_I2C - -/* we use the built-in I2C controller */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -/* use EEPROM for environment vars */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -/* environment starts at offset 0 */ -#define CONFIG_ENV_OFFSET 0x000 -/* 2KB should be more than enough */ -#define CONFIG_ENV_SIZE 0x800 - -#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -/* 64 bytes page write mode on 24C256 */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * Hardware drivers - */ -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 - -/* - * select serial console configuration - */ -#define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ - -/* USB support (currently only works with D-cache off) */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_OHCI_S3C24XX -#define CONFIG_DOS_PARTITION - -/* Enable needed helper functions */ - -/* RTC */ -#define CONFIG_RTC_S3C24X0 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_RESET_TO_RETRY - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 - -#if defined(CONFIG_CMD_KGDB) -/* speed to run kgdb serial port */ -#define CONFIG_KGDB_BAUDRATE 115200 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ - -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_LOAD_ADDR 0x30800000 - -/* we configure PWM Timer 4 to 1ms 1000Hz */ - -/* support additional compression methods */ -#define CONFIG_BZIP2 -#define CONFIG_LZO -#define CONFIG_LZMA - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/* FLASH and environment organization */ - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT (19) - -/* - * Size of malloc() pool - * BZIP2 / LZO / LZMA need a lot of RAM - */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -/* NAND configuration */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_S3C2410 -#define CONFIG_SYS_S3C2410_NAND_HWECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x4E000000 -#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING -#define CONFIG_S3C24XX_TACLS 1 -#define CONFIG_S3C24XX_TWRPH0 5 -#define CONFIG_S3C24XX_TWRPH1 3 -#endif - -#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 - -/* File system */ -#define CONFIG_CMD_UBIFS -#define CONFIG_CMD_JFFS2 -#define CONFIG_YAFFS2 -#define CONFIG_RBTREE -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_LZO - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_BOARD_EARLY_INIT_F - -#endif /* __CONFIG_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a573210..208c6e4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -8229,7 +8229,6 @@ CONFIG_U_QE CONFIG_V38B CONFIG_VAL CONFIG_VAR_SIZE_SPL -CONFIG_VCMA9 CONFIG_VCO_HZ CONFIG_VCO_MULT CONFIG_VCT_NOR

This is not used by any boards. Drop it.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v2: - Drop the pxa patches since it is now converted

doc/driver-model/serial-howto.txt | 1 - drivers/serial/Makefile | 1 - drivers/serial/serial_s3c24x0.c | 208 -------------------------------------- scripts/config_whitelist.txt | 1 - 4 files changed, 211 deletions(-) delete mode 100644 drivers/serial/serial_s3c24x0.c

diff --git a/doc/driver-model/serial-howto.txt b/doc/driver-model/serial-howto.txt index 3720274..a0df9a7 100644 --- a/doc/driver-model/serial-howto.txt +++ b/doc/driver-model/serial-howto.txt @@ -6,7 +6,6 @@ ones remain:

serial_bfin.c serial_pxa.c - serial_s3c24x0.c

The deadline for this work was the end of January 2016. If no one steps forward to convert these, at some point there may come a patch to remove them! diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 21b1292..8430668 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_MESON_SERIAL) += serial_meson.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o endif -obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c deleted file mode 100644 index 0f0878a..0000000 --- a/drivers/serial/serial_s3c24x0.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, garyj@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/compiler.h> -#include <asm/arch/s3c24x0_cpu.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SERIAL1 -#define UART_NR S3C24X0_UART0 - -#elif defined(CONFIG_SERIAL2) -#define UART_NR S3C24X0_UART1 - -#elif defined(CONFIG_SERIAL3) -#define UART_NR S3C24X0_UART2 - -#else -#error "Bad: you didn't configure serial ..." -#endif - -#include <asm/io.h> -#include <serial.h> - -/* Multi serial device functions */ -#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \ - int s3serial##port##_init(void) \ - { \ - return serial_init_dev(port); \ - } \ - void s3serial##port##_setbrg(void) \ - { \ - serial_setbrg_dev(port); \ - } \ - int s3serial##port##_getc(void) \ - { \ - return serial_getc_dev(port); \ - } \ - int s3serial##port##_tstc(void) \ - { \ - return serial_tstc_dev(port); \ - } \ - void s3serial##port##_putc(const char c) \ - { \ - serial_putc_dev(port, c); \ - } \ - void s3serial##port##_puts(const char *s) \ - { \ - serial_puts_dev(port, s); \ - } - -#define INIT_S3C_SERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = s3serial##port##_init, \ - .stop = NULL, \ - .setbrg = s3serial##port##_setbrg, \ - .getc = s3serial##port##_getc, \ - .tstc = s3serial##port##_tstc, \ - .putc = s3serial##port##_putc, \ - .puts = s3serial##port##_puts, \ -} - -static void _serial_setbrg(const int dev_index) -{ - struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - unsigned int reg = 0; - int i; - - /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ - reg = get_PCLK() / (16 * gd->baudrate) - 1; - - writel(reg, &uart->ubrdiv); - for (i = 0; i < 100; i++) - /* Delay */ ; -} - -static inline void serial_setbrg_dev(unsigned int dev_index) -{ - _serial_setbrg(dev_index); -} - -/* Initialise the serial port. The settings are always 8 data bits, no parity, - * 1 stop bit, no start bits. - */ -static int serial_init_dev(const int dev_index) -{ - struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - - /* FIFO enable, Tx/Rx FIFO clear */ - writel(0x07, &uart->ufcon); - writel(0x0, &uart->umcon); - - /* Normal,No parity,1 stop,8 bit */ - writel(0x3, &uart->ulcon); - /* - * tx=level,rx=edge,disable timeout int.,enable rx error int., - * normal,interrupt or polling - */ - writel(0x245, &uart->ucon); - - _serial_setbrg(dev_index); - - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int _serial_getc(const int dev_index) -{ - struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - - while (!(readl(&uart->utrstat) & 0x1)) - /* wait for character to arrive */ ; - - return readb(&uart->urxh) & 0xff; -} - -static inline int serial_getc_dev(unsigned int dev_index) -{ - return _serial_getc(dev_index); -} - -/* - * Output a single byte to the serial port. - */ -static void _serial_putc(const char c, const int dev_index) -{ - struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - - /* If \n, also do \r */ - if (c == '\n') - serial_putc('\r'); - - while (!(readl(&uart->utrstat) & 0x2)) - /* wait for room in the tx FIFO */ ; - - writeb(c, &uart->utxh); -} - -static inline void serial_putc_dev(unsigned int dev_index, const char c) -{ - _serial_putc(c, dev_index); -} - -/* - * Test whether a character is in the RX buffer - */ -static int _serial_tstc(const int dev_index) -{ - struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - - return readl(&uart->utrstat) & 0x1; -} - -static inline int serial_tstc_dev(unsigned int dev_index) -{ - return _serial_tstc(dev_index); -} - -static void _serial_puts(const char *s, const int dev_index) -{ - while (*s) { - _serial_putc(*s++, dev_index); - } -} - -static inline void serial_puts_dev(int dev_index, const char *s) -{ - _serial_puts(s, dev_index); -} - -DECLARE_S3C_SERIAL_FUNCTIONS(0); -struct serial_device s3c24xx_serial0_device = -INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0"); -DECLARE_S3C_SERIAL_FUNCTIONS(1); -struct serial_device s3c24xx_serial1_device = -INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1"); -DECLARE_S3C_SERIAL_FUNCTIONS(2); -struct serial_device s3c24xx_serial2_device = -INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2"); - -__weak struct serial_device *default_serial_console(void) -{ -#if defined(CONFIG_SERIAL1) - return &s3c24xx_serial0_device; -#elif defined(CONFIG_SERIAL2) - return &s3c24xx_serial1_device; -#elif defined(CONFIG_SERIAL3) - return &s3c24xx_serial2_device; -#else -#error "CONFIG_SERIAL? missing." -#endif -} - -void s3c24xx_serial_initialize(void) -{ - serial_register(&s3c24xx_serial0_device); - serial_register(&s3c24xx_serial1_device); - serial_register(&s3c24xx_serial2_device); -} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 208c6e4..6cb836e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3879,7 +3879,6 @@ CONFIG_S3C2410_NAND_BBT CONFIG_S3C2410_NAND_HWECC CONFIG_S3C2440 CONFIG_S3C24X0 -CONFIG_S3C24X0_SERIAL CONFIG_S3C24XX_CUSTOM_NAND_TIMING CONFIG_S3C24XX_TACLS CONFIG_S3C24XX_TWRPH0