On Mon, Jan 14, 2019 at 06:11:04PM +0530, Amit Singh Tomar wrote:

This adds memory regions needed to setup MMU for actions S900 and S700 SoCs.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v1:

• compile sysmap-owl.c against CONFIG_ARM64 now.

---

arch/arm/mach-owl/Makefile | 3 ++- arch/arm/mach-owl/sysmap-owl.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mach-owl/sysmap-s900.c | 32 -------------------------------- 3 files changed, 34 insertions(+), 33 deletions(-) create mode 100644 arch/arm/mach-owl/sysmap-owl.c delete mode 100644 arch/arm/mach-owl/sysmap-s900.c

diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile index 0b181c6..b17fc14 100644 --- a/arch/arm/mach-owl/Makefile +++ b/arch/arm/mach-owl/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+

obj-y += soc.o -obj-y += sysmap-s900.o +obj-$(CONFIG_ARM64) += sysmap-owl.o

diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c new file mode 100644 index 0000000..9d30759 --- /dev/null +++ b/arch/arm/mach-owl/sysmap-owl.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Memory map for Actions Semi S900/S700 based SoCs.

Actions Semi Owl series SoCs?

With this,

Reviewed-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org

Thanks, Mani

• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h> +#include <asm/armv8/mmu.h>

+static struct mm_region owl_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

+};

+struct mm_region *mem_map = owl_mem_map; diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c deleted file mode 100644 index f78b639..0000000 --- a/arch/arm/mach-owl/sysmap-s900.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 Memory map
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region s900_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

-};

-struct mm_region *mem_map = s900_mem_map;

2.7.4

On 14/01/2019 12:41, Amit Singh Tomar wrote:

Hi,

CMU block on most of the actions SoC seems to be identical(at-least, S900 and S700).

Actually they are not. Not even for the small subset that we implement here. Try "diff -wu arch/arm/include/asm/arch-owl/regs_s*.h" for a start, plus the differences in the #ifdefs below.

This patch converts S900 clock driver to something common that can be used for other SoCs, for instance S700(most of clk registres are same).

I am not sure this is a viable approach, really. The driver claims to support both SoC's via their compatible strings, but in fact is just implementing the one configured via Kconfig. While we should be able to easily replace the #ifdefs with something checking the .data member associated with the respective .compatible string, it gets hairy with the #defines in regs_s[79]00.h. So either it's two different .c files, with the register definitions in there, or we change the CMU_* defines to CMU_S[79]00_* and include both.

Maybe you could try this and report how it looks like? If half of the file is within if-else statements, separating is problem more worthwhile. Mani, you mentioned the S500, I guess this is even more different, right? Which would point into the "separate files" direction.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v1:

• Moved CLK and CLK_OWL symbols from defconfig to arch/arm/Kconfig.

---

arch/arm/Kconfig | 2 + arch/arm/include/asm/arch-owl/clk_owl.h | 61 +++++++++++++ arch/arm/include/asm/arch-owl/clk_s900.h | 57 ------------- arch/arm/include/asm/arch-owl/regs_s700.h | 56 ++++++++++++

This file doesn't define an interface, so should live in the drivers/clk/owl directory. Same with the regs_s900.h.

configs/bubblegum_96_defconfig | 3 - drivers/clk/owl/Kconfig | 10 +-- drivers/clk/owl/Makefile | 2 +- drivers/clk/owl/clk_owl.c | 132 ++++++++++++++++++++++++++++ drivers/clk/owl/clk_s900.c | 137 ------------------------------ 9 files changed, 255 insertions(+), 205 deletions(-) create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 drivers/clk/owl/clk_owl.c delete mode 100644 drivers/clk/owl/clk_s900.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1a2e561..1daf3bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -764,6 +764,8 @@ config ARCH_OWL select DM select DM_SERIAL select OWL_SERIAL

• select CLK
• select CLK_OWL select OF_CONTROL imply CMD_DM

diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h b/arch/arm/include/asm/arch-owl/clk_owl.h new file mode 100644 index 0000000..962badd --- /dev/null +++ b/arch/arm/include/asm/arch-owl/clk_owl.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi SoCs Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _OWL_CLK_H_ +#define _OWL_CLK_H_

+#include <clk-uclass.h>

+struct owl_clk_priv {

• phys_addr_t base;

+};

+/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0)

+/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24)

+/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6)

+/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

+/* DEVCLKEN1 register definitions */ +#if defined(CONFIG_MACH_S900)

Meh.

+#define CMU_DEVCLKEN1_UART5 BIT(21) +#elif defined(CONFIG_MACH_S700) +#define CMU_DEVCLKEN1_UART3 BIT(11) +#endif

+#define PLL_STABILITY_WAIT_US 50

+#endif diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h deleted file mode 100644 index 88e88f7..0000000 --- a/arch/arm/include/asm/arch-owl/clk_s900.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Actions Semi S900 Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#ifndef _OWL_CLK_S900_H_ -#define _OWL_CLK_S900_H_

-#include <clk-uclass.h>

-struct owl_clk_priv {

• phys_addr_t base;

-};

-/* BUSCLK register definitions */ -#define CMU_PDBGDIV_8 7 -#define CMU_PDBGDIV_SHIFT 26 -#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) -#define CMU_PERDIV_8 7 -#define CMU_PERDIV_SHIFT 20 -#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) -#define CMU_NOCDIV_2 1 -#define CMU_NOCDIV_SHIFT 19 -#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) -#define CMU_DMMCLK_SRC_APLL 2 -#define CMU_DMMCLK_SRC_SHIFT 10 -#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) -#define CMU_APBCLK_DIV BIT(8) -#define CMU_NOCCLK_SRC BIT(7) -#define CMU_AHBCLK_DIV BIT(4) -#define CMU_CORECLK_MASK 3 -#define CMU_CORECLK_CPLL BIT(1) -#define CMU_CORECLK_HOSC BIT(0)

-/* COREPLL register definitions */ -#define CMU_COREPLL_EN BIT(9) -#define CMU_COREPLL_HOSC_EN BIT(8) -#define CMU_COREPLL_OUT (1104 / 24)

-/* DEVPLL register definitions */ -#define CMU_DEVPLL_CLK BIT(12) -#define CMU_DEVPLL_EN BIT(8) -#define CMU_DEVPLL_OUT (660 / 6)

-/* UARTCLK register definitions */ -#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

-/* DEVCLKEN1 register definitions */ -#define CMU_DEVCLKEN1_UART5 BIT(21)

-#define PLL_STABILITY_WAIT_US 50

-#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h new file mode 100644 index 0000000..a0bd737 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi S700 Register Definitions
• */

+#ifndef _OWL_REGS_S700_H_ +#define _OWL_REGS_S700_H_

+#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSIPLLCLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_SICLK (0x0034) +#define CMU_BUSCLK1 (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_UART3CLK (0x0068) +#define CMU_UART4CLK (0x006C) +#define CMU_UART5CLK (0x0070) +#define CMU_UART6CLK (0x0074) +#define CMU_PWM0CLK (0x0078) +#define CMU_PWM1CLK (0x007C) +#define CMU_PWM2CLK (0x0080) +#define CMU_PWM3CLK (0x0084) +#define CMU_PWM4CLK (0x0088) +#define CMU_PWM5CLK (0x008C) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_USBPLL (0x00B0) +#define CMU_ETHERNETPLL (0x00B4) +#define CMU_CVBSPLL (0x00B8) +#define CMU_SSTSCLK (0x00C0)

+#endif diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index d1f403f..6803f04 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -15,6 +15,3 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" -CONFIG_CLK=y -CONFIG_CLK_OWL=y -CONFIG_CLK_S900=y diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index 661f198..dabac85 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -1,12 +1,8 @@ config CLK_OWL bool "Actions Semi OWL clock drivers"

•    depends on CLK && ARCH_OWL
  

•    depends on CLK && ARCH_OWL && ARM64
  

Why this change? Is there a 32-bit config that would break? I think even supporting the S500 would not work like this.

     help
       Enable support for clock managemet unit present in Actions Semi

•  OWL SoCs.
  

•  S900/S700 SoCs.
  

-config CLK_S900

•    bool "Actions Semi S900 clock driver"
  

•    depends on CLK_OWL && ARM64
  

•    help
  

•      Enable support for the clocks in Actions Semi S900 SoC.
  

diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile index 63ab573..5218b6b 100644 --- a/drivers/clk/owl/Makefile +++ b/drivers/clk/owl/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-$(CONFIG_CLK_S900) += clk_s900.o +obj-$(CONFIG_CLK_OWL) += clk_owl.o diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c new file mode 100644 index 0000000..f8d2102 --- /dev/null +++ b/drivers/clk/owl/clk_owl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Common clock driver for Actions Semi SoCs.
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h> +#include <dm.h> +#include <asm/arch-owl/clk_owl.h> +#include <asm/io.h> +#if defined(CONFIG_MACH_S900) +#include <asm/arch-owl/regs_s900.h> +#elif defined(CONFIG_MACH_S700) +#include <asm/arch-owl/regs_s700.h> +#endif

+void owl_clk_init(struct owl_clk_priv *priv) +{

• u32 bus_clk = 0, core_pll, dev_pll;

+#if defined(CONFIG_MACH_S900)

• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);

+#endif

• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

+}

+int owl_clk_enable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);

+#if defined(CONFIG_MACH_S900)

This is somewhat obsoleted by my above note, but this changes the code, so that owl_clk_enable/disable *always* affects the UART clock, regardless of the struct clk passed in. You would at least need to check for the clk->id.

• /* Source HOSC for UART5 interface */

•    clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
  

•    /* Enable UART5 interface clock */
  

•    setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

+#elif defined(CONFIG_MACH_S700)

•    /* Source HOSC for UART3 interface */
  

•    clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
  

•    /* Enable UART3 interface clock */
  

•    setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
  

+#endif

• return 0;

+}

+int owl_clk_disable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);

+#if defined(CONFIG_MACH_S900)

•    /* Disable UART5 interface clock */
  

•    clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

+#elif defined(CONFIG_MACH_S700)

• /* Disable UART3 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);

+#endif

• return 0;

+}

+static int owl_clk_probe(struct udevice *dev) +{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

+}

+static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

+};

+static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { .compatible = "actions,s700-cmu" },

For the records: This is dodgy part. You claim to support both devices, but actually don't.

Can you try to add a .data member with the clock type, then replace the #ifdef's above with comparing this type? That would be much cleaner, still keep the code relatively small and simple.

• { }

+};

+U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

+}; diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c deleted file mode 100644 index a7c15d2..0000000 --- a/drivers/clk/owl/clk_s900.c

So actually this file doesn't look too big, so I wonder if we could live with two separate files for S700 and S900.

Cheers, Andre.

+++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 clock driver
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <dm.h> -#include <asm/arch-owl/clk_s900.h> -#include <asm/arch-owl/regs_s900.h> -#include <asm/io.h>

-#include <dt-bindings/clock/s900_cmu.h>

-void owl_clk_init(struct owl_clk_priv *priv) -{

• u32 bus_clk = 0, core_pll, dev_pll;
• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);
• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

-}

-void owl_uart_clk_enable(struct owl_clk_priv *priv) -{

• /* Source HOSC for UART5 interface */
• clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
• /* Enable UART5 interface clock */
• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-void owl_uart_clk_disable(struct owl_clk_priv *priv) -{

• /* Disable UART5 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-int owl_clk_enable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_enable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-int owl_clk_disable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_disable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-static int owl_clk_probe(struct udevice *dev) -{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

-}

-static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

-};

-static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { }

-};

-U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

-};

On Thu, 17 Jan 2019 20:45:44 +0530 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org wrote:

Hi,

On Tue, Jan 15, 2019 at 12:43:36AM +0000, André Przywara wrote:

...

On 14/01/2019 12:41, Amit Singh Tomar wrote:

Hi,

...

CMU block on most of the actions SoC seems to be identical(at-least, S900 and S700).

Actually they are not. Not even for the small subset that we implement here. Try "diff -wu arch/arm/include/asm/arch-owl/regs_s*.h" for a start, plus the differences in the #ifdefs below.

...

This patch converts S900 clock driver to something common that can be used for other SoCs, for instance S700(most of clk registres are same).

I am not sure this is a viable approach, really. The driver claims to support both SoC's via their compatible strings, but in fact is just implementing the one configured via Kconfig. While we should be able to easily replace the #ifdefs with something checking the .data member associated with the respective .compatible string, it gets hairy with the #defines in regs_s[79]00.h. So either it's two different .c files, with the register definitions in there, or we change the CMU_* defines to CMU_S[79]00_* and include both.

Maybe you could try this and report how it looks like? If half of the file is within if-else statements, separating is problem more worthwhile. Mani, you mentioned the S500, I guess this is even more different, right? Which would point into the "separate files" direction.

S500 is different in terms of the clock initializations. Ideally we should have a minimal set of common clk driver like in Linux which I authored. Otherwise, we should move forward with individual clk files for each SoC. Having #ifdef's will definitely make the code look messy.

Yeah, that is probably the right way to go, especially when it comes to clocks like MMC, which are probably similar in their internal workings, but are at different addresses or use different offsets. Problem is we don't know this yet for sure, and Amit has a point that the files are indeed very similar right now.

So as a quick measure to ensure correctness, but still keep it simple, I was thinking about keeping most of the patch as it is (still addressing my previous comments) and just protect the compatible strings below with MACH_S[79]00 ifdefs, so that both SoCs share the file, but compile to different drivers supporting only one compatible (due to the different reg_sx00.h and the #ifdef protected parts). This would arguably be the only difference between the s700 and s900 U-Boot binaries, but it's still a good start to get this SoC supported in the first place. We can always rework the clocks once we get more users (both clock-wise and SoC wise) and see what we really need and how much we can share.

Cheers, Andre.

...

...

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v1:

• Moved CLK and CLK_OWL symbols from defconfig to

arch/arm/Kconfig. --- arch/arm/Kconfig | 2 + arch/arm/include/asm/arch-owl/clk_owl.h | 61 +++++++++++++ arch/arm/include/asm/arch-owl/clk_s900.h | 57 ------------- arch/arm/include/asm/arch-owl/regs_s700.h | 56 ++++++++++++

This file doesn't define an interface, so should live in the drivers/clk/owl directory. Same with the regs_s900.h.

...

configs/bubblegum_96_defconfig | 3 - drivers/clk/owl/Kconfig | 10 +-- drivers/clk/owl/Makefile | 2 +- drivers/clk/owl/clk_owl.c | 132 ++++++++++++++++++++++++++++ drivers/clk/owl/clk_s900.c | 137 ------------------------------ 9 files changed, 255 insertions(+), 205 deletions(-) create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 drivers/clk/owl/clk_owl.c delete mode 100644 drivers/clk/owl/clk_s900.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1a2e561..1daf3bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -764,6 +764,8 @@ config ARCH_OWL select DM select DM_SERIAL select OWL_SERIAL

• select CLK
• select CLK_OWL select OF_CONTROL imply CMD_DM

diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h b/arch/arm/include/asm/arch-owl/clk_owl.h new file mode 100644 index 0000000..962badd --- /dev/null +++ b/arch/arm/include/asm/arch-owl/clk_owl.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi SoCs Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

+#ifndef _OWL_CLK_H_ +#define _OWL_CLK_H_

+#include <clk-uclass.h>

+struct owl_clk_priv {

• phys_addr_t base;

+};

+/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0)

+/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24)

+/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6)

+/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

+/* DEVCLKEN1 register definitions */ +#if defined(CONFIG_MACH_S900)

Meh.

...

+#define CMU_DEVCLKEN1_UART5 BIT(21) +#elif defined(CONFIG_MACH_S700) +#define CMU_DEVCLKEN1_UART3 BIT(11) +#endif

+#define PLL_STABILITY_WAIT_US 50

+#endif diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h deleted file mode 100644 index 88e88f7..0000000 --- a/arch/arm/include/asm/arch-owl/clk_s900.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Actions Semi S900 Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

-#ifndef _OWL_CLK_S900_H_ -#define _OWL_CLK_S900_H_

-#include <clk-uclass.h>

-struct owl_clk_priv {

• phys_addr_t base;

-};

-/* BUSCLK register definitions */ -#define CMU_PDBGDIV_8 7 -#define CMU_PDBGDIV_SHIFT 26 -#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) -#define CMU_PERDIV_8 7 -#define CMU_PERDIV_SHIFT 20 -#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) -#define CMU_NOCDIV_2 1 -#define CMU_NOCDIV_SHIFT 19 -#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) -#define CMU_DMMCLK_SRC_APLL 2 -#define CMU_DMMCLK_SRC_SHIFT 10 -#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) -#define CMU_APBCLK_DIV BIT(8) -#define CMU_NOCCLK_SRC BIT(7) -#define CMU_AHBCLK_DIV BIT(4) -#define CMU_CORECLK_MASK 3 -#define CMU_CORECLK_CPLL BIT(1) -#define CMU_CORECLK_HOSC BIT(0)

-/* COREPLL register definitions */ -#define CMU_COREPLL_EN BIT(9) -#define CMU_COREPLL_HOSC_EN BIT(8) -#define CMU_COREPLL_OUT (1104 / 24)

-/* DEVPLL register definitions */ -#define CMU_DEVPLL_CLK BIT(12) -#define CMU_DEVPLL_EN BIT(8) -#define CMU_DEVPLL_OUT (660 / 6)

-/* UARTCLK register definitions */ -#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

-/* DEVCLKEN1 register definitions */ -#define CMU_DEVCLKEN1_UART5 BIT(21)

-#define PLL_STABILITY_WAIT_US 50

-#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h new file mode 100644 index 0000000..a0bd737 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi S700 Register Definitions
• */

+#ifndef _OWL_REGS_S700_H_ +#define _OWL_REGS_S700_H_

+#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSIPLLCLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_SICLK (0x0034) +#define CMU_BUSCLK1 (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_UART3CLK (0x0068) +#define CMU_UART4CLK (0x006C) +#define CMU_UART5CLK (0x0070) +#define CMU_UART6CLK (0x0074) +#define CMU_PWM0CLK (0x0078) +#define CMU_PWM1CLK (0x007C) +#define CMU_PWM2CLK (0x0080) +#define CMU_PWM3CLK (0x0084) +#define CMU_PWM4CLK (0x0088) +#define CMU_PWM5CLK (0x008C) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_USBPLL (0x00B0) +#define CMU_ETHERNETPLL (0x00B4) +#define CMU_CVBSPLL (0x00B8) +#define CMU_SSTSCLK (0x00C0)

+#endif diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index d1f403f..6803f04 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -15,6 +15,3 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" -CONFIG_CLK=y -CONFIG_CLK_OWL=y -CONFIG_CLK_S900=y diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index 661f198..dabac85 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -1,12 +1,8 @@ config CLK_OWL bool "Actions Semi OWL clock drivers"

•    depends on CLK && ARCH_OWL
  

•    depends on CLK && ARCH_OWL && ARM64  
  

Why this change? Is there a 32-bit config that would break? I think even supporting the S500 would not work like this.

...

     help
       Enable support for clock managemet unit present in

Actions Semi

•  OWL SoCs.
  

•  S900/S700 SoCs.
  

-config CLK_S900

•    bool "Actions Semi S900 clock driver"
  

•    depends on CLK_OWL && ARM64
  

•    help
  

•      Enable support for the clocks in Actions Semi S900 SoC.
  

diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile index 63ab573..5218b6b 100644 --- a/drivers/clk/owl/Makefile +++ b/drivers/clk/owl/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-$(CONFIG_CLK_S900) += clk_s900.o +obj-$(CONFIG_CLK_OWL) += clk_owl.o diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c new file mode 100644 index 0000000..f8d2102 --- /dev/null +++ b/drivers/clk/owl/clk_owl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Common clock driver for Actions Semi SoCs.
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

+#include <common.h> +#include <dm.h> +#include <asm/arch-owl/clk_owl.h> +#include <asm/io.h> +#if defined(CONFIG_MACH_S900) +#include <asm/arch-owl/regs_s900.h> +#elif defined(CONFIG_MACH_S700) +#include <asm/arch-owl/regs_s700.h> +#endif

+void owl_clk_init(struct owl_clk_priv *priv) +{

• u32 bus_clk = 0, core_pll, dev_pll;

+#if defined(CONFIG_MACH_S900)

• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);

+#endif

• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV |

CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV |
  

CMU_AHBCLK_DIV |

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN |

CMU_COREPLL_OUT);

• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK,

CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

+}

+int owl_clk_enable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);

+#if defined(CONFIG_MACH_S900)

This is somewhat obsoleted by my above note, but this changes the code, so that owl_clk_enable/disable *always* affects the UART clock, regardless of the struct clk passed in. You would at least need to check for the clk->id.

...

• /* Source HOSC for UART5 interface */

•    clrbits_le32(priv->base + CMU_UART5CLK,
  

CMU_UARTCLK_SRC_DEVPLL); +

•    /* Enable UART5 interface clock */
  

•    setbits_le32(priv->base + CMU_DEVCLKEN1,
  

CMU_DEVCLKEN1_UART5); +#elif defined(CONFIG_MACH_S700)

•    /* Source HOSC for UART3 interface */
  

•    clrbits_le32(priv->base + CMU_UART3CLK,
  

CMU_UARTCLK_SRC_DEVPLL); +

•    /* Enable UART3 interface clock */
  

•    setbits_le32(priv->base + CMU_DEVCLKEN1,
  

CMU_DEVCLKEN1_UART3); +#endif

• return 0;

+}

+int owl_clk_disable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);

+#if defined(CONFIG_MACH_S900)

•    /* Disable UART5 interface clock */
  

•    clrbits_le32(priv->base + CMU_DEVCLKEN1,
  

CMU_DEVCLKEN1_UART5); +#elif defined(CONFIG_MACH_S700)

• /* Disable UART3 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1,

CMU_DEVCLKEN1_UART3); +#endif

• return 0;

+}

+static int owl_clk_probe(struct udevice *dev) +{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

+}

+static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

+};

+static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { .compatible = "actions,s700-cmu" },

For the records: This is dodgy part. You claim to support both devices, but actually don't.

Can you try to add a .data member with the clock type, then replace the #ifdef's above with comparing this type? That would be much cleaner, still keep the code relatively small and simple.

...

• { }

+};

+U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

+}; diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c deleted file mode 100644 index a7c15d2..0000000 --- a/drivers/clk/owl/clk_s900.c

So actually this file doesn't look too big, so I wonder if we could live with two separate files for S700 and S900.

Cheers, Andre.

...

+++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 clock driver
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

-#include <common.h> -#include <dm.h> -#include <asm/arch-owl/clk_s900.h> -#include <asm/arch-owl/regs_s900.h> -#include <asm/io.h>

-#include <dt-bindings/clock/s900_cmu.h>

-void owl_clk_init(struct owl_clk_priv *priv) -{

• u32 bus_clk = 0, core_pll, dev_pll;
• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);
• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV |

CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV |
  

CMU_AHBCLK_DIV |

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN |

CMU_COREPLL_OUT);

• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK,

CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

-}

-void owl_uart_clk_enable(struct owl_clk_priv *priv) -{

• /* Source HOSC for UART5 interface */
• clrbits_le32(priv->base + CMU_UART5CLK,

CMU_UARTCLK_SRC_DEVPLL); -

• /* Enable UART5 interface clock */
• setbits_le32(priv->base + CMU_DEVCLKEN1,

CMU_DEVCLKEN1_UART5); -}

-void owl_uart_clk_disable(struct owl_clk_priv *priv) -{

• /* Disable UART5 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1,

CMU_DEVCLKEN1_UART5); -}

-int owl_clk_enable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_enable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-int owl_clk_disable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_disable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-static int owl_clk_probe(struct udevice *dev) -{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

-}

-static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

-};

-static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { }

-};

-U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

-};

On Mon, Jan 14, 2019 at 06:11:06PM +0530, Amit Singh Tomar wrote:

This patch adds basic support for Actions Semi based S700 SoC, which is driven by common owl framework.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v1:

• S700 specific changes are factored out here from patch 1 of 9.

---

arch/arm/mach-owl/Kconfig | 6 ++++++ include/configs/s700.h | 15 +++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 include/configs/s700.h

diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index 5eb93c9..d05cc68 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -8,13 +8,19 @@ config MACH_S900 bool "Actionss Semi S900" select ARM64

+config MACH_S700

•    bool "Actions Semi S700"
  

•    select ARM64
  

endchoice

config SYS_CONFIG_NAME default "s900" if MACH_S900

•    default "s700" if MACH_S700
  
  

config SYS_SOC default "s900" if MACH_S900

•    default "s700" if MACH_S700
  
  

config SYS_TEXT_BASE default 0x11000000 diff --git a/include/configs/s700.h b/include/configs/s700.h new file mode 100644 index 0000000..84f9174 --- /dev/null +++ b/include/configs/s700.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Board configuration file for Action semi s700

Please be consistent with naming conventions... Actions Semi S700 SoC.

Thanks, Mani

• */

+#ifndef _CONFIG_S700_H_ +#define _CONFIG_S700_H_

+/*

• • Include common owl configuration where most the settings are
• */

+#include <configs/owl-common.h>

+#endif

2.7.4

On Mon, Jan 14, 2019 at 6:46 AM Amit Singh Tomar amittomer25@gmail.com wrote:

This patch adds .dtsi file(sync with Linux 4.20) and required binding for S700 SoC that is a 64-bit Quad-core ARM Cortex-A53 cores.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v1: * Moved the u-boot specific changes to s700-u-boot.dtsi, now s700.dtsi is in complete sync with Linux 4.20.

---

arch/arm/dts/s700.dtsi | 190 +++++++++++++++++++++++++++ include/dt-bindings/clock/actions,s700-cmu.h | 118 +++++++++++++++++ 2 files changed, 308 insertions(+) create mode 100644 arch/arm/dts/s700.dtsi create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h

diff --git a/arch/arm/dts/s700.dtsi b/arch/arm/dts/s700.dtsi new file mode 100644 index 0000000..192c7b3 --- /dev/null +++ b/arch/arm/dts/s700.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2017 Andreas Färber
• */

+#include <dt-bindings/clock/actions,s700-cmu.h> +#include <dt-bindings/interrupt-controller/arm-gic.h>

+/ {

•   compatible = "actions,s700";
  

•   interrupt-parent = <&gic>;
  

•   #address-cells = <2>;
  

•   #size-cells = <2>;
  

•   cpus {
  

•           #address-cells = <2>;
  

•           #size-cells = <0>;
  

•           cpu0: cpu@0 {
  

•                   device_type = "cpu";
  

•                   compatible = "arm,cortex-a53", "arm,armv8";
  

Drop the 'arm,armv8'. This was used inconsistently and is in the process of being removed except for s/w models.

•                   reg = <0x0 0x0>;
  

•                   enable-method = "psci";
  

•           };
  

On 14/01/2019 12:41, Amit Singh Tomar wrote:

The Cubieboard is a single board computer containing a Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).

This patch adds respective defconfig alongwith device tree(sync with Linux 4.20).

This should come later in the series, as patch 8/9, just _after_ everything works. It compiles at this point, but you still need the next two patches for it to work.

The _defconfig is still a bit too crowded, but so is the S900 version, so:

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Reviewed-by: Andre Przywara andre.przywara@arm.com

Cheers, Andre.

---

Changes since v1:

• No changes.

---

arch/arm/dts/s700-cubieboard7.dts | 39 +++++++++++++++++++++++++++++++++++++++ configs/cubieboard7_defconfig | 16 ++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 arch/arm/dts/s700-cubieboard7.dts create mode 100644 configs/cubieboard7_defconfig

diff --git a/arch/arm/dts/s700-cubieboard7.dts b/arch/arm/dts/s700-cubieboard7.dts new file mode 100644 index 0000000..28f3f4a --- /dev/null +++ b/arch/arm/dts/s700-cubieboard7.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2017 Andreas Färber
• */

+/dts-v1/;

+#include "s700.dtsi"

+/ {

• compatible = "cubietech,cubieboard7", "actions,s700";
• model = "CubieBoard7";
• aliases {

• serial3 = &uart3;
  

• };
• chosen {

• stdout-path = "serial3:115200n8";
  

• };
• memory@0 {

• device_type = "memory";
  

• reg = <0x0 0x0 0x0 0x80000000>;
  

• };
• memory@1,e0000000 {

• device_type = "memory";
  

• reg = <0x1 0xe0000000 0x0 0x0>;
  

• };

+};

+&timer {

• clocks = <&hosc>;

+};

+&uart3 {

• status = "okay";

+}; diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig new file mode 100644 index 0000000..0459997 --- /dev/null +++ b/configs/cubieboard7_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_OWL=y +CONFIG_MACH_S700=y +CONFIG_IDENT_STRING="\ncubieboard7" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyOWL3,115200n8" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="U-Boot => " +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_TIMER=y +CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"

On Mon, Jan 14, 2019 at 06:11:08PM +0530, Amit Singh Tomar wrote:

The Cubieboard is a single board computer containing a Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).

This patch adds respective defconfig alongwith device tree(sync with Linux 4.20).

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Reviewed-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org

Thanks, Mani

---

Changes since v1:

• No changes.

---

arch/arm/dts/s700-cubieboard7.dts | 39 +++++++++++++++++++++++++++++++++++++++ configs/cubieboard7_defconfig | 16 ++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 arch/arm/dts/s700-cubieboard7.dts create mode 100644 configs/cubieboard7_defconfig

diff --git a/arch/arm/dts/s700-cubieboard7.dts b/arch/arm/dts/s700-cubieboard7.dts new file mode 100644 index 0000000..28f3f4a --- /dev/null +++ b/arch/arm/dts/s700-cubieboard7.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2017 Andreas Färber
• */

+/dts-v1/;

+#include "s700.dtsi"

+/ {

• compatible = "cubietech,cubieboard7", "actions,s700";
• model = "CubieBoard7";
• aliases {

• serial3 = &uart3;
  

• };
• chosen {

• stdout-path = "serial3:115200n8";
  

• };
• memory@0 {

• device_type = "memory";
  

• reg = <0x0 0x0 0x0 0x80000000>;
  

• };
• memory@1,e0000000 {

• device_type = "memory";
  

• reg = <0x1 0xe0000000 0x0 0x0>;
  

• };

+};

+&timer {

• clocks = <&hosc>;

+};

+&uart3 {

• status = "okay";

+}; diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig new file mode 100644 index 0000000..0459997 --- /dev/null +++ b/configs/cubieboard7_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_OWL=y +CONFIG_MACH_S700=y +CONFIG_IDENT_STRING="\ncubieboard7" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyOWL3,115200n8" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="U-Boot => " +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_TIMER=y

+CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"

2.7.4

On Mon, Jan 14, 2019 at 06:11:09PM +0530, Amit Singh Tomar wrote:

Devices like uart and clk are needed to be enabled before relocation. this patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v1:

• This is newly added file that was *not* present in v1 and contains u-boot specific changes.

---

arch/arm/dts/s700-u-boot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm/dts/s700-u-boot.dtsi

diff --git a/arch/arm/dts/s700-u-boot.dtsi b/arch/arm/dts/s700-u-boot.dtsi new file mode 100644 index 0000000..46e98de --- /dev/null +++ b/arch/arm/dts/s700-u-boot.dtsi @@ -0,0 +1,14 @@ +/{

Missing License and description.

Regards, Mani

• soc {

• u-boot,dm-pre-reloc;
  

• };

+};

+&uart3 {

• u-boot,dm-pre-reloc;

+};

+&cmu {

• u-boot,dm-pre-reloc;

+};

-- 2.7.4

On 14/01/2019 12:41, Amit Singh Tomar wrote:

UART controller present on S700 is compatible with existing S900 controller, this patch simply adds a proper compatible string so that owl uart driver can be reused for S700.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Reviewed-by: Andre Przywara andre.przywara@arm.com

Cheers, Andre

---

Changes since v1:

• No changes.

---

drivers/serial/serial_owl.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c index 7ead73e..76995bf 100644 --- a/drivers/serial/serial_owl.c +++ b/drivers/serial/serial_owl.c @@ -121,6 +121,7 @@ static const struct dm_serial_ops owl_serial_ops = {

static const struct udevice_id owl_serial_ids[] = { { .compatible = "actions,s900-serial" },

• { .compatible = "actions,owl-uart" }, { }

};

On Thu, 17 Jan 2019 21:09:45 +0530 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org wrote:

Hi,

[On top of Andre's review]

On Mon, Jan 14, 2019 at 06:11:03PM +0530, Amit Singh Tomar wrote:

...

This adds common arch owl support that can drive, 64-bits SoCs from Actions Semi.

Could be, "This commit adds common arch support for Actions Semi Owl series SoCs and removes the Bubblegum96 board files."

...

It also removes the Bubblegum specific board files.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v1:

• Moved S700 specific changes to patch 4 of 9.
  • Moved couple of symbols from defconfig to

arch/arm/Kconfig and platform owl Kconfig.

arch/arm/Kconfig | 3 +- arch/arm/mach-owl/Kconfig | 29 ++++++-------- arch/arm/mach-owl/Makefile | 1 + arch/arm/mach-owl/soc.c | 56 ++++++++++++++++++++++++++++ board/ucRobotics/bubblegum_96/Kconfig | 15 -------- board/ucRobotics/bubblegum_96/MAINTAINERS | 6 --- board/ucRobotics/bubblegum_96/Makefile | 3 -- board/ucRobotics/bubblegum_96/bubblegum_96.c | 56

---

configs/bubblegum_96_defconfig | 4 +- include/configs/bubblegum_96.h | 42 --------------------- include/configs/owl-common.h | 42 +++++++++++++++++++++ include/configs/s900.h | 18 +++++++++ 12 files changed, 131 insertions(+), 144 deletions(-) create mode 100644 arch/arm/mach-owl/soc.c delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS delete mode 100644 board/ucRobotics/bubblegum_96/Makefile delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c delete mode 100644 include/configs/bubblegum_96.h create mode 100644 include/configs/owl-common.h create mode 100644 include/configs/s900.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d6b1629..1a2e561 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -761,9 +761,9 @@ config ARCH_MX5

config ARCH_OWL bool "Actions Semi OWL SoCs"

• select ARM64 select DM select DM_SERIAL

• select OWL_SERIAL select OF_CONTROL imply CMD_DM

@@ -1555,7 +1555,6 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" -source "board/ucRobotics/bubblegum_96/Kconfig" source "board/birdland/bav335x/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/vscom/baltos/Kconfig" diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index 199e772..5eb93c9 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -1,27 +1,22 @@ if ARCH_OWL

-config SYS_SOC

• default "owl"

choice

•    prompt "Actions Semi OWL SoCs board select"
  

•    prompt "Actions Semi SoC Variant"  
  

We should explicitly say "Owl" series SoCs here.

...

     optional

-config TARGET_BUBBLEGUM_96

• bool "96Boards Bubblegum-96"
• help

•  Support for 96Boards Bubblegum-96. This board complies
  

with

•  96Board Consumer Edition Specification. Features:
  

•  - Actions Semi S900 SoC (4xCortex A53, Power VR G6230
  

GPU)

•  - 2GiB RAM
  

•  - 8GiB eMMC, uSD slot
  

•  - WiFi, Bluetooth and GPS module
  

•  - 2x Host, 1x Device USB port
  

•  - HDMI
  

•  - 20-pin low speed and 40-pin high speed expanders, 6
  

LED, 3 buttons +config MACH_S900

•    bool "Actionss Semi S900"
  

•    select ARM64
  
  

endchoice

-source "board/ucRobotics/bubblegum_96/Kconfig" +config SYS_CONFIG_NAME

•    default "s900" if MACH_S900
  

+config SYS_SOC

•    default "s900" if MACH_S900
  

+config SYS_TEXT_BASE

•    default 0x11000000
  
  

Move the above config symbols before MACH_S900.

...

endif diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile index 1b43dc2..0b181c6 100644 --- a/arch/arm/mach-owl/Makefile +++ b/arch/arm/mach-owl/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+

+obj-y += soc.o obj-y += sysmap-s900.o diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c new file mode 100644 index 0000000..d0630d2 --- /dev/null +++ b/arch/arm/mach-owl/soc.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Actions Semi SoCs Boards Support.

Owl SoCs...

Good point, but to avoid misunderstandings, you mean: * Actions Semi Owl SoCs boards support right? I just want to make sure that we keep "Actions Semi" somewhere, as many people might not know that "Owl" is the family name from that company and just "Owl" sounds rather generic.

Cheers, Andre.

...

• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

+#include <linux/arm-smccc.h> +#include <linux/psci.h> +#include <common.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/psci.h>

+DECLARE_GLOBAL_DATA_PTR;

+/*

• • dram_init - sets uboots idea of sdram size
• */

+int dram_init(void) +{

• gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
• return 0;

+}

+/* This is called after dram_init() so use get_ram_size result */ +int dram_init_banksize(void) +{

• gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
• gd->bd->bi_dram[0].size = gd->ram_size;
• return 0;

+}

+static void show_psci_version(void) +{

• struct arm_smccc_res res;
• arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0,

0, 0, &res); +

• printf("PSCI: v%ld.%ld\n",

• PSCI_VERSION_MAJOR(res.a0),
  

• PSCI_VERSION_MINOR(res.a0));
  

+}

+int board_init(void) +{

• show_psci_version();
• return 0;

+}

+void reset_cpu(ulong addr) +{

• psci_system_reset();

+} diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig deleted file mode 100644 index 2dd40d9..0000000 --- a/board/ucRobotics/bubblegum_96/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BUBBLEGUM_96

-config SYS_BOARD

• default "bubblegum_96"

-config SYS_VENDOR

• default "ucRobotics"

-config SYS_SOC

• default "s900"

-config SYS_CONFIG_NAME

• default "bubblegum_96"

-endif diff --git a/board/ucRobotics/bubblegum_96/MAINTAINERS b/board/ucRobotics/bubblegum_96/MAINTAINERS deleted file mode 100644 index d0cb727..0000000 --- a/board/ucRobotics/bubblegum_96/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BUBBLEGUM_96 BOARD -M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org -S: Maintained -F: board/ucRobotics/bubblegum_96/ -F: include/configs/bubblegum_96.h -F: configs/bubblegum_96_defconfig diff --git a/board/ucRobotics/bubblegum_96/Makefile b/board/ucRobotics/bubblegum_96/Makefile deleted file mode 100644 index c4b524d..0000000 --- a/board/ucRobotics/bubblegum_96/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+

-obj-y := bubblegum_96.o diff --git a/board/ucRobotics/bubblegum_96/bubblegum_96.c b/board/ucRobotics/bubblegum_96/bubblegum_96.c deleted file mode 100644 index a4c202d..0000000 --- a/board/ucRobotics/bubblegum_96/bubblegum_96.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Bubblegum-96 Boards Support
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

-#include <linux/arm-smccc.h> -#include <linux/psci.h> -#include <common.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/psci.h>

-DECLARE_GLOBAL_DATA_PTR;

-/*

• • dram_init - sets uboots idea of sdram size
• */

-int dram_init(void) -{

• gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
• return 0;

-}

-/* This is called after dram_init() so use get_ram_size result */ -int dram_init_banksize(void) -{

• gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
• gd->bd->bi_dram[0].size = gd->ram_size;
• return 0;

-}

-static void show_psci_version(void) -{

• struct arm_smccc_res res;
• arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0,

0, 0, &res); -

• printf("PSCI: v%ld.%ld\n",

•       PSCI_VERSION_MAJOR(res.a0),
  

• PSCI_VERSION_MINOR(res.a0));
  

-}

-int board_init(void) -{

• show_psci_version();
• return 0;

-}

-void reset_cpu(ulong addr) -{

• psci_system_reset();

-} diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index 74a9121..d1f403f 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OWL=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_TARGET_BUBBLEGUM_96=y +CONFIG_MACH_S900=y CONFIG_IDENT_STRING="\nBubblegum-96" CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 @@ -19,4 +18,3 @@ CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" CONFIG_CLK=y CONFIG_CLK_OWL=y CONFIG_CLK_S900=y -CONFIG_OWL_SERIAL=y diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h deleted file mode 100644 index e1dc37b..0000000 --- a/include/configs/bubblegum_96.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Board configuration file for Bubblegum-96
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

-#ifndef _BUBBLEGUM_96_H_ -#define _BUGGLEGUM_96_H_

-/* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000

-/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (24000000) /* 24MHz */ - -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)

-/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE

• 0x7ffc0) -

-/*

• • This is the initial SP which is used only briefly for

relocating the u-boot

• • image to the top of SDRAM. After relocation u-boot moves the

stack to the

• • proper place.
• */

-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) - -/* UART Definitions */ -#define CONFIG_BAUDRATE 115200

-#define CONFIG_ENV_SIZE 0x2000

-/* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

-#endif diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h new file mode 100644 index 0000000..42cd891 --- /dev/null +++ b/include/configs/owl-common.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Board configuration file for Actions Semi SoCs.

Owl SoCs...

...

• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

+#ifndef _OWL_COMMON_CONFIG_H_ +#define _OWL_COMMON_CONFIG_H_

+/* SDRAM Definitions */ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000

+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (24000000) /* 24MHz */ + +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)

+/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE

• 0x7ffc0) +

+/*

• • This is the initial SP which is used only briefly for

relocating the u-boot

• • image to the top of SDRAM. After relocation u-boot moves the

stack to the

• • proper place.
• */

+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) + +/* UART Definitions */ +#define CONFIG_BAUDRATE 115200

+#define CONFIG_ENV_SIZE 0x2000

+/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+#endif diff --git a/include/configs/s900.h b/include/configs/s900.h new file mode 100644 index 0000000..394925b --- /dev/null +++ b/include/configs/s900.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Board configuration file for Bubblegum-96 based on S900 SoC.

"s900.h" is not a board configuration file.

PS: I cannot verify this patchset on Bubblegum96 till Linaro Connect. But, I'll fix if any regression happens.

Thanks, Mani

...

• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam

manivannan.sadhasivam@linaro.org

• */

+#ifndef _CONFIG_S900_H_ +#define _CONFIG_S900_H_

+/*

• • Include common owl configuration where most the settings are
• */

+#include <configs/owl-common.h>

+#endif

2.7.4