[U-Boot] [PATCH v2 00/14] Moving Emaclite to DM + MDIO support

newer
[U-Boot] [PATCH v2 0/9] Various...

older
[U-Boot] [PATCH v2 00/11] Moving...

Michal Simek

17 Dec 2015 17 Dec '15

1:09 p.m.

Hi,

The first part of this series is about adding MDIO support to driver which was out of mainline and it was much easier to merge it before move to DM. Then driver didn't use indirect register access. In the middle of moving this driver I have fixed logic in some functions which doesn't affect performance of this driver. All these changes were tested on HW design with emaclite with and without pong buffers.

This patch series depends on microblaze cleanup series. All these patches will be available in git://git.denx.de/u-boot-microblaze.git also with patches which I am going to send now.

Thanks, Michal

Changes in v2: - Fix subject to point to rx instead of tx - Fix commit message - Joe - rename nextrxbuffertouse to use_rx_pong_buffer_next - Joe - fix type in immediatelly - Joe - Redesign packet lenght size to two subsequent reads - Remove additional blankline - new patch in this series - Joe

Michal Simek (14): net: emaclite: Remove ancient OF probe function net: emaclite: Add MDIO support to driver net: emaclite: Convert MDIO to use register offset net: emaclite: Use indirect register access for tx_ping/pong net: emaclite: Use indirect register access for rx_ping/pong net: emaclite: Use indirect register access for TX reset net: emaclite: Fix logic around available TX buffers net: emaclite: Remove XEL_TSR_XMIT_ACTIVE_MASK flag net: emaclite: Use indirect reg access in send net: emaclite: Use indirect access in emaclite_recv net: emaclite: Move driver to DM net: emaclite: Rename start and stop functions net: emaclite: Let core to handle received packet net: emaclite: Move emaclite to Kconfig

-- 1.9.1

Show replies by date

Michal Simek

17 Dec 17 Dec

1:09 p.m.

New subject: [U-Boot] [PATCH v2 01/14] net: emaclite: Remove ancient OF probe function

Prepare for DM move.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 30 ------------------------------ include/netdev.h | 1 - 2 files changed, 31 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 564205df83d3..d3d40b12adf2 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -360,33 +360,3 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,

return 1; } - -#if CONFIG_IS_ENABLED(OF_CONTROL) -int xilinx_emaclite_of_init(const void *blob) -{ - int offset = 0; - u32 ret = 0; - u32 reg; - - do { - offset = fdt_node_offset_by_compatible(blob, offset, - "xlnx,xps-ethernetlite-1.00.a"); - if (offset != -1) { - reg = fdtdec_get_addr(blob, offset, "reg"); - if (reg != FDT_ADDR_T_NONE) { - u32 rxpp = fdtdec_get_int(blob, offset, - "xlnx,rx-ping-pong", 0); - u32 txpp = fdtdec_get_int(blob, offset, - "xlnx,tx-ping-pong", 0); - ret |= xilinx_emaclite_initialize(NULL, reg, - txpp, rxpp); - } else { - debug("EMACLITE: Can't get base address\n"); - return -1; - } - } - } while (offset != -1); - - return ret; -} -#endif diff --git a/include/netdev.h b/include/netdev.h index b8d4e6abd5cc..9fc41ab11575 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -80,7 +80,6 @@ int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); -int xilinx_emaclite_of_init(const void *blob); int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 02/14] net: emaclite: Add MDIO support to driver

Add MDIO support before move to DM.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 238 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 238 insertions(+)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index d3d40b12adf2..f5e4c029ed75 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -10,9 +10,13 @@ #include <common.h> #include <net.h> #include <config.h> +#include <console.h> #include <malloc.h> #include <asm/io.h> +#include <phy.h> +#include <miiphy.h> #include <fdtdec.h> +#include <asm-generic/errno.h>

#undef DEBUG

@@ -46,11 +50,36 @@ /* Recv interrupt enable bit */ #define XEL_RSR_RECV_IE_MASK 0x00000008UL

+/* MDIO */ +#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ +#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ +#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ +#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ + +/* MDIO Address Register Bit Masks */ +#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ +#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ +#define XEL_MDIOADDR_PHYADR_SHIFT 5 +#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ + +/* MDIO Write Data Register Bit Masks */ +#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ + +/* MDIO Read Data Register Bit Masks */ +#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ + +/* MDIO Control Register Bit Masks */ +#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ +#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ + struct xemaclite { u32 nexttxbuffertouse; /* Next TX buffer to write to */ u32 nextrxbuffertouse; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ + int phyaddr; + struct phy_device *phydev; + struct mii_dev *bus; };

static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ @@ -107,11 +136,177 @@ static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) *to32ptr++ = alignbuffer; }

+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) +static int wait_for_bit(const char *func, u32 *reg, const u32 mask, + bool set, unsigned int timeout) +{ + u32 val; + unsigned long start = get_timer(0); + + while (1) { + val = readl(reg); + + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout) + break; + + if (ctrlc()) { + puts("Abort\n"); + return -EINTR; + } + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + func, reg, mask, set); + + return -ETIMEDOUT; +} + +static int mdio_wait(struct eth_device *dev) +{ + return wait_for_bit(__func__, + (u32 *)(dev->iobase + XEL_MDIOCTRL_OFFSET), + XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); +} + +static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, + u16 *data) +{ + if (mdio_wait(dev)) + return 1; + + u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); + out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, + XEL_MDIOADDR_OP_MASK | + ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, + ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + + if (mdio_wait(dev)) + return 1; + + /* Read data */ + *data = in_be32(dev->iobase + XEL_MDIORD_OFFSET); + return 0; +} + +static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, + u16 data) +{ + if (mdio_wait(dev)) + return 1; + + /* + * Write the PHY address, register number and clear the OP bit in the + * MDIO Address register and then write the value into the MDIO Write + * Data register. Finally, set the Status bit in the MDIO Control + * register to start a MDIO write transaction. + */ + u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); + out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, + ~XEL_MDIOADDR_OP_MASK & + ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); + out_be32(dev->iobase + XEL_MDIOWR_OFFSET, data); + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, + ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + + if (mdio_wait(dev)) + return 1; + + return 0; +} +#endif + static void emaclite_halt(struct eth_device *dev) { debug("eth_halt\n"); }

+/* Use MII register 1 (MII status register) to detect PHY */ +#define PHY_DETECT_REG 1 + +/* Mask used to verify certain PHY features (or register contents) + * in the register above: + * 0x1000: 10Mbps full duplex support + * 0x0800: 10Mbps half duplex support + * 0x0008: Auto-negotiation support + */ +#define PHY_DETECT_MASK 0x1808 + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) +static int setup_phy(struct eth_device *dev) +{ + int i; + u16 phyreg; + struct xemaclite *emaclite = dev->priv; + struct phy_device *phydev; + + u32 supported = SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full; + + if (emaclite->phyaddr != -1) { + phyread(dev, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + debug("Default phy address %d is valid\n", + emaclite->phyaddr); + } else { + debug("PHY address is not setup correctly %d\n", + emaclite->phyaddr); + emaclite->phyaddr = -1; + } + } + + if (emaclite->phyaddr == -1) { + /* detect the PHY address */ + for (i = 31; i >= 0; i--) { + phyread(dev, i, PHY_DETECT_REG, &phyreg); + if ((phyreg != 0xFFFF) && + ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + emaclite->phyaddr = i; + debug("emaclite: Found valid phy address, %d\n", + i); + break; + } + } + } + + /* interface - look at tsec */ + phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, + PHY_INTERFACE_MODE_MII); + /* + * Phy can support 1000baseT but device NOT that's why phydev->supported + * must be setup for 1000baseT. phydev->advertising setups what speeds + * will be used for autonegotiation where 1000baseT must be disabled. + */ + phydev->supported = supported | SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; + phydev->advertising = supported; + emaclite->phydev = phydev; + phy_config(phydev); + phy_startup(phydev); + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } + + /* Do not setup anything */ + return 1; +} +#endif + static int emaclite_init(struct eth_device *dev, bd_t *bis) { struct xemaclite *emaclite = dev->priv; @@ -156,6 +351,13 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, XEL_RSR_RECV_IE_MASK);

+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, XEL_MDIOCTRL_MDIOEN_MASK); + if (in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET) & + XEL_MDIOCTRL_MDIOEN_MASK) + if (!setup_phy(dev)) + return -1; +#endif debug("EmacLite Initialization complete\n"); return 0; } @@ -327,6 +529,28 @@ static int emaclite_recv(struct eth_device *dev)

}

+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) +static int emaclite_miiphy_read(const char *devname, uchar addr, + uchar reg, ushort *val) +{ + u32 ret; + struct eth_device *dev = eth_get_dev(); + + ret = phyread(dev, addr, reg, val); + debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); + return ret; +} + +static int emaclite_miiphy_write(const char *devname, uchar addr, + uchar reg, ushort val) +{ + struct eth_device *dev = eth_get_dev(); + + debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); + return phywrite(dev, addr, reg, val); +} +#endif + int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, int txpp, int rxpp) { @@ -356,7 +580,21 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, dev->send = emaclite_send; dev->recv = emaclite_recv;

+#ifdef CONFIG_PHY_ADDR + emaclite->phyaddr = CONFIG_PHY_ADDR; +#else + emaclite->phyaddr = -1; +#endif + eth_register(dev);

+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) + miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); + emaclite->bus = miiphy_get_dev_by_name(dev->name); + + out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, + XEL_MDIOCTRL_MDIOEN_MASK); +#endif + return 1; }

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 03/14] net: emaclite: Convert MDIO to use register offset

Use u-boot coding style how to setup and access MDIO bus.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 92 ++++++++++++++++++++++++++----------------- 1 file changed, 56 insertions(+), 36 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index f5e4c029ed75..9d413a0bbf8d 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -50,12 +50,6 @@ /* Recv interrupt enable bit */ #define XEL_RSR_RECV_IE_MASK 0x00000008UL

-/* MDIO */ -#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ -#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ -#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ -#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ - /* MDIO Address Register Bit Masks */ #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ @@ -72,12 +66,36 @@ #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */

+struct emaclite_regs { + u32 tx_ping; /* 0x0 - TX Ping buffer */ + u32 reserved1[504]; + u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ + u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ + u32 mdiord;/* 0x7ec - MDIO Read Data Register */ + u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ + u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ + u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ + u32 tx_ping_tsr; /* 0x7fc - Tx status */ + u32 tx_pong; /* 0x800 - TX Pong buffer */ + u32 reserved2[508]; + u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ + u32 reserved3; /* 0xff8 */ + u32 tx_pong_tsr; /* 0xffc - Tx status */ + u32 rx_ping; /* 0x1000 - Receive Buffer */ + u32 reserved4[510]; + u32 rx_ping_rsr; /* 0x17fc - Rx status */ + u32 rx_pong; /* 0x1800 - Receive Buffer */ + u32 reserved5[510]; + u32 rx_pong_rsr; /* 0x1ffc - Rx status */ +}; + struct xemaclite { u32 nexttxbuffertouse; /* Next TX buffer to write to */ u32 nextrxbuffertouse; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ int phyaddr; + struct emaclite_regs *regs; struct phy_device *phydev; struct mii_dev *bus; }; @@ -169,38 +187,39 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask, return -ETIMEDOUT; }

-static int mdio_wait(struct eth_device *dev) +static int mdio_wait(struct emaclite_regs *regs) { - return wait_for_bit(__func__, - (u32 *)(dev->iobase + XEL_MDIOCTRL_OFFSET), + return wait_for_bit(__func__, &regs->mdioctrl, XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); }

-static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum, +static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, u16 *data) { - if (mdio_wait(dev)) + struct emaclite_regs *regs = emaclite->regs; + + if (mdio_wait(regs)) return 1;

- u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); - out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, - XEL_MDIOADDR_OP_MASK | + u32 ctrl_reg = in_be32(&regs->mdioctrl); + out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); - out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, - ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);

- if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1;

/* Read data */ - *data = in_be32(dev->iobase + XEL_MDIORD_OFFSET); + *data = in_be32(&regs->mdiord); return 0; }

-static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, +static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, u16 data) { - if (mdio_wait(dev)) + struct emaclite_regs *regs = emaclite->regs; + + if (mdio_wait(regs)) return 1;

/* @@ -209,15 +228,13 @@ static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum, * Data register. Finally, set the Status bit in the MDIO Control * register to start a MDIO write transaction. */ - u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET); - out_be32(dev->iobase + XEL_MDIOADDR_OFFSET, - ~XEL_MDIOADDR_OP_MASK & + u32 ctrl_reg = in_be32(&regs->mdioctrl); + out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); - out_be32(dev->iobase + XEL_MDIOWR_OFFSET, data); - out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, - ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); + out_be32(&regs->mdiowr, data); + out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);

- if (mdio_wait(dev)) + if (mdio_wait(regs)) return 1;

return 0; @@ -254,7 +271,7 @@ static int setup_phy(struct eth_device *dev) SUPPORTED_100baseT_Full;

if (emaclite->phyaddr != -1) { - phyread(dev, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); + phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ @@ -270,7 +287,7 @@ static int setup_phy(struct eth_device *dev) if (emaclite->phyaddr == -1) { /* detect the PHY address */ for (i = 31; i >= 0; i--) { - phyread(dev, i, PHY_DETECT_REG, &phyreg); + phyread(emaclite, i, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ @@ -310,6 +327,8 @@ static int setup_phy(struct eth_device *dev) static int emaclite_init(struct eth_device *dev, bd_t *bis) { struct xemaclite *emaclite = dev->priv; + struct emaclite_regs *regs = emaclite->regs; + debug("EmacLite Initialization Started\n");

/* @@ -352,9 +371,8 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) XEL_RSR_RECV_IE_MASK);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, XEL_MDIOCTRL_MDIOEN_MASK); - if (in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET) & - XEL_MDIOCTRL_MDIOEN_MASK) + out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); + if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) if (!setup_phy(dev)) return -1; #endif @@ -536,7 +554,7 @@ static int emaclite_miiphy_read(const char *devname, uchar addr, u32 ret; struct eth_device *dev = eth_get_dev();

- ret = phyread(dev, addr, reg, val); + ret = phyread(dev->priv, addr, reg, val); debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); return ret; } @@ -547,7 +565,7 @@ static int emaclite_miiphy_write(const char *devname, uchar addr, struct eth_device *dev = eth_get_dev();

debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); - return phywrite(dev, addr, reg, val); + return phywrite(dev->priv, addr, reg, val); } #endif

@@ -556,6 +574,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, { struct eth_device *dev; struct xemaclite *emaclite; + struct emaclite_regs *regs;

dev = calloc(1, sizeof(*dev)); if (dev == NULL) @@ -574,6 +593,8 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,

sprintf(dev->name, "Xelite.%lx", base_addr);

+ emaclite->regs = (struct emaclite_regs *)base_addr; + regs = emaclite->regs; dev->iobase = base_addr; dev->init = emaclite_init; dev->halt = emaclite_halt; @@ -592,8 +613,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); emaclite->bus = miiphy_get_dev_by_name(dev->name);

- out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, - XEL_MDIOCTRL_MDIOEN_MASK); + out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); #endif

return 1;

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 04/14] net: emaclite: Use indirect register access for tx_ping/pong

Do initialization via indirect register access.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 9d413a0bbf8d..654ad58cea3c 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -335,28 +335,28 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) * TX - TX_PING & TX_PONG initialization */ /* Restart PING TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + out_be32(&regs->tx_ping_tsr, 0); /* Copy MAC address */ - xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH); + xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_ping, + ENET_ADDR_LENGTH); /* Set the length */ - out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH); /* Update the MAC address in the EMAC Lite */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); /* Wait for EMAC Lite to finish with the MAC address update */ - while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) & + while ((in_be32 (&regs->tx_ping_tsr) & XEL_TSR_PROG_MAC_ADDR) != 0) ;

if (emaclite->txpp) { /* The same operation with PONG TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); - xemaclite_alignedwrite(dev->enetaddr, dev->iobase + - XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); - out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); - out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_TSR_PROG_MAC_ADDR); - while ((in_be32 (dev->iobase + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) + out_be32(&regs->tx_pong_tsr, 0); + xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_pong, + ENET_ADDR_LENGTH); + out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH); + out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); + while ((in_be32(&regs->tx_pong_tsr) & + XEL_TSR_PROG_MAC_ADDR) != 0) ; }

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 05/14] net: emaclite: Use indirect register access for rx_ping/pong

Do initialization via indirect register access.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

Changes in v2: - Fix subject to point to rx instead of tx

drivers/net/xilinx_emaclite.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 654ad58cea3c..724b61e0b7e1 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -364,11 +364,10 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) * RX - RX_PING & RX_PONG initialization */ /* Write out the value to flush the RX buffer */ - out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); + out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);

if (emaclite->rxpp) - out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, - XEL_RSR_RECV_IE_MASK); + out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 06/14] net: emaclite: Use indirect register access for TX reset

Move to use indirect register access when timeout expires for resetting TX buffers.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 724b61e0b7e1..72b6e0ac424a 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -408,6 +408,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) u32 reg; u32 baseaddress; struct xemaclite *emaclite = dev->priv; + struct emaclite_regs *regs = emaclite->regs;

u32 maxtry = 1000;

@@ -422,10 +423,9 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) if (!maxtry) { printf("Error: Timeout waiting for ethernet TX buffer\n"); /* Restart PING TX */ - out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); + out_be32(&regs->tx_ping_tsr, 0); if (emaclite->txpp) { - out_be32 (dev->iobase + XEL_TSR_OFFSET + - XEL_BUFFER_OFFSET, 0); + out_be32(&regs->tx_pong_tsr, 0); } return -1; }

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 07/14] net: emaclite: Fix logic around available TX buffers

Simplify logic how to find out if there is free TX buffer. Both buffers are checked all the time that's why logic around order can be removed. Also add check when only one buffer is available.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 72b6e0ac424a..b0c26354e2e2 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -379,28 +379,20 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) return 0; }

-static int xemaclite_txbufferavailable(struct eth_device *dev) +static int xemaclite_txbufferavailable(struct xemaclite *emaclite) { - u32 reg; - u32 txpingbusy; - u32 txpongbusy; - struct xemaclite *emaclite = dev->priv; + u32 tmp; + struct emaclite_regs *regs = emaclite->regs;

/* * Read the other buffer register * and determine if the other buffer is available */ - reg = in_be32 (dev->iobase + - emaclite->nexttxbuffertouse + 0); - txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); - - reg = in_be32 (dev->iobase + - (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); - txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == - XEL_TSR_XMIT_BUSY_MASK); + tmp = ~in_be32(&regs->tx_ping_tsr); + if (emaclite->txpp) + tmp |= ~in_be32(&regs->tx_pong_tsr);

- return !(txpingbusy && txpongbusy); + return !(tmp & XEL_TSR_XMIT_BUSY_MASK); }

static int emaclite_send(struct eth_device *dev, void *ptr, int len) @@ -415,7 +407,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) if (len > PKTSIZE) len = PKTSIZE;

- while (!xemaclite_txbufferavailable(dev) && maxtry) { + while (xemaclite_txbufferavailable(emaclite) && maxtry) { udelay(10); maxtry--; }

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 08/14] net: emaclite: Remove XEL_TSR_XMIT_ACTIVE_MASK flag

This flag is not documented anywhere in the latest documentation that's why this patch removes it.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index b0c26354e2e2..b6f3acae5a01 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -33,8 +33,6 @@ #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL /* Xmit interrupt enable bit */ #define XEL_TSR_XMIT_IE_MASK 0x00000008UL -/* Buffer is active, SW bit only */ -#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL /* Program the MAC address */ #define XEL_TSR_PROGRAM_MASK 0x00000002UL /* define for programming the MAC address into the EMAC Lite */ @@ -427,10 +425,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)

/* Determine if the expected buffer address is empty */ reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { - + if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { if (emaclite->txpp) emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;

@@ -441,8 +436,6 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); reg = in_be32 (baseaddress + XEL_TSR_OFFSET); reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) - reg |= XEL_TSR_XMIT_ACTIVE_MASK; out_be32 (baseaddress + XEL_TSR_OFFSET, reg); return 0; } @@ -452,9 +445,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) baseaddress ^= XEL_BUFFER_OFFSET; /* Determine if the expected buffer address is empty */ reg = in_be32 (baseaddress + XEL_TSR_OFFSET); - if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) - && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) - & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { + if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { debug("Send packet from 0x%x\n", baseaddress); /* Write the frame to the buffer */ xemaclite_alignedwrite(ptr, baseaddress, len); @@ -463,8 +454,6 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) XEL_TPLR_LENGTH_MASK_LO))); reg = in_be32 (baseaddress + XEL_TSR_OFFSET); reg |= XEL_TSR_XMIT_BUSY_MASK; - if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) - reg |= XEL_TSR_XMIT_ACTIVE_MASK; out_be32 (baseaddress + XEL_TSR_OFFSET, reg); return 0; }

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 09/14] net: emaclite: Use indirect reg access in send

The original logic in the driver was exchanging buffers which are used for sending packet and tx_ping and tx_pong buffers were exchanged all the time to ensure that IP has enough time to send the packet out. Based on this "feature" send function was using nextbuffertouse variable to save which buffer should be used. Before this algorithm was called driver checked that there is free buffer available. This checking remains in the driver but driver tries to use tx_ping first if available. If not, tx_pong buffer is used instead. To reach this code the original condition is met that at least one of the buffer should be available. Testing doesn't show any performance drop when this patch is applied.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: - Fix commit message - Joe

drivers/net/xilinx_emaclite.c | 48 ++++++++++++++++--------------------------- 1 file changed, 18 insertions(+), 30 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index b6f3acae5a01..e97ce2ce31f3 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -24,8 +24,6 @@

/* EmacLite constants */ #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ -#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ -#define XEL_TSR_OFFSET 0x07FC /* Tx status */ #define XEL_RSR_OFFSET 0x17FC /* Rx status */ #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */

@@ -88,7 +86,6 @@ struct emaclite_regs { };

struct xemaclite { - u32 nexttxbuffertouse; /* Next TX buffer to write to */ u32 nextrxbuffertouse; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ @@ -126,7 +123,7 @@ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) *to8ptr++ = *from8ptr++; }

-static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) +static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) { u32 i; u32 alignbuffer; @@ -335,7 +332,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) /* Restart PING TX */ out_be32(&regs->tx_ping_tsr, 0); /* Copy MAC address */ - xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_ping, + xemaclite_alignedwrite(dev->enetaddr, &regs->tx_ping, ENET_ADDR_LENGTH); /* Set the length */ out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH); @@ -349,7 +346,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) if (emaclite->txpp) { /* The same operation with PONG TX */ out_be32(&regs->tx_pong_tsr, 0); - xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_pong, + xemaclite_alignedwrite(dev->enetaddr, &regs->tx_pong, ENET_ADDR_LENGTH); out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH); out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); @@ -396,7 +393,6 @@ static int xemaclite_txbufferavailable(struct xemaclite *emaclite) static int emaclite_send(struct eth_device *dev, void *ptr, int len) { u32 reg; - u32 baseaddress; struct xemaclite *emaclite = dev->priv; struct emaclite_regs *regs = emaclite->regs;

@@ -420,41 +416,33 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) return -1; }

- /* Determine the expected TX buffer address */ - baseaddress = (dev->iobase + emaclite->nexttxbuffertouse); - /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg = in_be32(&regs->tx_ping_tsr); if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { - if (emaclite->txpp) - emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; - - debug("Send packet from 0x%x\n", baseaddress); + debug("Send packet from tx_ping buffer\n"); /* Write the frame to the buffer */ - xemaclite_alignedwrite(ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & - (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + xemaclite_alignedwrite(ptr, &regs->tx_ping, len); + out_be32(&regs->tx_ping_tplr, len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)); + reg = in_be32(&regs->tx_ping_tsr); reg |= XEL_TSR_XMIT_BUSY_MASK; - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + out_be32(&regs->tx_ping_tsr, reg); return 0; }

if (emaclite->txpp) { - /* Switch to second buffer */ - baseaddress ^= XEL_BUFFER_OFFSET; /* Determine if the expected buffer address is empty */ - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg = in_be32(&regs->tx_pong_tsr); if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { - debug("Send packet from 0x%x\n", baseaddress); + debug("Send packet from tx_pong buffer\n"); /* Write the frame to the buffer */ - xemaclite_alignedwrite(ptr, baseaddress, len); - out_be32 (baseaddress + XEL_TPLR_OFFSET, (len & - (XEL_TPLR_LENGTH_MASK_HI | - XEL_TPLR_LENGTH_MASK_LO))); - reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + xemaclite_alignedwrite(ptr, &regs->tx_pong, len); + out_be32(&regs->tx_pong_tplr, len & + (XEL_TPLR_LENGTH_MASK_HI | + XEL_TPLR_LENGTH_MASK_LO)); + reg = in_be32(&regs->tx_pong_tsr); reg |= XEL_TSR_XMIT_BUSY_MASK; - out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + out_be32(&regs->tx_pong_tsr, reg); return 0; } }

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 10/14] net: emaclite: Use indirect access in emaclite_recv

When IP is configured with pong buffers, IP is receiving packets to ping and then to pong buffer and than ping again. The original logic in the driver remains there that when ping buffer is free, pong buffer is checked too and return if both are free.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

Changes in v2: - rename nextrxbuffertouse to use_rx_pong_buffer_next - Joe - fix type in immediatelly - Joe - Redesign packet lenght size to two subsequent reads

drivers/net/xilinx_emaclite.c | 125 ++++++++++++++++++++++++------------------ 1 file changed, 73 insertions(+), 52 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index e97ce2ce31f3..800345bba489 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -17,15 +17,12 @@ #include <miiphy.h> #include <fdtdec.h> #include <asm-generic/errno.h> +#include <linux/kernel.h>

#undef DEBUG

#define ENET_ADDR_LENGTH 6 - -/* EmacLite constants */ -#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ -#define XEL_RSR_OFFSET 0x17FC /* Rx status */ -#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ +#define ETH_FCS_LEN 4 /* Octets in the FCS */

/* Xmit complete */ #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL @@ -86,7 +83,7 @@ struct emaclite_regs { };

struct xemaclite { - u32 nextrxbuffertouse; /* Next RX buffer to read from */ + bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ u32 txpp; /* TX ping pong buffer */ u32 rxpp; /* RX ping pong buffer */ int phyaddr; @@ -453,63 +450,87 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len)

static int emaclite_recv(struct eth_device *dev) { - u32 length; - u32 reg; - u32 baseaddress; + u32 length, first_read, reg, attempt = 0; + void *addr, *ack; struct xemaclite *emaclite = dev->priv; - - baseaddress = dev->iobase + emaclite->nextrxbuffertouse; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - debug("Testing data at address 0x%x\n", baseaddress); - if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { - if (emaclite->rxpp) - emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; + struct emaclite_regs *regs = emaclite->regs; + struct ethernet_hdr *eth; + struct ip_udp_hdr *ip; + +try_again: + if (!emaclite->use_rx_pong_buffer_next) { + reg = in_be32(&regs->rx_ping_rsr); + debug("Testing data at rx_ping\n"); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + debug("Data found in rx_ping buffer\n"); + addr = &regs->rx_ping; + ack = &regs->rx_ping_rsr; + } else { + debug("Data not found in rx_ping buffer\n"); + /* Pong buffer is not available - return immediately */ + if (!emaclite->rxpp) + return -1; + + /* Try pong buffer if this is first attempt */ + if (attempt++) + return -1; + emaclite->use_rx_pong_buffer_next = + !emaclite->use_rx_pong_buffer_next; + goto try_again; + } } else { - - if (!emaclite->rxpp) { - debug("No data was available - address 0x%x\n", - baseaddress); - return 0; + reg = in_be32(&regs->rx_pong_rsr); + debug("Testing data at rx_pong\n"); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { + debug("Data found in rx_pong buffer\n"); + addr = &regs->rx_pong; + ack = &regs->rx_pong_rsr; } else { - baseaddress ^= XEL_BUFFER_OFFSET; - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); - if ((reg & XEL_RSR_RECV_DONE_MASK) != - XEL_RSR_RECV_DONE_MASK) { - debug("No data was available - address 0x%x\n", - baseaddress); - return 0; - } + debug("Data not found in rx_pong buffer\n"); + /* Try ping buffer if this is first attempt */ + if (attempt++) + return -1; + emaclite->use_rx_pong_buffer_next = + !emaclite->use_rx_pong_buffer_next; + goto try_again; } } - /* Get the length of the frame that arrived */ - switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & - 0xFFFF0000 ) >> 16) { - case 0x806: - length = 42 + 20; /* FIXME size of ARP */ - debug("ARP Packet\n"); - break; - case 0x800: - length = 14 + 14 + - (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + - 0x10))) & 0xFFFF0000) >> 16); - /* FIXME size of IP packet */ - debug ("IP Packet\n"); - break; - default: - debug("Other Packet\n"); - length = PKTSIZE; - break; + + /* Read all bytes for ARP packet with 32bit alignment - 48bytes */ + first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); + xemaclite_alignedread(addr, etherrxbuff, first_read); + + /* Detect real packet size */ + eth = (struct ethernet_hdr *)etherrxbuff; + switch (ntohs(eth->et_protlen)) { + case PROT_ARP: + length = first_read; + debug("ARP Packet %x\n", length); + break; + case PROT_IP: + ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); + length = ntohs(ip->ip_len); + length += ETHER_HDR_SIZE + ETH_FCS_LEN; + debug("IP Packet %x\n", length); + break; + default: + debug("Other Packet\n"); + length = PKTSIZE; + break; }

- xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), - etherrxbuff, length); + /* Read the rest of the packet which is longer then first read */ + if (length != first_read) + xemaclite_alignedread(addr + first_read, + etherrxbuff + first_read, + length - first_read);

/* Acknowledge the frame */ - reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + reg = in_be32(ack); reg &= ~XEL_RSR_RECV_DONE_MASK; - out_be32 (baseaddress + XEL_RSR_OFFSET, reg); + out_be32(ack, reg);

- debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); + debug("Packet receive from 0x%p, length %dB\n", addr, length); net_process_received_packet((uchar *)etherrxbuff, length); return length;

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 11/14] net: emaclite: Move driver to DM

Move driver to DM.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: - Remove additional blankline

.../xilinx/microblaze-generic/microblaze-generic.c | 21 --- board/xilinx/zynq/board.c | 20 --- configs/microblaze-generic_defconfig | 1 + drivers/net/xilinx_emaclite.c | 159 ++++++++++++--------- include/netdev.h | 2 - 5 files changed, 92 insertions(+), 111 deletions(-)

diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index a3122da9acaa..0e7509d288ce 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -12,7 +12,6 @@ #include <common.h> #include <config.h> #include <fdtdec.h> -#include <netdev.h> #include <asm/processor.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -100,23 +99,3 @@ void board_init(void) { gpio_init(); } - -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - - return ret; -} diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 427e75485deb..e89b05dffb4c 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -8,7 +8,6 @@ #include <fdtdec.h> #include <fpga.h> #include <mmc.h> -#include <netdev.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -99,25 +98,6 @@ int checkboard(void) } #endif

-int board_eth_init(bd_t *bis) -{ - u32 ret = 0; - -#ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - return ret; -} - int dram_init(void) { #if CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index dad05410be50..5e815c6bcdcb 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -9,6 +9,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y +CONFIG_DM_ETH=y CONFIG_PHYLIB=y CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 800345bba489..903b3e8d19a4 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -10,6 +10,7 @@ #include <common.h> #include <net.h> #include <config.h> +#include <dm.h> #include <console.h> #include <malloc.h> #include <asm/io.h> @@ -19,7 +20,7 @@ #include <asm-generic/errno.h> #include <linux/kernel.h>

-#undef DEBUG +DECLARE_GLOBAL_DATA_PTR;

#define ENET_ADDR_LENGTH 6 #define ETH_FCS_LEN 4 /* Octets in the FCS */ @@ -146,7 +147,6 @@ static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) *to32ptr++ = alignbuffer; }

-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) static int wait_for_bit(const char *func, u32 *reg, const u32 mask, bool set, unsigned int timeout) { @@ -231,9 +231,8 @@ static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,

return 0; } -#endif

-static void emaclite_halt(struct eth_device *dev) +static void emaclite_halt(struct udevice *dev) { debug("eth_halt\n"); } @@ -249,12 +248,11 @@ static void emaclite_halt(struct eth_device *dev) */ #define PHY_DETECT_MASK 0x1808

-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) -static int setup_phy(struct eth_device *dev) +static int setup_phy(struct udevice *dev) { int i; u16 phyreg; - struct xemaclite *emaclite = dev->priv; + struct xemaclite *emaclite = dev_get_priv(dev); struct phy_device *phydev;

u32 supported = SUPPORTED_10baseT_Half | @@ -314,11 +312,11 @@ static int setup_phy(struct eth_device *dev) /* Do not setup anything */ return 1; } -#endif

-static int emaclite_init(struct eth_device *dev, bd_t *bis) +static int emaclite_init(struct udevice *dev) { - struct xemaclite *emaclite = dev->priv; + struct xemaclite *emaclite = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); struct emaclite_regs *regs = emaclite->regs;

debug("EmacLite Initialization Started\n"); @@ -329,7 +327,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) /* Restart PING TX */ out_be32(&regs->tx_ping_tsr, 0); /* Copy MAC address */ - xemaclite_alignedwrite(dev->enetaddr, &regs->tx_ping, + xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping, ENET_ADDR_LENGTH); /* Set the length */ out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH); @@ -343,7 +341,7 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) if (emaclite->txpp) { /* The same operation with PONG TX */ out_be32(&regs->tx_pong_tsr, 0); - xemaclite_alignedwrite(dev->enetaddr, &regs->tx_pong, + xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong, ENET_ADDR_LENGTH); out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH); out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); @@ -361,12 +359,11 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) if (emaclite->rxpp) out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);

-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) if (!setup_phy(dev)) return -1; -#endif + debug("EmacLite Initialization complete\n"); return 0; } @@ -387,10 +384,10 @@ static int xemaclite_txbufferavailable(struct xemaclite *emaclite) return !(tmp & XEL_TSR_XMIT_BUSY_MASK); }

-static int emaclite_send(struct eth_device *dev, void *ptr, int len) +static int emaclite_send(struct udevice *dev, void *ptr, int len) { u32 reg; - struct xemaclite *emaclite = dev->priv; + struct xemaclite *emaclite = dev_get_priv(dev); struct emaclite_regs *regs = emaclite->regs;

u32 maxtry = 1000; @@ -448,7 +445,7 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) return -1; }

-static int emaclite_recv(struct eth_device *dev) +static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp) { u32 length, first_read, reg, attempt = 0; void *addr, *ack; @@ -532,78 +529,104 @@ try_again:

debug("Packet receive from 0x%p, length %dB\n", addr, length); net_process_received_packet((uchar *)etherrxbuff, length); - return length; - + return 0; }

-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) -static int emaclite_miiphy_read(const char *devname, uchar addr, - uchar reg, ushort *val) +static int emaclite_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) { u32 ret; - struct eth_device *dev = eth_get_dev(); + u16 val = 0;

- ret = phyread(dev->priv, addr, reg, val); - debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val); - return ret; + ret = phyread(bus->priv, addr, reg, &val); + debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret); + return val; }

-static int emaclite_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) +static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { - struct eth_device *dev = eth_get_dev(); - - debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val); - return phywrite(dev->priv, addr, reg, val); + debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); + return phywrite(bus->priv, addr, reg, value); } -#endif

-int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, - int txpp, int rxpp) +static int emaclite_probe(struct udevice *dev) { - struct eth_device *dev; - struct xemaclite *emaclite; - struct emaclite_regs *regs; + struct xemaclite *emaclite = dev_get_priv(dev); + int ret;

- dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -1; + emaclite->bus = mdio_alloc(); + emaclite->bus->read = emaclite_miiphy_read; + emaclite->bus->write = emaclite_miiphy_write; + emaclite->bus->priv = emaclite; + strcpy(emaclite->bus->name, "emaclite");

- emaclite = calloc(1, sizeof(struct xemaclite)); - if (emaclite == NULL) { - free(dev); - return -1; - } + ret = mdio_register(emaclite->bus); + if (ret) + return ret; + + return 0; +}

- dev->priv = emaclite; +static int emaclite_remove(struct udevice *dev) +{ + struct xemaclite *emaclite = dev_get_priv(dev); + + free(emaclite->phydev); + mdio_unregister(emaclite->bus); + mdio_free(emaclite->bus);

- emaclite->txpp = txpp; - emaclite->rxpp = rxpp; + return 0; +}

- sprintf(dev->name, "Xelite.%lx", base_addr); +static const struct eth_ops emaclite_ops = { + .start = emaclite_init, + .send = emaclite_send, + .recv = emaclite_recv, + .stop = emaclite_halt, +}; + +static int emaclite_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct xemaclite *emaclite = dev_get_priv(dev); + int offset = 0;

- emaclite->regs = (struct emaclite_regs *)base_addr; - regs = emaclite->regs; - dev->iobase = base_addr; - dev->init = emaclite_init; - dev->halt = emaclite_halt; - dev->send = emaclite_send; - dev->recv = emaclite_recv; + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + emaclite->regs = (struct emaclite_regs *)pdata->iobase;

-#ifdef CONFIG_PHY_ADDR - emaclite->phyaddr = CONFIG_PHY_ADDR; -#else emaclite->phyaddr = -1; -#endif

- eth_register(dev); + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy-handle"); + if (offset > 0) + emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, + "reg", -1);

-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write); - emaclite->bus = miiphy_get_dev_by_name(dev->name); + emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,tx-ping-pong", 0); + emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "xlnx,rx-ping-pong", 0);

- out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); -#endif + printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, + emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);

- return 1; + return 0; } + +static const struct udevice_id emaclite_ids[] = { + { .compatible = "xlnx,xps-ethernetlite-1.00.a" }, + { } +}; + +U_BOOT_DRIVER(emaclite) = { + .name = "emaclite", + .id = UCLASS_ETH, + .of_match = emaclite_ids, + .ofdata_to_platdata = emaclite_ofdata_to_platdata, + .probe = emaclite_probe, + .remove = emaclite_remove, + .ops = &emaclite_ops, + .priv_auto_alloc_size = sizeof(struct xemaclite), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/include/netdev.h b/include/netdev.h index 9fc41ab11575..244f23f93c36 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -80,8 +80,6 @@ int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); int armada100_fec_register(unsigned long base_addr); -int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, - int txpp, int rxpp); int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags, unsigned long ctrl_addr); /*

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 12/14] net: emaclite: Rename start and stop functions

Rename start and stop functions to align with DM functions names.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

Changes in v2: - new patch in this series - Joe

drivers/net/xilinx_emaclite.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 903b3e8d19a4..7e9a31ea982d 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -232,9 +232,9 @@ static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, return 0; }

-static void emaclite_halt(struct udevice *dev) +static void emaclite_stop(struct udevice *dev) { - debug("eth_halt\n"); + debug("eth_stop\n"); }

/* Use MII register 1 (MII status register) to detect PHY */ @@ -313,7 +313,7 @@ static int setup_phy(struct udevice *dev) return 1; }

-static int emaclite_init(struct udevice *dev) +static int emaclite_start(struct udevice *dev) { struct xemaclite *emaclite = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_platdata(dev); @@ -580,10 +580,10 @@ static int emaclite_remove(struct udevice *dev) }

static const struct eth_ops emaclite_ops = { - .start = emaclite_init, + .start = emaclite_start, .send = emaclite_send, .recv = emaclite_recv, - .stop = emaclite_halt, + .stop = emaclite_stop, };

static int emaclite_ofdata_to_platdata(struct udevice *dev)

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 13/14] net: emaclite: Let core to handle received packet

Pass pointer to core to handle packet.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

Changes in v2: None

drivers/net/xilinx_emaclite.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 7e9a31ea982d..5862bf0a7e2d 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -93,7 +93,7 @@ struct xemaclite { struct mii_dev *bus; };

-static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ +static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */

static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) { @@ -528,8 +528,8 @@ try_again: out_be32(ack, reg);

debug("Packet receive from 0x%p, length %dB\n", addr, length); - net_process_received_packet((uchar *)etherrxbuff, length); - return 0; + *packetp = etherrxbuff; + return length; }

static int emaclite_miiphy_read(struct mii_dev *bus, int addr,

-- 1.9.1

Michal Simek

1:09 p.m.

New subject: [U-Boot] [PATCH v2 14/14] net: emaclite: Move emaclite to Kconfig

Add PHYLIB and MII dependencies and enable it by default for Microblaze.

Signed-off-by: Michal Simek michal.simek@xilinx.com Acked-by: Joe Hershberger joe.hershberger@ni.com ---

Changes in v2: None

board/xilinx/microblaze-generic/xparameters.h | 3 --- configs/microblaze-generic_defconfig | 2 +- drivers/net/Kconfig | 8 ++++++++ include/configs/microblaze-generic.h | 3 +-- 4 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 79c87fb61803..4f44427e601c 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -44,9 +44,6 @@ #define XILINX_SYSACE_HIGHADDR 0x4180ffff #define XILINX_SYSACE_MEM_WIDTH 16

-/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 5e815c6bcdcb..1a389615729f 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -10,6 +10,6 @@ CONFIG_CMD_GPIO=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_DM_ETH=y -CONFIG_PHYLIB=y +CONFIG_XILINX_EMACLITE=y CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 9dc106cc93b7..43e4f600e7cc 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -109,6 +109,14 @@ config XILINX_AXIEMAC help This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.

+config XILINX_EMACLITE + depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) + select PHYLIB + select MII + bool "Xilinx Ethernetlite" + help + This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. + config ZYNQ_GEM depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP) select PHYLIB diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index f1525f506a7d..4d8bf46e69f2 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -42,8 +42,7 @@

/* ethernet */ #undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) -# define CONFIG_XILINX_EMACLITE 1 +#if defined(CONFIG_XILINX_EMACLITE) # define CONFIG_SYS_ENET #endif #if defined(XILINX_AXIEMAC_BASEADDR)

-- 1.9.1

3432

Age (days ago)

3432

Last active (days ago)

List overview

Download

14 comments

1 participants

tags (0)

participants (1)

Michal Simek