On 12/3/2013 12:56 PM, Fabio Estevam wrote:

From: Fabio Estevam fabio.estevam@freescale.com

According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.

• 00 - 25MHz
• 01 - 50MHz
• 10 - 100MHz
• 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury rabeeh@solid-run.com Signed-off-by: Fabio Estevam fabio.estevam@freescale.com

---

arch/arm/cpu/armv7/mx6/clock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 873d9d0..eab8596 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -94,7 +94,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) div = __raw_readl(&imx_ccm->analog_pll_enet); div &= BM_ANADIG_PLL_ENET_DIV_SELECT;

• return (div == 3 ? 125000000 : 25000000 * (div << 1));
  

• if (div == 0)
  

• 	return 25000000;
  

• else
  

• 	return (div == 3 ? 125000000 : 25000000 * (div << 1));
  

  default: return 0; }

How about just

return 25000000 * (div + (div >> 1) + 1);