After starting or setting the rate of a PLL, the enable bit must be set.

This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

(no changes since v1)

drivers/clk/kendryte/pll.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index ab6d75d585..f198920113 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk) k210_pll_waitfor_lock(pll);

reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; writel(reg, pll->reg);

return 0; @@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk) writel(reg, pll->reg);

reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; writel(reg, pll->reg); return 0; }

This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it.

Reported-by: Damien Le Moal Damien.LeMoal@wdc.com Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v2: - New

drivers/clk/kendryte/pll.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index f198920113..d46fd0ebbf 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -512,7 +512,8 @@ static int k210_pll_enable(struct clk *clk) struct k210_pll *pll = to_k210_pll(clk); u32 reg = readl(pll->reg);

- if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET)) + if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) && + !(reg & K210_PLL_RESET)) return 0;

reg |= K210_PLL_PWRD;

Now that the PLLs get properly enabled, the bypass clock is no longer necessary.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v2: - New

drivers/clk/kendryte/Makefile | 2 +- drivers/clk/kendryte/bypass.c | 273 ---------------------------------- drivers/clk/kendryte/clk.c | 43 ++---- include/kendryte/bypass.h | 31 ---- 4 files changed, 15 insertions(+), 334 deletions(-) delete mode 100644 drivers/clk/kendryte/bypass.c delete mode 100644 include/kendryte/bypass.h

diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile index 6fb68253ae..d26bce954f 100644 --- a/drivers/clk/kendryte/Makefile +++ b/drivers/clk/kendryte/Makefile @@ -1 +1 @@ -obj-y += bypass.o clk.o pll.o +obj-y += clk.o pll.o diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c deleted file mode 100644 index 5f1986f2cb..0000000000 --- a/drivers/clk/kendryte/bypass.c +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Sean Anderson seanga2@gmail.com - */ - -#define LOG_CATEGORY UCLASS_CLK - -#include <common.h> -#include <clk.h> -#include <clk-uclass.h> -#include <dm.h> -#include <log.h> -#include <kendryte/bypass.h> -#include <linux/clk-provider.h> -#include <linux/err.h> - -#define CLK_K210_BYPASS "k210_clk_bypass" - -/* - * This is a small driver to do a software bypass of a clock if hardware bypass - * is not working. I have tried to write this in a generic fashion, so that it - * could be potentially broken out of the kendryte code at some future date. - * - * Say you have the following clock configuration - * - * +---+ +---+ - * |osc| |pll| - * +---+ +---+ - * ^ - * /| - * / | - * / | - * / | - * / | - * +---+ +---+ - * |clk| |clk| - * +---+ +---+ - * - * But the pll does not have a bypass, so when you configure the pll, the - * configuration needs to change to look like - * - * +---+ +---+ - * |osc| |pll| - * +---+ +---+ - * ^ - * |\ - * | \ - * | \ - * | \ - * | \ - * +---+ +---+ - * |clk| |clk| - * +---+ +---+ - * - * To set this up, create a bypass clock with bypassee=pll and alt=osc. When - * creating the child clocks, set their parent to the bypass clock. After - * creating all the children, call k210_bypass_setchildren(). - */ - -static int k210_bypass_dobypass(struct k210_bypass *bypass) -{ - int ret, i; - - /* - * If we already have saved parents, then the children are already - * bypassed - */ - if (bypass->child_count && bypass->saved_parents[0]) - return 0; - - for (i = 0; i < bypass->child_count; i++) { - struct clk *child = bypass->children[i]; - struct clk *parent = clk_get_parent(child); - - if (IS_ERR(parent)) { - for (; i; i--) - bypass->saved_parents[i] = NULL; - return PTR_ERR(parent); - } - bypass->saved_parents[i] = parent; - } - - for (i = 0; i < bypass->child_count; i++) { - struct clk *child = bypass->children[i]; - - ret = clk_set_parent(child, bypass->alt); - if (ret) { - for (; i; i--) - clk_set_parent(bypass->children[i], - bypass->saved_parents[i]); - for (i = 0; i < bypass->child_count; i++) - bypass->saved_parents[i] = NULL; - return ret; - } - } - - return 0; -} - -static int k210_bypass_unbypass(struct k210_bypass *bypass) -{ - int err, ret, i; - - if (!bypass->child_count && !bypass->saved_parents[0]) { - log_warning("Cannot unbypass children; dobypass not called first\n"); - return 0; - } - - ret = 0; - for (i = 0; i < bypass->child_count; i++) { - err = clk_set_parent(bypass->children[i], - bypass->saved_parents[i]); - if (err) - ret = err; - bypass->saved_parents[i] = NULL; - } - return ret; -} - -static ulong k210_bypass_get_rate(struct clk *clk) -{ - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - if (ops->get_rate) - return ops->get_rate(bypass->bypassee); - else - return clk_get_parent_rate(bypass->bypassee); -} - -static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate) -{ - int ret; - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - /* Don't bother bypassing if we aren't going to set the rate */ - if (!ops->set_rate) - return k210_bypass_get_rate(clk); - - ret = k210_bypass_dobypass(bypass); - if (ret) - return ret; - - ret = ops->set_rate(bypass->bypassee, rate); - if (ret < 0) - return ret; - - return k210_bypass_unbypass(bypass); -} - -static int k210_bypass_set_parent(struct clk *clk, struct clk *parent) -{ - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - if (ops->set_parent) - return ops->set_parent(bypass->bypassee, parent); - else - return -ENOTSUPP; -} - -/* - * For these next two functions, do the bypassing even if there is no - * en-/-disable function, since the bypassing itself can be observed in between - * calls. - */ -static int k210_bypass_enable(struct clk *clk) -{ - int ret; - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - ret = k210_bypass_dobypass(bypass); - if (ret) - return ret; - - if (ops->enable) - ret = ops->enable(bypass->bypassee); - else - ret = 0; - if (ret) - return ret; - - return k210_bypass_unbypass(bypass); -} - -static int k210_bypass_disable(struct clk *clk) -{ - int ret; - struct k210_bypass *bypass = to_k210_bypass(clk); - const struct clk_ops *ops = bypass->bypassee_ops; - - ret = k210_bypass_dobypass(bypass); - if (ret) - return ret; - - if (ops->disable) - return ops->disable(bypass->bypassee); - else - return 0; -} - -static const struct clk_ops k210_bypass_ops = { - .get_rate = k210_bypass_get_rate, - .set_rate = k210_bypass_set_rate, - .set_parent = k210_bypass_set_parent, - .enable = k210_bypass_enable, - .disable = k210_bypass_disable, -}; - -int k210_bypass_set_children(struct clk *clk, struct clk **children, - size_t child_count) -{ - struct k210_bypass *bypass = to_k210_bypass(clk); - - kfree(bypass->saved_parents); - if (child_count) { - bypass->saved_parents = - kcalloc(child_count, sizeof(struct clk *), GFP_KERNEL); - if (!bypass->saved_parents) - return -ENOMEM; - } - bypass->child_count = child_count; - bypass->children = children; - - return 0; -} - -struct clk *k210_register_bypass_struct(const char *name, - const char *parent_name, - struct k210_bypass *bypass) -{ - int ret; - struct clk *clk; - - clk = &bypass->clk; - - ret = clk_register(clk, CLK_K210_BYPASS, name, parent_name); - if (ret) - return ERR_PTR(ret); - - bypass->bypassee->dev = clk->dev; - return clk; -} - -struct clk *k210_register_bypass(const char *name, const char *parent_name, - struct clk *bypassee, - const struct clk_ops *bypassee_ops, - struct clk *alt) -{ - struct clk *clk; - struct k210_bypass *bypass; - - bypass = kzalloc(sizeof(*bypass), GFP_KERNEL); - if (!bypass) - return ERR_PTR(-ENOMEM); - - bypass->bypassee = bypassee; - bypass->bypassee_ops = bypassee_ops; - bypass->alt = alt; - - clk = k210_register_bypass_struct(name, parent_name, bypass); - if (IS_ERR(clk)) - kfree(bypass); - return clk; -} - -U_BOOT_DRIVER(k210_bypass) = { - .name = CLK_K210_BYPASS, - .id = UCLASS_CLK, - .ops = &k210_bypass_ops, -}; diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index bb196961af..e657efc572 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -11,7 +11,6 @@ #include <log.h> #include <mapmem.h>

-#include <kendryte/bypass.h> #include <kendryte/pll.h>

/* All methods are delegated to CCF clocks */ @@ -347,10 +346,6 @@ static const struct k210_comp_params k210_comps[] = { #undef COMP_NOMUX_ID #undef COMP_LIST

-static struct clk *k210_bypass_children = { - NULL, -}; - /* Helper functions to create sub-clocks */ static struct clk_mux *k210_create_mux(const struct k210_mux_params *params, void *base) @@ -482,7 +477,7 @@ static int k210_clk_probe(struct udevice *dev) { int ret; const char *in0; - struct clk *in0_clk, *bypass; + struct clk *in0_clk; struct clk_mux *mux; struct clk_divider *div; struct k210_pll *pll; @@ -516,17 +511,13 @@ static int k210_clk_probe(struct udevice *dev) aclk_sels[0] = in0; pll2_sels[0] = in0;

- /* - * All PLLs have a broken bypass, but pll0 has the CPU downstream, so we - * need to manually reparent it whenever we configure pll0 - */ - pll = k210_create_pll(&k210_plls[0], base); - if (pll) { - bypass = k210_register_bypass("pll0", in0, &pll->clk, - &k210_pll_ops, in0_clk); - clk_dm(K210_CLK_PLL0, bypass); - } else { - return -ENOMEM; + { + const struct k210_pll_params *params = &k210_plls[0]; + + clk_dm(K210_CLK_PLL0, + k210_register_pll("pll0", in0, base + params->off, + base + params->lock_off, params->shift, + params->width)); }

{ @@ -565,18 +556,12 @@ static int k210_clk_probe(struct udevice *dev) free(mux); free(div); } else { - struct clk *aclk = - clk_register_composite(NULL, "aclk", aclk_sels, - ARRAY_SIZE(aclk_sels), - &mux->clk, &clk_mux_ops, - &div->clk, &clk_divider_ops, - NULL, NULL, 0); - clk_dm(K210_CLK_ACLK, aclk); - if (!IS_ERR(aclk)) { - k210_bypass_children = aclk; - k210_bypass_set_children(bypass, - &k210_bypass_children, 1); - } + clk_dm(K210_CLK_ACLK, + clk_register_composite(NULL, "aclk", aclk_sels, + ARRAY_SIZE(aclk_sels), + &mux->clk, &clk_mux_ops, + &div->clk, &clk_divider_ops, + NULL, NULL, 0)); }

#define REGISTER_COMP(id, name) \ diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h deleted file mode 100644 index ab85bbcbfc..0000000000 --- a/include/kendryte/bypass.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020 Sean Anderson seanga2@gmail.com - */ -#ifndef K210_BYPASS_H -#define K210_BYPASS_H - -struct clk; - -struct k210_bypass { - struct clk clk; - struct clk **children; /* Clocks to reparent */ - struct clk **saved_parents; /* Parents saved over en-/dis-able */ - struct clk *bypassee; /* Clock to bypass */ - const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */ - struct clk *alt; /* Clock to set children to when bypassing */ - size_t child_count; -}; - -#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk) - -int k210_bypass_set_children(struct clk *clk, struct clk **children, - size_t child_count); -struct clk *k210_register_bypass_struct(const char *name, - const char *parent_name, - struct k210_bypass *bypass); -struct clk *k210_register_bypass(const char *name, const char *parent_name, - struct clk *bypassee, - const struct clk_ops *bypassee_ops, - struct clk *alt); -#endif /* K210_BYPASS_H */

No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v2: - New

drivers/clk/kendryte/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index 88a997e80b..28e21d0bf9 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -625,7 +625,7 @@ static int k210_clk_probe(struct udevice *dev)

/* The MTIME register in CLINT runs at one 50th the CPU clock speed */ clk_dm(K210_CLK_CLINT, - clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50)); + clk_register_fixed_factor(NULL, "clint", "aclk", 0, 1, 50));

return 0; }

This adds a driver to handle enabling the clock for the AI SRAM. This was previously done in board_init, but it needs to happen before relocation now. An alternative would be to move this to board_init_early_f, but by doing it this way we can use clk_bulk.

Signed-off-by: Sean Anderson seanga2@gmail.com Reviewed-by: Simon Glass sjg@chromium.org ---

(no changes since v1)

MAINTAINERS | 1 + drivers/ram/Kconfig | 7 ++++++ drivers/ram/Makefile | 1 + drivers/ram/kendryte.c | 56 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 65 insertions(+) create mode 100644 drivers/ram/kendryte.c

diff --git a/MAINTAINERS b/MAINTAINERS index fb9ba37984..166acb30c2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -938,6 +938,7 @@ F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt F: doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt F: drivers/clk/kendryte/ F: drivers/pinctrl/kendryte/ +F: drivers/ram/kendryte.c F: include/kendryte/

RNG diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index a270e13b26..075e6b5cd7 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -73,6 +73,13 @@ config IMXRT_SDRAM to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the SEMC.

+config K210_SRAM + bool "Enable Kendryte K210 SRAM support" + depends on RAM + help + The Kendryte K210 has three banks of SRAM. This driver does the + necessary initialization. + source "drivers/ram/aspeed/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 209a78c06f..fdc9bbeb1f 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/

obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o +obj-$(CONFIG_K210_SRAM) += kendryte.o

obj-$(CONFIG_RAM_SIFIVE) += sifive/

diff --git a/drivers/ram/kendryte.c b/drivers/ram/kendryte.c new file mode 100644 index 0000000000..50818bf005 --- /dev/null +++ b/drivers/ram/kendryte.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sean Anderson seanga2@gmail.com + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> + +static int k210_sram_probe(struct udevice *dev) +{ + int ret; + struct clk_bulk clocks; + + /* Relocate as high as possible to leave more space to load payloads */ + ret = fdtdec_setup_mem_size_base_highest(); + if (ret) + return ret; + + /* Enable ram bank clocks */ + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + + return 0; +} + +static int k210_sram_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = gd->ram_base; + info->size = gd->ram_size; + + return 0; +} + +static struct ram_ops k210_sram_ops = { + .get_info = k210_sram_get_info, +}; + +static const struct udevice_id k210_sram_ids[] = { + { .compatible = "kendryte,k210-sram" }, + { } +}; + +U_BOOT_DRIVER(fu540_ddr) = { + .name = "k210_sram", + .id = UCLASS_RAM, + .of_match = k210_sram_ids, + .ops = &k210_sram_ops, + .probe = k210_sram_probe, +};

Other RISC-V targets should not have RAM_SIFIVE enabled by default.

Signed-off-by: Sean Anderson seanga2@gmail.com Reviewed-by: Pragnesh Patel pragnesh.patel@openfive.com ---

(no changes since v1)

drivers/ram/sifive/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig index 6aca22ab2a..b24153d971 100644 --- a/drivers/ram/sifive/Kconfig +++ b/drivers/ram/sifive/Kconfig @@ -1,7 +1,7 @@ config RAM_SIFIVE bool "Ram drivers support for SiFive SoCs" depends on RAM && RISCV - default y + default y if TARGET_SIFIVE_FU540 help This enables support for ram drivers of SiFive SoCs.

If CONFIG_RAM is enabled, use the ram device to get the base/size of memory. This provides an easy way for boards/cpus to hook into the dram_init logic, without needing to provide a second SYS_CPU.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

(no changes since v1)

arch/riscv/cpu/generic/dram.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)

diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 1dc77efeca..fbcd4ddf5f 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -4,15 +4,41 @@ */

#include <common.h> +#include <dm.h> #include <fdtdec.h> #include <init.h> +#include <log.h> +#include <ram.h> #include <linux/sizes.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void) { +#if CONFIG_IS_ENABLED(RAM) + int ret; + struct ram_info info; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + ret = ram_get_info(dev, &info); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + + gd->ram_base = info.base; + gd->ram_size = info.size; + + return 0; +#else return fdtdec_setup_mem_size_base(); +#endif }

int dram_init_banksize(void)

CONFIG_SYS_SDRAM_{BASE,SIZE} are no longer necessary. The default get_effective_memsize will also work. The clock driver creates a bunch of devices, so we need to increase the pre-reloc malloc arena.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

(no changes since v1)

board/sipeed/maix/Kconfig | 2 ++ board/sipeed/maix/maix.c | 26 -------------------------- configs/sipeed_maix_bitm_defconfig | 1 + include/configs/sipeed-maix.h | 4 ---- 4 files changed, 3 insertions(+), 30 deletions(-)

diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index 4c42dd2087..ba61810079 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -42,6 +42,8 @@ config BOARD_SPECIFIC_OPTIONS imply CLK_K210 imply DM_RESET imply RESET_SYSCON + imply RAM + imply K210_SRAM imply SYSRESET imply SYSRESET_SYSCON imply PINCTRL diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index cbcb23cf5c..1b6f8a5115 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -9,33 +9,7 @@ #include <fdt_support.h> #include <asm/io.h>

-phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_SDRAM_SIZE; -} - int board_init(void) { - int ret, i; - const char * const banks[] = { "sram0", "sram1", "airam" }; - ofnode memory; - struct clk clk; - - /* Enable RAM clocks */ - memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram"); - if (ofnode_equal(memory, ofnode_null())) - return -ENOENT; - - for (i = 0; i < ARRAY_SIZE(banks); i++) { - ret = clk_get_by_name_nodev(memory, banks[i], &clk); - if (ret) - continue; - - ret = clk_enable(&clk); - clk_free(&clk); - if (ret) - return ret; - } - return 0; } diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 459bf0d530..d0100ad9e9 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_TARGET_SIPEED_MAIX=y CONFIG_ARCH_RV64I=y CONFIG_STACK_SIZE=0x100000 diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 36ff522e4b..81956cccfd 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -14,10 +14,6 @@ #define CONFIG_SYS_MALLOC_LEN SZ_128K #define CONFIG_SYS_CACHELINE_SIZE 64

-#define CONFIG_SYS_SDRAM_BASE 0x80000000 -/* Don't relocate into AI ram since it isn't set up yet */ -#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M) - /* For early init */ #define K210_SYSCTL_BASE 0x50440000

This is more consistent with the naming of other ram banks, and matches what Linux is doing.

Reported-by: Damien Le Moal Damien.LeMoal@wdc.com Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v2: - New

arch/riscv/dts/k210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 86d50f14e5..05f345f683 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -86,11 +86,11 @@ reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; - reg-names = "sram0", "sram1", "airam"; + reg-names = "sram0", "sram1", "aisram"; clocks = <&sysclk K210_CLK_SRAM0>, <&sysclk K210_CLK_SRAM1>, <&sysclk K210_CLK_PLL1>; - clock-names = "sram0", "sram1", "airam"; + clock-names = "sram0", "sram1", "aisram"; u-boot,dm-pre-reloc; };

Testing showed that disabling AI while leaving PLL1 enabled disabled the aisram. This suggests that AI is a more appropriate clock for that ram bank.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

Changes in v2: - New

arch/riscv/dts/k210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 05f345f683..600fce26af 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -89,7 +89,7 @@ reg-names = "sram0", "sram1", "aisram"; clocks = <&sysclk K210_CLK_SRAM0>, <&sysclk K210_CLK_SRAM1>, - <&sysclk K210_CLK_PLL1>; + <&sysclk K210_CLK_AI>; clock-names = "sram0", "sram1", "aisram"; u-boot,dm-pre-reloc; };

It is no longer necessary to disallow ai ram, since it is enabled by the sram driver.

Signed-off-by: Sean Anderson seanga2@gmail.com ---

(no changes since v1)

arch/riscv/dts/k210.dtsi | 12 ------------ 1 file changed, 12 deletions(-)

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 600fce26af..66dd438d50 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -94,17 +94,6 @@ u-boot,dm-pre-reloc; };

- reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ai_reserved: ai@80600000 { - reg = <0x80600000 0x200000>; - reusable; - }; - }; - clocks { in0: osc { compatible = "fixed-clock"; @@ -179,7 +168,6 @@ reg = <0x40800000 0xc00000>; interrupts = <25>; clocks = <&sysclk K210_CLK_AI>; - memory-region = <&ai_reserved>; status = "disabled"; };