[PATCH v1 0/6] mips: octeon: Misc Octeon drivers, DT and Kconfig / defconfig updates
This patchset includes the following parts: - Octeon GPIO driver in v3 - New simple Octeon clk driver - DT updates (GPIO, I2C & CLK nodes) - Kconfig & defconfig updates
Thanks, Stefan
Changes in v1: - Removed common.h and reduced headers as suggested by Daniel
Stefan Roese (5): mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodes mips: octeon: dts: Add I2C DT nodes clk: clk_octeon: Add simple MIPS Octeon clock driver mips: octeon: dts: Add Octeon clock driver DT nodes mips: octeon: Update Octeon Kconfig and EBB7304 defconfig
Suneel Garapati (1): gpio: octeon_gpio: Add GPIO controller driver for Octeon
arch/mips/Kconfig | 7 +- arch/mips/dts/mrvl,cn73xx.dtsi | 56 +++++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 12 +- configs/octeon_ebb7304_defconfig | 4 + drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk_octeon.c | 72 +++++++ drivers/gpio/Kconfig | 10 + drivers/gpio/Makefile | 1 + drivers/gpio/octeon_gpio.c | 250 +++++++++++++++++++++++ include/dt-bindings/clock/octeon-clock.h | 12 ++ 11 files changed, 429 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/clk_octeon.c create mode 100644 drivers/gpio/octeon_gpio.c create mode 100644 include/dt-bindings/clock/octeon-clock.h
From: Suneel Garapati sgarapati@marvell.com
Add support for GPIO controllers found on Octeon II/III and Octeon TX TX2 SoC platforms.
Signed-off-by: Aaron Williams awilliams@marvell.com Signed-off-by: Suneel Garapati sgarapati@marvell.com Signed-off-by: Stefan Roese sr@denx.de Reviewed-by: Simon Glass sjg@chromium.org
---
Changes in v1: - Removed common.h and reduced headers as suggested by Daniel
drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/octeon_gpio.c | 250 +++++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 drivers/gpio/octeon_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0e8ad9530d..18cf918b94 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -335,6 +335,16 @@ config PIC32_GPIO help Say yes here to support Microchip PIC32 GPIOs.
+config OCTEON_GPIO + bool "Octeon II/III/TX/TX2 GPIO driver" + depends on DM_GPIO && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) + default y + help + Add support for the Marvell Octeon GPIO driver. This is used with + various Octeon parts such as Octeon II/III and OcteonTX/TX2. + Octeon II/III has 32 GPIOs (count defined via DT) and OcteonTX/TX2 + has 64 GPIOs (count defined via internal register). + config STM32_GPIO bool "ST STM32 GPIO driver" depends on DM_GPIO && (ARCH_STM32 || ARCH_STM32MP) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 7638259007..eb6364adb4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o +obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o diff --git a/drivers/gpio/octeon_gpio.c b/drivers/gpio/octeon_gpio.c new file mode 100644 index 0000000000..0a5e844bdf --- /dev/null +++ b/drivers/gpio/octeon_gpio.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav ajay.bhargav@einfochips.com + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + */ + +#include <dm.h> +#include <pci.h> +#include <pci_ids.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/compat.h> +#include <dt-bindings/gpio/gpio.h> + +/* Returns the bit value to write or read based on the offset */ +#define GPIO_BIT(x) BIT_ULL((x) & 0x3f) + +#define GPIO_RX_DAT 0x00 +#define GPIO_TX_SET 0x08 +#define GPIO_TX_CLR 0x10 +#define GPIO_CONST 0x90 /* OcteonTX only */ + +/* Offset to register-set for 2nd GPIOs (> 63), OcteonTX only */ +#define GPIO1_OFFSET 0x1400 + +/* GPIO_CONST register bits */ +#define GPIO_CONST_GPIOS_MASK GENMASK_ULL(7, 0) + +/* GPIO_BIT_CFG register bits */ +#define GPIO_BIT_CFG_TX_OE BIT_ULL(0) +#define GPIO_BIT_CFG_PIN_XOR BIT_ULL(1) +#define GPIO_BIT_CFG_INT_EN BIT_ULL(2) +#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK_ULL(26, 16) + +enum { + PROBE_PCI = 0, /* PCI based probing */ + PROBE_DT, /* DT based probing */ +}; + +struct octeon_gpio_data { + int probe; + u32 reg_offs; + u32 gpio_bit_cfg_offs; +}; + +struct octeon_gpio { + void __iomem *base; + const struct octeon_gpio_data *data; +}; + +/* Returns the offset to the output register based on the offset and value */ +static u32 gpio_tx_reg(int offset, int value) +{ + u32 ret; + + ret = value ? GPIO_TX_SET : GPIO_TX_CLR; + if (offset > 63) + ret += GPIO1_OFFSET; + + return ret; +} + +/* Returns the offset to the input data register based on the offset */ +static u32 gpio_rx_dat_reg(int offset) +{ + u32 ret; + + ret = GPIO_RX_DAT; + if (offset > 63) + ret += GPIO1_OFFSET; + + return ret; +} + +static int octeon_gpio_dir_input(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u)\n", __func__, dev->name, offset); + clrbits_64(gpio->base + gpio->data->gpio_bit_cfg_offs + 8 * offset, + GPIO_BIT_CFG_TX_OE | GPIO_BIT_CFG_PIN_XOR | + GPIO_BIT_CFG_INT_EN | GPIO_BIT_CFG_PIN_SEL_MASK); + + return 0; +} + +static int octeon_gpio_dir_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value); + writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs + + gpio_tx_reg(offset, value)); + + clrsetbits_64(gpio->base + gpio->data->gpio_bit_cfg_offs + 8 * offset, + GPIO_BIT_CFG_PIN_SEL_MASK | GPIO_BIT_CFG_INT_EN, + GPIO_BIT_CFG_TX_OE); + + return 0; +} + +static int octeon_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + u64 reg = readq(gpio->base + gpio->data->reg_offs + + gpio_rx_dat_reg(offset)); + + debug("%s(%s, %u): value: %d\n", __func__, dev->name, offset, + !!(reg & GPIO_BIT(offset))); + + return !!(reg & GPIO_BIT(offset)); +} + +static int octeon_gpio_set_value(struct udevice *dev, + unsigned int offset, int value) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + + debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value); + writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs + + gpio_tx_reg(offset, value)); + + return 0; +} + +static int octeon_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct octeon_gpio *gpio = dev_get_priv(dev); + u64 val = readq(gpio->base + gpio->data->gpio_bit_cfg_offs + + 8 * offset); + int pin_sel; + + debug("%s(%s, %u): GPIO_BIT_CFG: 0x%llx\n", __func__, dev->name, + offset, val); + pin_sel = FIELD_GET(GPIO_BIT_CFG_PIN_SEL_MASK, val); + if (pin_sel) + return GPIOF_FUNC; + else if (val & GPIO_BIT_CFG_TX_OE) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static int octeon_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + if (args->args_count < 1) + return -EINVAL; + + desc->offset = args->args[0]; + desc->flags = 0; + if (args->args_count > 1) { + if (args->args[1] & GPIO_ACTIVE_LOW) + desc->flags |= GPIOD_ACTIVE_LOW; + /* In the future add tri-state flag support */ + } + return 0; +} + +static const struct dm_gpio_ops octeon_gpio_ops = { + .direction_input = octeon_gpio_dir_input, + .direction_output = octeon_gpio_dir_output, + .get_value = octeon_gpio_get_value, + .set_value = octeon_gpio_set_value, + .get_function = octeon_gpio_get_function, + .xlate = octeon_gpio_xlate, +}; + +static int octeon_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct octeon_gpio *priv = dev_get_priv(dev); + char *end; + + priv->data = (const struct octeon_gpio_data *)dev_get_driver_data(dev); + + if (priv->data->probe == PROBE_PCI) { + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + uc_priv->gpio_count = readq(priv->base + + priv->data->reg_offs + GPIO_CONST) & + GPIO_CONST_GPIOS_MASK; + } else { + priv->base = dev_remap_addr(dev); + uc_priv->gpio_count = ofnode_read_u32_default(dev->node, + "nr-gpios", 32); + } + + if (!priv->base) { + debug("%s(%s): Could not get base address\n", + __func__, dev->name); + return -ENODEV; + } + + uc_priv->bank_name = strdup(dev->name); + end = strchr(uc_priv->bank_name, '@'); + end[0] = 'A' + dev->seq; + end[1] = '\0'; + + debug("%s(%s): base address: %p, pin count: %d\n", + __func__, dev->name, priv->base, uc_priv->gpio_count); + + return 0; +} + +static const struct octeon_gpio_data gpio_octeon_data = { + .probe = PROBE_DT, + .reg_offs = 0x80, + .gpio_bit_cfg_offs = 0x100, +}; + +static const struct octeon_gpio_data gpio_octeontx_data = { + .probe = PROBE_PCI, + .reg_offs = 0x00, + .gpio_bit_cfg_offs = 0x400, +}; + +static const struct udevice_id octeon_gpio_ids[] = { + { .compatible = "cavium,thunder-8890-gpio", + .data = (ulong)&gpio_octeontx_data }, + { .compatible = "cavium,octeon-7890-gpio", + .data = (ulong)&gpio_octeon_data }, + { } +}; + +U_BOOT_DRIVER(octeon_gpio) = { + .name = "octeon_gpio", + .id = UCLASS_GPIO, + .of_match = of_match_ptr(octeon_gpio_ids), + .probe = octeon_gpio_probe, + .priv_auto_alloc_size = sizeof(struct octeon_gpio), + .ops = &octeon_gpio_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +static struct pci_device_id octeon_gpio_supported[] = { + { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_GPIO), + .driver_data = (ulong)&gpio_octeontx_data }, + { }, +}; + +U_BOOT_PCI_DEVICE(octeon_gpio, octeon_gpio_supported);
Add the Octeon GPIO DT node to the dtsi file.
Signed-off-by: Stefan Roese sr@denx.de ---
arch/mips/dts/mrvl,cn73xx.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi index a7bd55f8ad..8d32a49795 100644 --- a/arch/mips/dts/mrvl,cn73xx.dtsi +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -38,6 +38,32 @@ #size-cells = <1>; };
+ gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-7890-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + nr-gpios = <32>; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <0x03000 4>, <0x03001 4>, + <0x03002 4>, <0x03003 4>, + <0x03004 4>, <0x03005 4>, + <0x03006 4>, <0x03007 4>, + <0x03008 4>, <0x03009 4>, + <0x0300a 4>, <0x0300b 4>, + <0x0300c 4>, <0x0300d 4>, + <0x0300e 4>, <0x0300f 4>; + }; + reset: reset@1180006001600 { compatible = "mrvl,cn7xxx-rst"; reg = <0x11800 0x06001600 0x0 0x200>;
Add I2C DT nodes to the Octeon dts / dtsi files.
Signed-off-by: Stefan Roese sr@denx.de ---
arch/mips/dts/mrvl,cn73xx.dtsi | 20 ++++++++++++++++++++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 10 ++++++++++ 2 files changed, 30 insertions(+)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi index 8d32a49795..4c7b6e4160 100644 --- a/arch/mips/dts/mrvl,cn73xx.dtsi +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -86,5 +86,25 @@ reg-shift = <3>; interrupts = <0x08040 4>; }; + + i2c0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>; + clock-frequency = <100000>; + }; + + i2c1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7890-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + /* INT_ST, INT_TS, INT_CORE */ + interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>; + clock-frequency = <100000>; + }; }; }; diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts index 4e9c2de7d4..096e5c8f66 100644 --- a/arch/mips/dts/mrvl,octeon-ebb7304.dts +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -94,3 +94,13 @@ &uart0 { clock-frequency = <1200000000>; }; + +&i2c0 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +}; + +&i2c1 { + u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */ + clock-frequency = <100000>; +};
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC family. Its for IO clock rate passing via DT in some of the Octeon driver, like I2C. So that we don't need to use the non-mainline API octeon_get_io_clock().
Signed-off-by: Stefan Roese sr@denx.de Cc: Lukasz Majewski lukma@denx.de ---
drivers/clk/Kconfig | 7 +++ drivers/clk/Makefile | 1 + drivers/clk/clk_octeon.c | 72 ++++++++++++++++++++++++ include/dt-bindings/clock/octeon-clock.h | 12 ++++ 4 files changed, 92 insertions(+) create mode 100644 drivers/clk/clk_octeon.c create mode 100644 include/dt-bindings/clock/octeon-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 82cb1874e1..6003e140b5 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -83,6 +83,13 @@ config CLK_INTEL set up by U-Boot itself but only statically. Thus the driver does not support changing clock rates, only querying them.
+config CLK_OCTEON + bool "Clock controller driver for Marvell MIPS Octeon" + depends on CLK && ARCH_OCTEON + default y + help + Enable this to support the clocks on Octeon MIPS platforms. + config CLK_STM32F bool "Enable clock driver support for STM32F family" depends on CLK && (STM32F7 || STM32F4) diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d911954581..cda4b4b605 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_K210) += kendryte/ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o +obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ diff --git a/drivers/clk/clk_octeon.c b/drivers/clk/clk_octeon.c new file mode 100644 index 0000000000..fd559e05fc --- /dev/null +++ b/drivers/clk/clk_octeon.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Stefan Roese sr@denx.de + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <dt-bindings/clock/octeon-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct octeon_clk_priv { + u64 core_clk; + u64 io_clk; +}; + +static int octeon_clk_enable(struct clk *clk) +{ + /* Nothing to do on Octeon */ + return 0; +} + +static ulong octeon_clk_get_rate(struct clk *clk) +{ + struct octeon_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case OCTEON_CLK_CORE: + return priv->core_clk; + + case OCTEON_CLK_IO: + return priv->io_clk; + + default: + return 0; + } + + return 0; +} + +static struct clk_ops octeon_clk_ops = { + .enable = octeon_clk_enable, + .get_rate = octeon_clk_get_rate, +}; + +static const struct udevice_id octeon_clk_ids[] = { + { .compatible = "mrvl,octeon-clk" }, + { /* sentinel */ } +}; + +static int octeon_clk_probe(struct udevice *dev) +{ + struct octeon_clk_priv *priv = dev_get_priv(dev); + + /* + * The clock values are already read into GD, lets just store them + * in priv data + */ + priv->core_clk = gd->cpu_clk; + priv->io_clk = gd->bus_clk; + + return 0; +} + +U_BOOT_DRIVER(clk_octeon) = { + .name = "clk_octeon", + .id = UCLASS_CLK, + .of_match = octeon_clk_ids, + .ops = &octeon_clk_ops, + .probe = octeon_clk_probe, + .priv_auto_alloc_size = sizeof(struct octeon_clk_priv), +}; diff --git a/include/dt-bindings/clock/octeon-clock.h b/include/dt-bindings/clock/octeon-clock.h new file mode 100644 index 0000000000..34e6a3bf41 --- /dev/null +++ b/include/dt-bindings/clock/octeon-clock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Stefan Roese sr@denx.de + */ + +#ifndef __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H +#define __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H + +#define OCTEON_CLK_CORE 0 +#define OCTEON_CLK_IO 1 + +#endif /* __DT_BINDINGS_CLOCK_OCTEON_CLOCK_H */
This patch adds the DT nodes for the Octeon clock support via the common clk_ API.
Signed-off-by: Stefan Roese sr@denx.de ---
arch/mips/dts/mrvl,cn73xx.dtsi | 10 ++++++++++ arch/mips/dts/mrvl,octeon-ebb7304.dts | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi index 4c7b6e4160..7c0a8d73f0 100644 --- a/arch/mips/dts/mrvl,cn73xx.dtsi +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/clock/octeon-clock.h> + / { #address-cells = <2>; #size-cells = <2>; @@ -38,6 +40,12 @@ #size-cells = <1>; };
+ clk: clock { + compatible = "mrvl,octeon-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + gpio: gpio-controller@1070000000800 { #gpio-cells = <2>; compatible = "cavium,octeon-7890-gpio"; @@ -95,6 +103,7 @@ /* INT_ST, INT_TS, INT_CORE */ interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>; clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; };
i2c1: i2c@1180000001200 { @@ -105,6 +114,7 @@ /* INT_ST, INT_TS, INT_CORE */ interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>; clock-frequency = <100000>; + clocks = <&clk OCTEON_CLK_IO>; }; }; }; diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts index 096e5c8f66..c229aa5fc0 100644 --- a/arch/mips/dts/mrvl,octeon-ebb7304.dts +++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts @@ -5,7 +5,7 @@
/dts-v1/;
-/include/ "mrvl,cn73xx.dtsi" +#include "mrvl,cn73xx.dtsi"
/ { model = "cavium,ebb7304";
This patch selects DM_PCI, DM_GPIO and DM_SPI for MIPS Octeon. It also enables PCI and SPI and the matching commands in the EBB7304 defconfig file.
This needs to be done in one patch, as the Kconfig change depends on the defconfig change and vice versa.
Signed-off-by: Stefan Roese sr@denx.de
---
arch/mips/Kconfig | 7 +++++-- configs/octeon_ebb7304_defconfig | 4 ++++ 2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 997e145450..52a49a8541 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -112,9 +112,12 @@ config ARCH_OCTEON select DISPLAY_CPUINFO select DMA_ADDR_T_64BIT select DM - select DM_SERIAL - select DM_GPIO select DM_ETH + select DM_GPIO + select DM_I2C + select DM_PCI + select DM_SERIAL + select DM_SPI select MIPS_L2_CACHE select MIPS_MACH_EARLY_INIT select MIPS_TUNE_OCTEON3 diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index d810b1e45f..e6ab4e0211 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -12,6 +12,8 @@ CONFIG_ARCH_OCTEON=y CONFIG_DEBUG_UART=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y @@ -30,9 +32,11 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y # CONFIG_NETDEVICES is not set +CONFIG_PCI=y CONFIG_DEBUG_UART_SHIFT=3 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_OCTEON=y CONFIG_HEXDUMP=y
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Stefan Roese