-----Original Message----- From: thor.thayer@linux.intel.com thor.thayer@linux.intel.com Sent: Saturday, December 7, 2019 3:48 AM To: marex@denx.de; simon.k.r.goldschmidt@gmail.com; Tan, Ley Foon ley.foon.tan@intel.com Cc: albert.u.boot@aribaud.net; Ang, Chee Hong chee.hong.ang@intel.com; Chee, Tien Fong tien.fong.chee@intel.com; u-boot@lists.denx.de; Thor Thayer thor.thayer@linux.intel.com Subject: [PATCHv2 1/2] arm: socfpga: stratix10: Enable SMMU access

From: Thor Thayer thor.thayer@linux.intel.com

Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM.

Signed-off-by: Thor Thayer thor.thayer@linux.intel.com

Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com

---

v2 Rebase patch on top of pending patchset [PATCH v8 00/19] Add Intel Agilex SoC support https://patchwork.ozlabs.org/cover/1201373/

---

arch/arm/mach-socfpga/include/mach/firewall.h | 7 +++++++ drivers/ddr/altera/sdram_s10.c | 14 ++++++++++++++ 2 files changed, 21 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 516bd1c0e1ec..430341bea14c 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys {

#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628

+#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0 +#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0

#define CCU_ADMASK_P_MASK BIT(0) #define CCU_ADMASK_NS_MASK BIT(1)

diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index fcab3ae3e4ba..a7bf82e4e5ce 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -104,6 +104,20 @@ int sdram_mmr_init_full(struct udevice *dev)

clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE 1E), CCU_ADBASE_DI_MASK);

• /* Enable access to DDR from TCU */
• clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE

0),

•      CCU_ADBASE_DI_MASK);
  

• clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE

1A),

•      CCU_ADBASE_DI_MASK);
  

• clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE

1B),

•      CCU_ADBASE_DI_MASK);
  

• clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE

1C),

•      CCU_ADBASE_DI_MASK);
  

• clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE

1D),

•      CCU_ADBASE_DI_MASK);
  

• clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE

1E),

•      CCU_ADBASE_DI_MASK);
  

• /* this enables nonsecure access to DDR */ /* mpuregion0addr_limit */ FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,

FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);

2.7.4

-----Original Message----- From: thor.thayer@linux.intel.com thor.thayer@linux.intel.com Sent: Saturday, December 7, 2019 3:48 AM To: marex@denx.de; simon.k.r.goldschmidt@gmail.com; Tan, Ley Foon ley.foon.tan@intel.com Cc: albert.u.boot@aribaud.net; Ang, Chee Hong chee.hong.ang@intel.com; Chee, Tien Fong tien.fong.chee@intel.com; u-boot@lists.denx.de; Thor Thayer thor.thayer@linux.intel.com Subject: [PATCHv2 2/2] ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access

From: Thor Thayer thor.thayer@linux.intel.com

The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled.

The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access.

Signed-off-by: Thor Thayer thor.thayer@linux.intel.com

Reviewed-by: Ley Foon Tan ley.foon.tan@intel.com

---

v2 New Patch. Rebase patch on top of pending patchset [PATCH v8 00/19] Add Intel Agilex SoC support https://patchwork.ozlabs.org/cover/1201373/

---

drivers/ddr/altera/sdram_agilex.c | 6 +++--- drivers/ddr/altera/sdram_s10.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index cc7679a6e4c1..0cbcd1405607 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -143,9 +143,6 @@ int sdram_mmr_init_full(struct udevice *dev) setbits_le32(plat->hmc + ERRINTEN, DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);

• /* Enable non-secure writes to HMC Adapter for SDRAM ECC
  

*/

• writel(FW_HMC_ADAPTOR_MPU_MASK,
  

FW_HMC_ADAPTOR_REG_ADDR);

• if (!cpu_has_been_warmreset()) sdram_init_ecc_bits(&bd); } else {

@@ -158,6 +155,9 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); }

• /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC

*/

• writel(FW_HMC_ADAPTOR_MPU_MASK,

FW_HMC_ADAPTOR_REG_ADDR);

• sdram_size_check(&bd);

  priv->info.base = bd.bi_dram[0].start; diff --git

a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index a7bf82e4e5ce..2b8889260f9f 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -306,9 +306,6 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);

• /* Enable non-secure writes to HMC Adapter for SDRAM ECC
  

*/

• writel(FW_HMC_ADAPTOR_MPU_MASK,
  

FW_HMC_ADAPTOR_REG_ADDR);

• /* Initialize memory content if not from warm reset */ if (!cpu_has_been_warmreset()) sdram_init_ecc_bits(&bd);

@@ -322,6 +319,9 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); }

• /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC

*/

• writel(FW_HMC_ADAPTOR_MPU_MASK,

FW_HMC_ADAPTOR_REG_ADDR);

• sdram_size_check(&bd);

  priv->info.base = bd.bi_dram[0].start;

-- 2.7.4