[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
From: Vaibhav Hiremath hvaibhav@ti.com
This patch adds basic support for the AM3517EVM. It includes: - Board int file (.c and .h) - Default configuration file - Updates for Makefile
Changes from V2: - Removed trailing spaces - Updated MAINTAINERS & MAKEALL for am3517_evm
Signed-off-by: Vaibhav Hiremath hvaibhav@ti.com Signed-off-by: Sanjeev Premi premi@ti.com --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + arch/arm/include/asm/arch-omap3/mux.h | 38 +++- board/logicpd/am3517evm/Makefile | 46 ++++ board/logicpd/am3517evm/am3517evm.c | 76 ++++++ board/logicpd/am3517evm/am3517evm.h | 405 +++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/config.mk | 30 +++ include/configs/am3517_evm.h | 296 ++++++++++++++++++++++++ 9 files changed, 898 insertions(+), 1 deletions(-) create mode 100644 board/logicpd/am3517evm/Makefile create mode 100644 board/logicpd/am3517evm/am3517evm.c create mode 100644 board/logicpd/am3517evm/am3517evm.h create mode 100644 board/logicpd/am3517evm/config.mk create mode 100644 include/configs/am3517_evm.h
diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..0bc65e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110
+Vaibhav Hiremath hvaibhav@ti.com + + am3517_evm ARM CORTEX-A8 (AM35x SoC) + -------------------------------------------------------------------------
Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index bb09627..cd59daa 100755 --- a/MAKEALL +++ b/MAKEALL @@ -641,6 +641,7 @@ LIST_ARM11=" \ ## ARM Cortex-A8 Systems ######################################################################### LIST_ARM_CORTEX_A8=" \ + am3517_evm \ devkit8000 \ mx51evk \ omap3_beagle \ diff --git a/Makefile b/Makefile index 2d96574..57b3491 100644 --- a/Makefile +++ b/Makefile @@ -3155,6 +3155,9 @@ SMN42_config : unconfig ## ARM CORTEX Systems #########################################################################
+am3517_evm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3 + devkit8000_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 0c01c73..ffeb982 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -283,7 +283,7 @@ /*Control and debug */ #define CONTROL_PADCONF_SYS_32K 0x0A04 #define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 #define CONTROL_PADCONF_SYS_BOOT0 0x0A0A #define CONTROL_PADCONF_SYS_BOOT1 0x0A0C #define CONTROL_PADCONF_SYS_BOOT2 0x0A0E @@ -337,6 +337,7 @@ #define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 #define CONTROL_PADCONF_ETK_D15_ES2 0x05FA /*Die to Die */ +#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 #define CONTROL_PADCONF_D2D_MCAD0 0x01E4 #define CONTROL_PADCONF_D2D_MCAD1 0x01E6 #define CONTROL_PADCONF_D2D_MCAD2 0x01E8 @@ -403,6 +404,41 @@ #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 #define CONTROL_PADCONF_SDRC_CKE0 0x0262 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 +/* AM3517 specific */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226
#define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile new file mode 100644 index 0000000..3a6b1a1 --- /dev/null +++ b/board/logicpd/am3517evm/Makefile @@ -0,0 +1,46 @@ +# +# Author: Vaibhav Hiremath hvaibhav@ti.com +# +# Based on ti/evm/Makefile +# +# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := am3517evm.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c new file mode 100644 index 0000000..2b912a9 --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.c @@ -0,0 +1,76 @@ +/* + * am3517evm.c - board file for TI's AM3517 family of devices. + * + * Author: Vaibhav Hiremath hvaibhav@ti.com + * + * Based on ti/evm/evm.c + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <i2c.h> +#include "am3517evm.h" + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Init i2c, ethernet, etc... (done here so udelay works) + */ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_AM3517EVM(); +} diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h new file mode 100644 index 0000000..68d746c --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.h @@ -0,0 +1,405 @@ +/* + * am3517evm.h - Header file for the AM3517 EVM. + * + * Author: Vaibhav Hiremath hvaibhav@ti.com + * + * Based on ti/evm/evm.h + * + * Copyright (C) 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "AM3517EVM Board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_AM3517EVM() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - ETH_nRESET*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + /* WriteProtect */\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ + /* - LCD_INI*/\ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ + /* - LCD_ENVDD */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ + /* - LCD_QVGA/nVGA */\ + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ + /* - LCD_RESB */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ + /* - LAN_INTR*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + /*SYS_nRESWARM */\ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + /* - GPIO30 */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + /* - PEN_IRQ */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk new file mode 100644 index 0000000..f7a35ce --- /dev/null +++ b/board/logicpd/am3517evm/config.mk @@ -0,0 +1,30 @@ +# +# Author: Vaibhav Hiremath hvaibhav@ti.com +# +# Based on ti/evm/config.mk +# +# Copyright (C) 2010 +# Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h new file mode 100644 index 0000000..63f853a --- /dev/null +++ b/include/configs/am3517_evm.h @@ -0,0 +1,296 @@ +/* + * am3517_evm.h - Default configuration for AM3517 EVM board. + * + * Author: Vaibhav Hiremath hvaibhav@ti.com + * + * Based on omap3_evm_config.h + * + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ + +#define CONFIG_EMIF4 1 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ +/* + * DDR related + */ +#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +#undef CONFIG_CMD_NET +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE uImage + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "AM3517_EVM # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND 1 +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#endif /* __CONFIG_H */ -- 1.6.2.4
-----Original Message----- From: Hiremath, Vaibhav Sent: Thursday, May 06, 2010 10:53 PM To: u-boot@lists.denx.de Cc: wd@denx.de; tom@bumblecow.com; Paulraj, Sandeep; Hiremath, Vaibhav; Premi, Sanjeev Subject: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
From: Vaibhav Hiremath hvaibhav@ti.com
This patch adds basic support for the AM3517EVM. It includes: - Board int file (.c and .h) - Default configuration file - Updates for Makefile
Changes from V2: - Removed trailing spaces - Updated MAINTAINERS & MAKEALL for am3517_evm
[Hiremath, Vaibhav] Denk,
If we do not have any further comments, can we merge these patches?
Thanks, Vaibhav
Signed-off-by: Vaibhav Hiremath hvaibhav@ti.com Signed-off-by: Sanjeev Premi premi@ti.com
MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + arch/arm/include/asm/arch-omap3/mux.h | 38 +++- board/logicpd/am3517evm/Makefile | 46 ++++ board/logicpd/am3517evm/am3517evm.c | 76 ++++++ board/logicpd/am3517evm/am3517evm.h | 405 +++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/config.mk | 30 +++ include/configs/am3517_evm.h | 296 ++++++++++++++++++++++++ 9 files changed, 898 insertions(+), 1 deletions(-) create mode 100644 board/logicpd/am3517evm/Makefile create mode 100644 board/logicpd/am3517evm/am3517evm.c create mode 100644 board/logicpd/am3517evm/am3517evm.h create mode 100644 board/logicpd/am3517evm/config.mk create mode 100644 include/configs/am3517_evm.h
diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..0bc65e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110
+Vaibhav Hiremath hvaibhav@ti.com
am3517_evm ARM CORTEX-A8 (AM35x SoC)
Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index bb09627..cd59daa 100755 --- a/MAKEALL +++ b/MAKEALL @@ -641,6 +641,7 @@ LIST_ARM11=" \ ## ARM Cortex-A8 Systems ######################################################################### LIST_ARM_CORTEX_A8=" \
am3517_evm \ devkit8000 \ mx51evk \ omap3_beagle \diff --git a/Makefile b/Makefile index 2d96574..57b3491 100644 --- a/Makefile +++ b/Makefile @@ -3155,6 +3155,9 @@ SMN42_config : unconfig ## ARM CORTEX Systems #########################################################################
+am3517_evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3devkit8000_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 0c01c73..ffeb982 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -283,7 +283,7 @@ /*Control and debug */ #define CONTROL_PADCONF_SYS_32K 0x0A04 #define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 #define CONTROL_PADCONF_SYS_BOOT0 0x0A0A #define CONTROL_PADCONF_SYS_BOOT1 0x0A0C #define CONTROL_PADCONF_SYS_BOOT2 0x0A0E @@ -337,6 +337,7 @@ #define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 #define CONTROL_PADCONF_ETK_D15_ES2 0x05FA /*Die to Die */ +#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 #define CONTROL_PADCONF_D2D_MCAD0 0x01E4 #define CONTROL_PADCONF_D2D_MCAD1 0x01E6 #define CONTROL_PADCONF_D2D_MCAD2 0x01E8 @@ -403,6 +404,41 @@ #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 #define CONTROL_PADCONF_SDRC_CKE0 0x0262 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 +/* AM3517 specific */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226
#define MUX_VAL(OFFSET,VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile new file mode 100644 index 0000000..3a6b1a1 --- /dev/null +++ b/board/logicpd/am3517evm/Makefile @@ -0,0 +1,46 @@ +# +# Author: Vaibhav Hiremath hvaibhav@ti.com +# +# Based on ti/evm/Makefile +# +# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).a
+COBJS := am3517evm.o
+SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)+clean:
rm -f $(OBJS)+distclean: clean
rm -f $(LIB) core *.bak $(obj).depend+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c new file mode 100644 index 0000000..2b912a9 --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.c @@ -0,0 +1,76 @@ +/*
- am3517evm.c - board file for TI's AM3517 family of devices.
- Author: Vaibhav Hiremath hvaibhav@ti.com
- Based on ti/evm/evm.c
- Copyright (C) 2010
- Texas Instruments Incorporated - http://www.ti.com/
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <i2c.h> +#include "am3517evm.h"
+/*
- Routine: board_init
- Description: Early hardware init.
- */
+int board_init(void) +{
DECLARE_GLOBAL_DATA_PTR;gpmc_init(); /* in SRAM or SDRAM, finish GPMC *//* board id for Linux */gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;/* boot param addr */gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);return 0;+}
+/*
- Routine: misc_init_r
- Description: Init i2c, ethernet, etc... (done here so udelay works)
- */
+int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);+#endif
dieid_num_r();return 0;+}
+/*
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers specific to the
hardware. Many pins need to be moved from protect to primary
mode.- */
+void set_muxconf_regs(void) +{
MUX_AM3517EVM();+} diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h new file mode 100644 index 0000000..68d746c --- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.h @@ -0,0 +1,405 @@ +/*
- am3517evm.h - Header file for the AM3517 EVM.
- Author: Vaibhav Hiremath hvaibhav@ti.com
- Based on ti/evm/evm.h
- Copyright (C) 2010
- Texas Instruments Incorporated - http://www.ti.com/
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_
+const omap3_sysinfo sysinfo = {
DDR_DISCRETE,"AM3517EVM Board","NAND",+};
+/*
- IEN - Input Enable
- IDIS - Input Disable
- PTD - Pull type Down
- PTU - Pull type Up
- DIS - Pull type selection is inactive
- EN - Pull type selection is active
- M0 - Mode 0
- The commented string gives the final mux configuration for that pin
- */
+#define MUX_AM3517EVM() \
/* SDRC */\MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \MUX_VAL(CP(SDRC_CKE0), (M0)) \MUX_VAL(CP(SDRC_CKE1), (M0)) \/*sdrc_strben_dly0*/\MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \/*sdrc_strben_dly1*/\MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \/* GPMC */\MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\/* - ETH_nRESET*/\MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \/* DSS */\MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \/* CAMERA */\MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\/* - CAM_RESET*/\MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \/* MMC */\MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \/* WriteProtect */\MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \\MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \/* McBSP */\MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \\MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \\MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \\MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\/* - LCD_INI*/\MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\/* - LCD_ENVDD */\MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\/* - LCD_QVGA/nVGA */\MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\/* - LCD_RESB */\/* UART */\MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \\MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \\MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \/* I2C */\MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \/* McSPI */\MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\/* - LAN_INTR*/\MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \\MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \/* CCDC */\MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \/* RMII */\MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \MUX_VAL(CP(RMII_RXER), (PTD | M0)) \MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \/* HECC */\MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \/* HSUSB */\MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \/* HDQ */\MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \/* Control and debug */\MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \/*SYS_nRESWARM */\MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \/* - GPIO30 */\MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\/* - PEN_IRQ */\MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\/* - VIO_1V8*/\MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \\MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \/* JTAG */\MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \/* ETK (ES2 onwards) */\MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \/* Die to Die */\MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \+#endif diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk new file mode 100644 index 0000000..f7a35ce --- /dev/null +++ b/board/logicpd/am3517evm/config.mk @@ -0,0 +1,30 @@ +# +# Author: Vaibhav Hiremath hvaibhav@ti.com +# +# Based on ti/evm/config.mk +# +# Copyright (C) 2010 +# Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved)
+# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h new file mode 100644 index 0000000..63f853a --- /dev/null +++ b/include/configs/am3517_evm.h @@ -0,0 +1,296 @@ +/*
- am3517_evm.h - Default configuration for AM3517 EVM board.
- Author: Vaibhav Hiremath hvaibhav@ti.com
- Based on omap3_evm_config.h
- Copyright (C) 2009 Texas Instruments Incorporated
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- High Level Configuration Options
- */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
+#define CONFIG_EMIF4 1 /* The chip has EMIF4 controller */
+#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h>
+/*
- Display CPU and Board information
- */
+#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1
+/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1)
+#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1
+/*
- Size of malloc() pool
- */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */+/*
- DDR related
- */
+#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
+/*
- Hardware drivers
- */
+/*
- NS16550 Configuration
- */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/*
- select serial console configuration
- */
+#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}+#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1
+/* commands to include */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#undef CONFIG_CMD_NET +/*
- Board NAND Info.
- */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access *//* nand at CS0 */+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+/* Environment information */ +#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTFILE uImage
+#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \"console=ttyS2,115200n8\0" \"mmcargs=setenv bootargs console=${console} " \"root=/dev/mmcblk0p2 rw " \"rootfstype=ext3 rootwait\0" \"nandargs=setenv bootargs console=${console} " \"root=/dev/mtdblock4 rw " \"rootfstype=jffs2\0" \"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \"bootscript=echo Running bootscript from mmc ...; " \"source ${loadaddr}\0" \"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \"mmcboot=echo Booting from mmc ...; " \"run mmcargs; " \"bootm ${loadaddr}\0" \"nandboot=echo Booting from nand ...; " \"run nandargs; " \"nand read ${loadaddr} 280000 400000; " \"bootm ${loadaddr}\0" \+#define CONFIG_BOOTCOMMAND \
"if mmc init; then " \"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loaduimage; then " \"run mmcboot; " \"else run nandboot; " \"fi; " \"fi; " \"else run nandboot; fi"+#define CONFIG_AUTO_COMPLETE 1 +/*
- Miscellaneous configurable options
- */
+#define V_PROMPT "AM3517_EVM # "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_MAXARGS 32 /* max number of command */
/* args */+/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */+/*
- AM3517 has 12 GP timers, they can be driven by the system clock
- (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- This rate is divided by a local divisor.
- */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000
+/*-----------------------------------------------------------------------
- Stack sizes
- The stack sizes are set up in start.S using the settings below
- */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif
+/*-----------------------------------------------------------------------
- Physical Memory Map
- */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1
+/*-----------------------------------------------------------------------
- FLASH and environment organization
- */
+/* **** PISMO SUPPORT *** */
+/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
+#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
/* on one chip */+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+#define CONFIG_SYS_FLASH_BASE boot_flash_base
+/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND 1 +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr
+/*-----------------------------------------------------------------------
- CFI FLASH driver setup
- */
+/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)+#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif
+#endif /* __CONFIG_H */
1.6.2.4
Dear hvaibhav@ti.com,
In message 1273166585-26101-1-git-send-email-hvaibhav@ti.com you wrote:
From: Vaibhav Hiremath hvaibhav@ti.com
This patch adds basic support for the AM3517EVM. It includes:
- Board int file (.c and .h)
- Default configuration file
- Updates for Makefile
Changes from V2:
- Removed trailing spaces
- Updated MAINTAINERS & MAKEALL for am3517_evm
Such comments do not belong into the commit message. Please place thes ebelow the "---" line:
Signed-off-by: Vaibhav Hiremath hvaibhav@ti.com Signed-off-by: Sanjeev Premi premi@ti.com
==> Comments should go here.
diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..0bc65e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110
+Vaibhav Hiremath hvaibhav@ti.com
- am3517_evm ARM CORTEX-A8 (AM35x SoC)
Please keep list sorted.
...
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 0c01c73..ffeb982 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h
...
+/* AM3517 specific */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
Board specific defoinitions should not be added to global header files. Please use a board specific header instead.
--- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.c @@ -0,0 +1,76 @@
...
+int board_init(void) +{
- DECLARE_GLOBAL_DATA_PTR;
This is bound to break. DECLARE_GLOBAL_DATA_PTR must always be used on file scope only; never use this on function scope. Please check all your code.
Best regards,
Wolfgang Denk
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Monday, May 31, 2010 3:11 PM To: Hiremath, Vaibhav Cc: u-boot@lists.denx.de; tom@bumblecow.com; Paulraj, Sandeep; Premi, Sanjeev Subject: Re: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
Dear hvaibhav@ti.com,
In message 1273166585-26101-1-git-send-email-hvaibhav@ti.com you wrote:
From: Vaibhav Hiremath hvaibhav@ti.com
This patch adds basic support for the AM3517EVM. It includes:
- Board int file (.c and .h)
- Default configuration file
- Updates for Makefile
Changes from V2:
- Removed trailing spaces
- Updated MAINTAINERS & MAKEALL for am3517_evm
Such comments do not belong into the commit message. Please place thes ebelow the "---" line:
[Hiremath, Vaibhav] Ok will incorporate in next post.
Signed-off-by: Vaibhav Hiremath hvaibhav@ti.com Signed-off-by: Sanjeev Premi premi@ti.com
==> Comments should go here.
diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..0bc65e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110
+Vaibhav Hiremath hvaibhav@ti.com
- am3517_evm ARM CORTEX-A8 (AM35x SoC)
Please keep list sorted.
[Hiremath, Vaibhav] How does this sorted, I could not see any relation between the entries there.
...
diff --git a/arch/arm/include/asm/arch-omap3/mux.h
b/arch/arm/include/asm/arch-omap3/mux.h
index 0c01c73..ffeb982 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h
...
+/* AM3517 specific */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
Board specific defoinitions should not be added to global header files. Please use a board specific header instead.
[Hiremath, Vaibhav] I think this has been placed at the right place. This is mux definition and got added to mux.h file. You could see all mux definition are present in this file.
Do you see any issues with this?
--- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.c @@ -0,0 +1,76 @@
...
+int board_init(void) +{
- DECLARE_GLOBAL_DATA_PTR;
This is bound to break. DECLARE_GLOBAL_DATA_PTR must always be used on file scope only; never use this on function scope.
[Hiremath, Vaibhav] Agreed. Actually this code is derived form board/ti/evm/, so followed the same here.
I will change it in next post.
Please check all your code.
[Hiremath, Vaibhav] Do you see any other issues? I don't get this statement.
Thanks, Vaibhav
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Genius doesn't work on an assembly line basis. You can't simply say, "Today I will be brilliant." -- Kirk, "The Ultimate Computer", stardate 4731.3
-----Original Message----- From: Hiremath, Vaibhav Sent: Thursday, June 03, 2010 10:57 PM To: 'Wolfgang Denk' Cc: u-boot@lists.denx.de; tom@bumblecow.com; Paulraj, Sandeep; Premi, Sanjeev Subject: RE: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
[Hiremath, Vaibhav] Denk,
Can you please reply to below queries of mine, so that I can incorporate the changes and submit it again?
Thanks, Vaibhav
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Monday, May 31, 2010 3:11 PM To: Hiremath, Vaibhav Cc: u-boot@lists.denx.de; tom@bumblecow.com; Paulraj, Sandeep; Premi, Sanjeev Subject: Re: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
Dear hvaibhav@ti.com,
In message 1273166585-26101-1-git-send-email-hvaibhav@ti.com you wrote:
From: Vaibhav Hiremath hvaibhav@ti.com
This patch adds basic support for the AM3517EVM. It includes:
- Board int file (.c and .h)
- Default configuration file
- Updates for Makefile
Changes from V2:
- Removed trailing spaces
- Updated MAINTAINERS & MAKEALL for am3517_evm
Such comments do not belong into the commit message. Please place thes ebelow the "---" line:
[Hiremath, Vaibhav] Ok will incorporate in next post.
Signed-off-by: Vaibhav Hiremath hvaibhav@ti.com Signed-off-by: Sanjeev Premi premi@ti.com
==> Comments should go here.
diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..0bc65e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110
+Vaibhav Hiremath hvaibhav@ti.com
- am3517_evm ARM CORTEX-A8 (AM35x SoC)
Please keep list sorted.
[Hiremath, Vaibhav] How does this sorted, I could not see any relation between the entries there.
[Hiremath, Vaibhav] Denk,
...
diff --git a/arch/arm/include/asm/arch-omap3/mux.h
b/arch/arm/include/asm/arch-omap3/mux.h
index 0c01c73..ffeb982 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h
...
+/* AM3517 specific */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
Board specific defoinitions should not be added to global header files. Please use a board specific header instead.
[Hiremath, Vaibhav] I think this has been placed at the right place. This is mux definition and got added to mux.h file. You could see all mux definition are present in this file.
Do you see any issues with this?
--- /dev/null +++ b/board/logicpd/am3517evm/am3517evm.c @@ -0,0 +1,76 @@
...
+int board_init(void) +{
- DECLARE_GLOBAL_DATA_PTR;
This is bound to break. DECLARE_GLOBAL_DATA_PTR must always be used on file scope only; never use this on function scope.
[Hiremath, Vaibhav] Agreed. Actually this code is derived form board/ti/evm/, so followed the same here.
I will change it in next post.
Please check all your code.
[Hiremath, Vaibhav] Do you see any other issues? I don't get this statement.
Thanks, Vaibhav
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Genius doesn't work on an assembly line basis. You can't simply say, "Today I will be brilliant." -- Kirk, "The Ultimate Computer", stardate 4731.3
Dear "Hiremath, Vaibhav",
In message 19F8576C6E063C45BE387C64729E7394044E7A16B5@dbde02.ent.ti.com you wrote: ...
diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..0bc65e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110
+Vaibhav Hiremath hvaibhav@ti.com
- am3517_evm ARM CORTEX-A8 (AM35x SoC)
Please keep list sorted.
[Hiremath, Vaibhav] How does this sorted, I could not see any relation between the entries there.
The list is sorted alphabetically by maintainer' last names, and then by CPU / board names.
diff --git a/arch/arm/include/asm/arch-omap3/mux.h
b/arch/arm/include/asm/arch-omap3/mux.h
index 0c01c73..ffeb982 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h
...
+/* AM3517 specific */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
Board specific defoinitions should not be added to global header files. Please use a board specific header instead.
[Hiremath, Vaibhav] I think this has been placed at the right place. This is mux definition and got added to mux.h file. You could see all mux definition are present in this file.
Do you see any issues with this?
Yes, as I wrote: board specific definitions should not be added to global header files. They should be added to board specific files only, avoiding the need for tons of #ifdef's in global files.
Best regards,
Wolfgang Denk
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Monday, June 07, 2010 5:55 PM To: Hiremath, Vaibhav Cc: u-boot@lists.denx.de; tom@bumblecow.com; Paulraj, Sandeep; Premi, Sanjeev Subject: Re: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
Dear "Hiremath, Vaibhav",
In message 19F8576C6E063C45BE387C64729E7394044E7A16B5@dbde02.ent.ti.com you wrote: ...
diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..0bc65e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110
+Vaibhav Hiremath hvaibhav@ti.com
- am3517_evm ARM CORTEX-A8 (AM35x SoC)
Please keep list sorted.
[Hiremath, Vaibhav] How does this sorted, I could not see any relation between the entries there.
The list is sorted alphabetically by maintainer' last names, and then by CPU / board names.
[Hiremath, Vaibhav] Thanks, I will update the patch and submit is shortly.
diff --git a/arch/arm/include/asm/arch-omap3/mux.h
b/arch/arm/include/asm/arch-omap3/mux.h
index 0c01c73..ffeb982 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h
...
+/* AM3517 specific */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
Board specific defoinitions should not be added to global header files. Please use a board specific header instead.
[Hiremath, Vaibhav] I think this has been placed at the right place.
This is
mux definition and got added to mux.h file. You could see all mux
definition
are present in this file.
Do you see any issues with this?
Yes, as I wrote: board specific definitions should not be added to global header files. They should be added to board specific files only, avoiding the need for tons of #ifdef's in global files.
[Hiremath, Vaibhav] Yes I agree this has to be there in board header file, but I don't think we are using #ifdefs anywhere for this, since the usage of this is happening through board header file.
I am moving these definitions to board/logicpd/am3517evm/am3517evm.h file.
Thanks, Vaibhav
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de When you die, the first thing you lose is your life. The next thing is the illusions. - Terry Pratchett, _Pyramids_
participants (3)
-
Hiremath, Vaibhav -
hvaibhav＠ti.com
-
Wolfgang Denk