From: Tien Fong Chee tien.fong.chee@intel.com

Switching to watchdog 1, because there is a hardware bug found in watchdog 0, it cannot reliable trigger a reset to the CPU.

More details can be referred in : Linux commit "59d94d2ed45d598211feb52566e6a806d17f8a3f"

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Teik Heng Chong teik.heng.chong@intel.com --- arch/arm/mach-socfpga/spl_a10.c | 4 ++-- include/configs/socfpga_arria10_socdk.h | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 5d661fb995..f743c0624f 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -263,8 +263,8 @@ void board_init_f(ulong dummy) cm_basic_init(gd->fdt_blob);

#ifdef CONFIG_HW_WATCHDOG - /* release watchdog 0 from reset */ - socfpga_reset_deassert_wd0(); + /* release watchdog 1 from reset */ + socfpga_reset_deassert_wd1();

/* reconfigure and enable the watchdog */ hw_watchdog_init(); diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index f712928d3c..cc2aeebe5b 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -36,4 +36,12 @@ /* The rest of the configuration is shared */ #include <configs/socfpga_common.h>

+/* + * L4 Watchdog + */ +#ifdef CONFIG_HW_WATCHDOG +#undef CONFIG_DW_WDT_BASE +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD1_ADDRESS +#endif + #endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */