In the DH electronics iMX6 board file fix the outdated eeprom path by using a DT label instead.

The label has been newly created for all iMX6QDL DHCOM boards.

Reviewed-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de

---

Changes in v2: - Reviewed-by Marek

arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi | 11 +++++++++++ board/dhelectronics/dh_imx6/dh_imx6.c | 4 ++-- 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi index 4c3b5e82d6..91545ab6e9 100644 --- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi @@ -3,6 +3,17 @@ * Copyright (C) 2020 Harald Seiler hws@denx.de */

+/ { + aliases { + eeprom0 = &eeprom0; + }; +}; + +&i2c3 { + eeprom0: eeprom@50 { + }; +}; + &reg_usb_otg_vbus { gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; enable-active-high; diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 2969e90a70..6059f96e80 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -100,9 +100,9 @@ static int setup_dhcom_mac_from_fuse(void) return 0; }

- eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50"); + eeprom = ofnode_get_aliases_node("eeprom0"); if (!ofnode_valid(eeprom)) { - printf("Invalid hardware path to EEPROM!\n"); + printf("Can't find eeprom0 alias!\n"); return -ENODEV; }

Migrate DH DRC02 device trees from Linux commit 42226c989789 (tag v5.18-rc7). No changes have been made, the DTs are exact copies. Furthermore add the DTB to dh_imx6_defconfig.

Reviewed-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de ---

(no changes since v1)

arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6qdl-dhcom-drc02.dtsi | 143 ++++++++++++++++++++++++++ arch/arm/dts/imx6s-dhcom-drc02.dts | 30 ++++++ configs/dh_imx6_defconfig | 2 +- 4 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6qdl-dhcom-drc02.dtsi create mode 100644 arch/arm/dts/imx6s-dhcom-drc02.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f6..7bfdfb5313 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -771,6 +771,7 @@ dtb-y += \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ imx6dl-wandboard-revd1.dtb \ + imx6s-dhcom-drc02.dtb

endif

diff --git a/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi new file mode 100644 index 0000000000..702cd4a1b2 --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* + * Special SoM hardware required which uses the pins from micro SD card. The + * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 + * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD + * card must be disabled and the uart1 rts/cts must be output on other DHCOM + * pins, see uart1 and usdhc3 node below. + */ +&can2 { + status = "okay"; +}; + +&gpio1 { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX6 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <18 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "DRC02-In1", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H", + "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "", + "", "", "", "", "DRC02-Out1", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&uart1 { + /* + * Due to the use of can2 the signals for can2 Tx and Rx are routed to + * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs + * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts. + */ + /delete-property/ uart-has-rtscts; + cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */ + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; + pinctrl-names = "default"; + rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&uart5 { + /* + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is + * controlled by DHCOM GPIO P. So remove rts/cts pins and the property + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 + * node above. + */ + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>; + pinctrl-names = "default"; + rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; + +&usbh1 { + disable-over-current; +}; + +&usdhc2 { /* SD card */ + status = "okay"; +}; + +&usdhc3 { + /* + * Due to the use of can2 the micro SD card on module have to be + * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as + * can2 Tx and Rx. + */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: uart1 rts + * M: uart1 cts + * P: uart5 rs485-tx-en + * Q: uart5 rs485-rx-en + */ + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; + + pinctrl_uart5_core: uart5-core-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6s-dhcom-drc02.dts b/arch/arm/dts/imx6s-dhcom-drc02.dts new file mode 100644 index 0000000000..4077b607c2 --- /dev/null +++ b/arch/arm/dts/imx6s-dhcom-drc02.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + * + * DHCOM iMX6 variant: + * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2 + * DHCOM PCB number: 493-400 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +/* + * The kernel only distinguishes between i.MX6 Quad and DualLite, + * but the Solo is actually a DualLite with only one CPU. So use + * DualLite for the Solo and disable one CPU node. + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-drc02.dtsi" + +/ { + model = "DH electronics i.MX6S DHCOM on DRC02"; + compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som", + "fsl,imx6dl"; + + cpus { + /delete-node/ cpu@1; + }; +}; diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index c45561aa0e..9c78987473 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2" +CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y

Migrate DH picoITX device trees from Linux commit 42226c989789 (tag v5.18-rc7). No changes have been made, the DTs are exact copies. Furthermore add the DTB to dh_imx6_defconfig.

Reviewed-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de ---

(no changes since v1)

arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6dl-dhcom-picoitx.dts | 20 +++++++ arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi | 69 +++++++++++++++++++++++++ configs/dh_imx6_defconfig | 2 +- 4 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6dl-dhcom-picoitx.dts create mode 100644 arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7bfdfb5313..f7601afd9c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -738,6 +738,7 @@ dtb-y += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dhcom-pdk2.dtb \ + imx6dl-dhcom-picoitx.dts \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ diff --git a/arch/arm/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/dts/imx6dl-dhcom-picoitx.dts new file mode 100644 index 0000000000..038bb00255 --- /dev/null +++ b/arch/arm/dts/imx6dl-dhcom-picoitx.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + * + * DHCOM iMX6 variant: + * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 + * DHCOM PCB number: 493-300 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-picoitx.dtsi" + +/ { + model = "DH electronics i.MX6DL DHCOM on PicoITX"; + compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som", + "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi new file mode 100644 index 0000000000..4cd4cb9543 --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + */ + +#include <dt-bindings/leds/common.h> + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_YELLOW>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "", + "", "", "", "", "", "", "", "", + "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H", + "DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "", + "", "", "", "", "PicoITX-Out1", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: yellow led + */ + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; +}; diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 9c78987473..558619fc31 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02" +CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2 imx6s-dhcom-drc02 imx6dl-dhcom-picoitx" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y

Use phy address from device tree instead of CONFIG_FEC_MXC_PHYADDR from board header. This is required, because the DH picoITX and DRC02 boards require different settings than PDK2. The corresponding 'phy-handle' device tree properties are already there.

I tested this change on picoITX and DRC02, but on PDK2 it is untested.

Reviewed-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de ---

(no changes since v1)

include/configs/dh_imx6.h | 3 --- 1 file changed, 3 deletions(-)

diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 2b14464dff..178f5a6e7d 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -30,9 +30,6 @@ /* Bootcounter */ #define CONFIG_SYS_BOOTCOUNT_BE

-/* FEC ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 7 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3

Firstly the FEC can now use the regulator reg_eth_vio from imx6qdl-dhcom-som.dtsi instead of defining its own.

Secondly the &fec node is moved to the more generic SoM device tree file, because it can be used by multiple boards.

Reviewed-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de

---

Changes in v2: - Reviewed-by Marek

arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi | 13 ------------- arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi | 7 +++++++ 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi index a1ffb1d6fc..0673c21e3c 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi @@ -5,19 +5,6 @@

#include "imx6qdl-dhcom-u-boot.dtsi"

-/ { - fec_vio: regulator-fec { - compatible = "regulator-fixed"; - - regulator-name = "fec-vio"; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; -}; - &fec { phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-reset-post-delay = <10>; - - phy-supply = <&fec_vio>; }; diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi index 91545ab6e9..190567ab7b 100644 --- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+) /* * Copyright (C) 2020 Harald Seiler hws@denx.de + * Copyright (C) 2022 Philip Oberfichtner pro@denx.de */

/ { @@ -9,6 +10,12 @@ }; };

+&fec { + phy-reset-duration = <1>; + phy-reset-post-delay = <10>; + phy-supply = <&reg_eth_vio>; +}; + &i2c3 { eeprom0: eeprom@50 { };

Add a u-boot dtsi for configuring the FEC node of the DH picoITX.

Reviewed-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de

---

Changes in v2: - Reviewed-by Marek

arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi

diff --git a/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi new file mode 100644 index 0000000000..16669b2533 --- /dev/null +++ b/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2022 Philip Oberfichtner pro@denx.de + */ + +#include "imx6qdl-dhcom-u-boot.dtsi" + +&fec { + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +};

Add a u-boot dtsi for configuring the FEC node of the DH DRC02.

Reviewed-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de

---

Changes in v2: - Reviewed-by Marek

arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi

diff --git a/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi new file mode 100644 index 0000000000..16669b2533 --- /dev/null +++ b/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2022 Philip Oberfichtner pro@denx.de + */ + +#include "imx6qdl-dhcom-u-boot.dtsi" + +&fec { + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +};

Before this commit device tree selection could rely solely on differentiating the iMX6 processor variant Q and DL. After adding two new carrier boards, the DRC02 and the picoITX, the interchangeability of SoMs makes this approach infeasible.

It is now required to specify the carrier board (dhcom-drc02, dhcom-picoitx or dhcom-pdk2) at compile time using CONFIG_DEFAULT_DEVICETREE. The SoM is determined at runtime as before.

Signed-off-by: Philip Oberfichtner pro@denx.de

---

Changes in v2: - Rewrite board_fit_config_name_match - Return -EINVAL instead of -1

board/dhelectronics/dh_imx6/dh_imx6.c | 31 +++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 6059f96e80..e8aba83e1a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -225,16 +225,35 @@ int checkboard(void) }

#ifdef CONFIG_MULTI_DTB_FIT +static int strcmp_prefix(const char *s1, const char *s2) +{ + size_t n; + + n = min(strlen(s1), strlen(s2)); + return strncmp(s1, s2, n); +} + int board_fit_config_name_match(const char *name) { - if (is_mx6dq()) { - if (!strcmp(name, "imx6q-dhcom-pdk2")) - return 0; - } else if (is_mx6sdl()) { - if (!strcmp(name, "imx6dl-dhcom-pdk2")) + char *want; + char *have; + + /* Test Board suffix, e.g. -dhcom-drc02 */ + want = strchr(CONFIG_DEFAULT_DEVICE_TREE, '-'); + have = strchr(name, '-'); + + if (!want || !have || strcmp(want, have)) + return -EINVAL; + + /* Test SoC prefix */ + if (is_mx6dq() && !strcmp_prefix(name, "imx6q-")) + return 0; + + if (is_mx6sdl()) { + if (!strcmp_prefix(name, "imx6s-") || !strcmp_prefix(name, "imx6dl-")) return 0; }

- return -1; + return -EINVAL; } #endif