Hi Marek,

Thanks for the reply.

Subject: Re: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

On 11/27/20 3:52 PM, Biju Das wrote:

Sorry for the late reply.

[...]

...

diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index 5bde24ae0e..08345503a2 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -6,6 +6,7 @@ */ #include <common.h> #include <asm/io.h> +#include <soc.h>

#define PRR_MASK 0x7fff #define R8A7796_REV_1_0 0x5200 @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void) #endif }

+static bool is_rzg_family(void) +{

• bool rzg_family_type = false;
• struct udevice *soc;
• char name[16];
• if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {

This depends on some other patchset, right ? I will wait for that to land and then apply this one.

Yes, Simon have reviewed this patches and not sure who needs to pick this up. So I have sent a gentle remainder for picking this patches [1] [1] http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC-identificatio...

Did you check that this is still OK on RCar Gen2 with its size-limited SPL?

Unfortunately I do not have access currently to RCar Gen2 boards.

Shall we enable "is_rzg_family" as a weekfunction and override it for RCar Gen3? or it will be grateful, please could you test this on RCar Gen2 boards, if you have any?

Please let us know.

Also, do you have a git tree with all the remaining patches applied on top? It would be useful to get an overview what's still pending for mainline.

We have an internal private u-boot repository, where we run mainline u-boot CI job as part of patch submission.

Regarding status wise, all the patches required for boot RZ/G2[HMN] boards are submitted to mainline and is in review state.

For RZ/G2E, some patches are pending because of the dependency with RZ/G2[HMN]. We created a public repo[1] to get an overview what is still pending for mainline.

[1] https://github.com/prabhakarlad/u-boot-rzg2

Regards, Biju

Thanks

...

• if (!strcmp(name, "RZ/G2"))
  

• 	rzg_family_type = true;
  

• }

[...]

Hi Marek,

-----Original Message----- From: Biju Das Sent: 15 January 2021 10:02 To: Marek Vasut marek.vasut@gmail.com; Nobuhiro Iwamatsu iwamatsu@nigauri.org Cc: Prabhakar Mahadev Lad prabhakar.mahadev-lad.rj@bp.renesas.com; u- boot@lists.denx.de; Chris Paterson Chris.Paterson2@renesas.com; Simon Glass sjg@chromium.org; Tom Rini trini@konsulko.com Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

Hi,

...

Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

...

...

diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index 5bde24ae0e..08345503a2 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -6,6 +6,7 @@ */ #include <common.h> #include <asm/io.h> +#include <soc.h>

#define PRR_MASK 0x7fff #define R8A7796_REV_1_0 0x5200 @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void) #endif }

+static bool is_rzg_family(void) +{

• bool rzg_family_type = false;
• struct udevice *soc;
• char name[16];
• if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {

This depends on some other patchset, right ? I will wait for that to land and then apply this one.

Yes, Simon have reviewed this patches and not sure who needs to pick this up. So I have sent a gentle remainder for picking this patches [1] [1] http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC- identification-driver-support-tt432936.html

...

Did you check that this is still OK on RCar Gen2 with its size-limited SPL?

Good catch. I have built spl image for koelsch and I see there is a change in Size of SPL with and without soc identification driver + SoC uclass driver included

With SoC identification driver + SoC uclass driver included -----------------------------------------------------------

$ ls -al spl/u-boot-spl.bin -rwxr-xr-x 1 biju biju 13996 Jan 16 14:16 spl/u-boot-spl.bin $ size spl/u-boot-spl text data bss dec hex filename 13789 204 1100 15093 3af5 spl/u-boot-spl

Without SoC identification driver + SoC uclass driver ----------------------------------------------------- $ ls -al spl/u-boot-spl.bin -rwxr-xr-x 1 biju biju 13916 Jan 16 14:19 spl/u-boot-spl.bin size spl/u-boot-spl text data bss dec hex filename 13785 128 1100 15013 3aa5 spl/u-boot-spl

I will post V5 with Renesas soc identification driver disabled for SPL builds along with SoC uclass driver.

Regards, Biju

On 11/27/20 11:52 PM, Biju Das wrote:

Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com

Reviewed-by: Jaehoon chung jh80.chung@samsung.com

Best Regards, Jaehoon Chung

---

v7:

• Incorporated Jaehoon Chung's review comments.
• Fixed the build error on Renesas ARM32 platforms.

v6:

• New patch. quirks using soc_device_match.

---

drivers/mmc/renesas-sdhi.c | 117 +++++++++++++++++++++++++++++++++++++ 1 file changed, 117 insertions(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index d80b3fc28f..7e3ea92cbf 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -19,6 +19,7 @@ #include <linux/io.h> #include <linux/sizes.h> #include <power/regulator.h> +#include <soc.h> #include <asm/unaligned.h> #include "tmio-common.h"

@@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv) return clk_get_rate(&priv->clk); }

+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \

• CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
• CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)

+#define SDHI_CALIB_TABLE_MAX 32

+struct renesas_sdhi_quirks {

• bool hs400_disabled;
• bool hs400_4taps;
• u32 hs400_bad_taps;
• const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];

+};

+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {

• .hs400_disabled = true,
• .hs400_4taps = true,

+};

+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {

• .hs400_disabled = true,
• .hs400_4taps = true,

+};

+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {

• .hs400_4taps = true,
• .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
• .hs400_calib_table = r8a7796_rev1_calib_table,

+};

+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {

• .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
• .hs400_calib_table = r8a7796_rev3_calib_table,

+};

+/*

• • Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
• • So, we want to treat them equally and only have a match for ES1.2 to enforce
• • this if there ever will be a way to distinguish ES1.2.
• */

+static const struct soc_attr sdhi_quirks_match[] = {

• { .soc_id = "r8a774a1",

•  .revision = "ES1.0",
  

•  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
  

• },
• { .soc_id = "r8a774a1",

•  .revision = "ES1.1",
  

•  .data = &sdhi_quirks_4tap_nohs400
  

• },
• { .soc_id = "r8a774a1",

•  .revision = "ES1.2",
  

•  .data = &sdhi_quirks_r8a7796_es12
  

• },
• { .soc_id = "r8a774a1",

•  .revision = "ES1.3",
  

•  .data = &sdhi_quirks_r8a7796_es13
  

• },
• { .soc_id = "r8a7796",

•  .revision = "ES1.0",
  

•  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
  

• },
• { .soc_id = "r8a7796",

•  .revision = "ES1.1",
  

•  .data = &sdhi_quirks_4tap_nohs400
  

• },
• { .soc_id = "r8a7796",

•  .revision = "ES1.2",
  

•  .data = &sdhi_quirks_r8a7796_es12
  

• },
• { .soc_id = "r8a7796",

•  .revision = "ES1.3",
  

•  .data = &sdhi_quirks_r8a7796_es13
  

• },
• { /* Sentinel. */ },

+};

+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,

• 		    struct tmio_sd_priv *priv,
  

• 		    const struct renesas_sdhi_quirks *quirks)
  

+{

• priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
• priv->nrtaps = 8;
• if (!quirks)

• return;
  

• if (quirks->hs400_disabled) {

• plat->cfg.host_caps &= ~MMC_MODE_HS400;
  

• if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
  

• 	priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
  

• }
• if (quirks->hs400_4taps)

• priv->nrtaps = 4;
  

• if (quirks->hs400_bad_taps)

• priv->hs400_bad_tap = quirks->hs400_bad_taps;
  

• if (quirks->hs400_calib_table) {

• priv->adjust_hs400_enable = true;
  

• priv->adjust_hs400_calib_table =
  

• 	quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
  

• if (quirks == &sdhi_quirks_r8a7796_es12)
  

• 	priv->adjust_hs400_offset = 3;
  

• else if (quirks == &sdhi_quirks_r8a7796_es13)
  

• 	priv->adjust_hs400_offset = 0;
  

• }

+} +#endif

static void renesas_sdhi_filter_caps(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); @@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) struct tmio_sd_plat *plat = dev_get_platdata(dev);

• const struct soc_attr *attr;

• attr = soc_device_match(sdhi_quirks_match);

• if (attr) {

• renesas_sdhi_add_quirks(plat, priv, attr->data);
  

• return;
  

• }

  /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&

On 11/27/20 11:52 PM, Biju Das wrote:

Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com

Reviewed-by: Jaehoon chung jh80.chung@samsung.com

Best Regards, Jaehoon Chung

---

v7:

• No Change.

v6:

• New patch. quirks using soc_device_match.

---

drivers/mmc/renesas-sdhi.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 7e3ea92cbf..b84cfaa9a3 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { .hs400_calib_table = r8a7796_rev3_calib_table, };

+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {

• .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
• .hs400_calib_table = r8a77965_calib_table,

+};

/*

• Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
• So, we want to treat them equally and only have a match for ES1.2 to enforce

@@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[] = { .revision = "ES1.3", .data = &sdhi_quirks_r8a7796_es13 },

• { .soc_id = "r8a774b1",

•  .data = &sdhi_quirks_r8a77965
  

• }, { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_b17_dtrend

@@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[] = { .revision = "ES1.3", .data = &sdhi_quirks_r8a7796_es13 },

• { .soc_id = "r8a77965",

•  .data = &sdhi_quirks_r8a77965
  

• }, { /* Sentinel. */ },

};

@@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat, priv->adjust_hs400_enable = true; priv->adjust_hs400_calib_table = quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];

• if (quirks == &sdhi_quirks_r8a7796_es12)
  

• if (quirks == &sdhi_quirks_r8a7796_es12 ||
  

•     quirks == &sdhi_quirks_r8a77965)
  priv->adjust_hs400_offset = 3;
  

  else if (quirks == &sdhi_quirks_r8a7796_es13) priv->adjust_hs400_offset = 0;

On 11/27/20 11:53 PM, Biju Das wrote:

Add SDHI quirks for R-Car H3 and RZ/G2H SoC.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com

Reviewed-by: Jaehoon chung jh80.chung@samsung.com

Best Regards, Jaehoon Chung

---

v7:

• No Change.

v6:

• New patch. quirks using soc_device_match.

---

drivers/mmc/renesas-sdhi.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index b84cfaa9a3..09d8a2aa0a 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { .hs400_4taps = true, };

+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {

• .hs400_4taps = true,
• .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),

+};

+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {

• .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
• .hs400_calib_table = r8a7795_calib_table,

+};

static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = { .hs400_4taps = true, .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), @@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[] = { { .soc_id = "r8a774b1", .data = &sdhi_quirks_r8a77965 },

• { .soc_id = "r8a774e1",

•  .revision = "ES3.0",
  

•  .data = &sdhi_quirks_r8a7795_es30
  

• },
• { .soc_id = "r8a7795",

•  .revision = "ES1.0",
  

•  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
  

• },
• { .soc_id = "r8a7795",

•  .revision = "ES1.1",
  

•  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
  

• },
• { .soc_id = "r8a7795",

•  .revision = "ES2.0",
  

•  .data = &sdhi_quirks_4tap
  

• },
• { .soc_id = "r8a7795",

•  .revision = "ES3.0",
  

•  .data = &sdhi_quirks_r8a7795_es30
  

• }, { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_b17_dtrend

@@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat, if (quirks == &sdhi_quirks_r8a7796_es12 || quirks == &sdhi_quirks_r8a77965) priv->adjust_hs400_offset = 3;

• else if (quirks == &sdhi_quirks_r8a7796_es13)
  

• else if (quirks == &sdhi_quirks_r8a7796_es13 ||
  

• 	 quirks == &sdhi_quirks_r8a7795_es30)
  priv->adjust_hs400_offset = 0;
  

  }

}