[U-Boot] [PATCH 0/3] ARM: at91: sama5d2_xplained: change SDHCI GCK's clock source to UPLL
To align to the Linux driver, change the clock source of the SDHCI's generated clock from PLLA to UPLL clock.
Wenyou Yang (3): ARM: at91: clock: fix the GCK's clock source ARM: at91: clock: complete the GCK's clock sources board: sama5d2_xplained: change SDHCI GCK's clock source to UPLL
arch/arm/mach-at91/armv7/clock.c | 11 +++++++++++ arch/arm/mach-at91/include/mach/clk.h | 2 ++ board/atmel/sama5d2_xplained/sama5d2_xplained.c | 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-)
Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com ---
arch/arm/mach-at91/armv7/clock.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 81e9f69..27372b3 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -162,6 +162,11 @@ int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) if (div > 0xff) return -EINVAL;
+ if (clk_source == GCK_CSS_UPLL_CLK) { + if (at91_upll_clk_enable()) + return -ENODEV; + } + writel(id, &pmc->pcr); regval = readl(&pmc->pcr); regval &= ~AT91_PMC_PCR_GCKCSS;
On Mon, Apr 11, 2016 at 04:41:31PM +0800, Wenyou Yang wrote:
Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com
Reviewed-by: Andreas Bießmann andreas@biessmann.org
arch/arm/mach-at91/armv7/clock.c | 5 +++++ 1 file changed, 5 insertions(+)
Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com ---
arch/arm/mach-at91/armv7/clock.c | 6 ++++++ arch/arm/mach-at91/include/mach/clk.h | 2 ++ 2 files changed, 8 insertions(+)
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 27372b3..76fcada 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -236,6 +236,12 @@ u32 at91_get_periph_generated_clk(u32 id) case AT91_PMC_PCR_GCKCSS_PLLA_CLK: freq = gd->arch.plla_rate_hz; break; + case AT91_PMC_PCR_GCKCSS_UPLL_CLK: + freq = AT91_UTMI_PLL_CLK_FREQ; + break; + case AT91_PMC_PCR_GCKCSS_MCK_CLK: + freq = gd->arch.mck_rate_hz; + break; default: printf("Improper GCK clock source selection!\n"); freq = 0; diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index 8577c74..ca7d7d0 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -20,6 +20,8 @@ #define GCK_CSS_MCK_CLK 4 #define GCK_CSS_AUDIO_CLK 5
+#define AT91_UTMI_PLL_CLK_FREQ 480000000 + static inline unsigned long get_cpu_clk_rate(void) { DECLARE_GLOBAL_DATA_PTR;
On Mon, Apr 11, 2016 at 04:41:32PM +0800, Wenyou Yang wrote:
Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com
Reviewed-by: Andreas Bießmann andreas@biessmann.org
arch/arm/mach-at91/armv7/clock.c | 6 ++++++ arch/arm/mach-at91/include/mach/clk.h | 2 ++ 2 files changed, 8 insertions(+)
Change the clock source of the SDHCI's generated clock from PLLA to UPLL clock to align to Linux driver.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com ---
board/atmel/sama5d2_xplained/sama5d2_xplained.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 10edf28..7324c2c 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -174,7 +174,7 @@ static void board_sdhci0_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_SDMMC0); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); }
static void board_sdhci1_hw_init(void) @@ -190,7 +190,7 @@ static void board_sdhci1_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_SDMMC1); at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, - GCK_CSS_PLLA_CLK, 1); + GCK_CSS_UPLL_CLK, 1); }
int board_mmc_init(bd_t *bis)
On Mon, Apr 11, 2016 at 04:41:33PM +0800, Wenyou Yang wrote:
Change the clock source of the SDHCI's generated clock from PLLA to UPLL clock to align to Linux driver.
Signed-off-by: Wenyou Yang wenyou.yang@atmel.com
Reviewed-by: Andreas Bießmann andreas@biessmann.org
board/atmel/sama5d2_xplained/sama5d2_xplained.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
participants (2)
-
Andreas Bießmann -
Wenyou Yang