Split PHY-related initialization to a common file

The mv881116 PHY initialization is split out to a common file to enable code reuse between different boards.

Signed-off-by: Simon Kagstrom simon.kagstrom@netinsight.net --- board/Marvell/common/mv881116.c | 65 +++++++++++++++++++++++++++++++++ board/Marvell/common/mv881116.h | 29 +++++++++++++++ board/Marvell/sheevaplug/Makefile | 2 +- board/Marvell/sheevaplug/sheevaplug.c | 32 ++--------------- board/Marvell/sheevaplug/sheevaplug.h | 8 ---- 5 files changed, 98 insertions(+), 38 deletions(-) create mode 100644 board/Marvell/common/mv881116.c create mode 100644 board/Marvell/common/mv881116.h

diff --git a/board/Marvell/common/mv881116.c b/board/Marvell/common/mv881116.c new file mode 100644 index 0000000..9f5c7f1 --- /dev/null +++ b/board/Marvell/common/mv881116.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +#include <common.h> +#include <miiphy.h> +#include "mv881116.h" + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +void mv881116_reset_phy(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} diff --git a/board/Marvell/common/mv881116.h b/board/Marvell/common/mv881116.h new file mode 100644 index 0000000..f1fe13f --- /dev/null +++ b/board/Marvell/common/mv881116.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +#ifndef __MV881116_H +#define __MV881116_H + +void mv881116_reset_phy(char *name); + +#endif /* __MV881116_H */ diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile index e378b5b..05c979d 100644 --- a/board/Marvell/sheevaplug/Makefile +++ b/board/Marvell/sheevaplug/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(BOARD).a

-COBJS := sheevaplug.o +COBJS := sheevaplug.o ../common/mv881116.o

SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 547126a..f018a46 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -27,6 +27,7 @@ #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> #include "sheevaplug.h" +#include "../common/mv881116.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -120,36 +121,9 @@ int dram_init(void) }

#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); + /* Configure and enable MV88E1116 PHY */ + mv881116_reset_phy("egiga0"); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h index 3ed5b7f..030d64f 100644 --- a/board/Marvell/sheevaplug/sheevaplug.h +++ b/board/Marvell/sheevaplug/sheevaplug.h @@ -30,12 +30,4 @@ #define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ #define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */

-/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - #endif /* __SHEEVAPLUG_H */

Support for the OpenRD base board

The implementation is borrowed from the sheevaplug board and the Marvell 1.1.4 code and likely to be a bit incomplete. GPIO pins are configured, but not really tested.

Signed-off-by: Simon Kagstrom simon.kagstrom@netinsight.net --- Makefile | 3 + board/Marvell/openrd_base/Makefile | 51 ++++++++ board/Marvell/openrd_base/config.mk | 25 ++++ board/Marvell/openrd_base/openrd_base.c | 129 +++++++++++++++++++ board/Marvell/openrd_base/openrd_base.h | 42 ++++++ include/asm-arm/arch-kirkwood/mpp.h | 2 +- include/asm-arm/mach-types.h | 13 ++ include/configs/openrd_base.h | 210 +++++++++++++++++++++++++++++++ 8 files changed, 474 insertions(+), 1 deletions(-) create mode 100644 board/Marvell/openrd_base/Makefile create mode 100644 board/Marvell/openrd_base/config.mk create mode 100644 board/Marvell/openrd_base/openrd_base.c create mode 100644 board/Marvell/openrd_base/openrd_base.h create mode 100644 include/configs/openrd_base.h

diff --git a/Makefile b/Makefile index 1515de6..d1ecd1e 100644 --- a/Makefile +++ b/Makefile @@ -2897,6 +2897,9 @@ omap1610h2_cs_autoboot_config: unconfig omap5912osk_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap

+openrd_base_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood + xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))

omap730p2_config \ diff --git a/board/Marvell/openrd_base/Makefile b/board/Marvell/openrd_base/Makefile new file mode 100644 index 0000000..42c0842 --- /dev/null +++ b/board/Marvell/openrd_base/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := openrd_base.o ../common/mv881116.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/openrd_base/config.mk b/board/Marvell/openrd_base/config.mk new file mode 100644 index 0000000..a4ea769 --- /dev/null +++ b/board/Marvell/openrd_base/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar prafulla@marvell.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00600000 diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c new file mode 100644 index 0000000..5a15091 --- /dev/null +++ b/board/Marvell/openrd_base/openrd_base.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net + * Based on sheevaplug.c written-by Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "openrd_base.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_TDM_CH0_TX_QL, + MPP36_TDM_SPI_CS1, + MPP37_TDM_CH2_TX_QL, + MPP38_TDM_CH2_RX_QL, + MPP39_AUDIO_I2SBCLK, + MPP40_AUDIO_I2SDO, + MPP41_AUDIO_I2SLRC, + MPP42_AUDIO_I2SMCLK, + MPP43_AUDIO_I2SDI, + MPP44_AUDIO_EXTCLK, + MPP45_TDM_PCLK, + MPP46_TDM_FS, + MPP47_TDM_DRX, + MPP48_TDM_DTX, + MPP49_TDM_CH0_RX_QL, + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + } + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ + /* Configure and enable MV88E1116 PHY */ + mv881116_reset_phy("egiga0"); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h new file mode 100644 index 0000000..8463eae --- /dev/null +++ b/board/Marvell/openrd_base/openrd_base.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net + * Based on sheevaplug.h written-by Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __OPENRD_BASE_H +#define __OPENRD_BASE_H + +#define OPENRD_OE_LOW (~(1<<28)) +#define OPENRD_OE_HIGH (~(1<<2)) +#define OPENRD_OE_VAL_LOW (0) +#define OPENRD_OE_VAL_HIGH (1 << 2) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __OPENRD_BASE_H */ diff --git a/include/asm-arm/arch-kirkwood/mpp.h b/include/asm-arm/arch-kirkwood/mpp.h index e021a80..bc74278 100644 --- a/include/asm-arm/arch-kirkwood/mpp.h +++ b/include/asm-arm/arch-kirkwood/mpp.h @@ -289,7 +289,7 @@

#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TDM_DTX MPP( 48. 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 )

#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 9b8485d..bbea2de 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -2120,6 +2120,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_FMZWEBMODUL 2134 #define MACH_TYPE_RD78X00_MASA 2135 #define MACH_TYPE_SMALLOGGER 2136 +#define MACH_TYPE_OPENRD_BASE 2261

#ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -26949,6 +26950,18 @@ extern unsigned int __machine_arch_type; # define machine_is_sheevaplug() (0) #endif

+#ifdef CONFIG_MACH_OPENRD_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_BASE +# endif +# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) +#else +# define machine_is_openrd_base() (0) +#endif + #ifdef CONFIG_MACH_AT91SAM9G20 # ifdef machine_arch_type # undef machine_arch_type diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h new file mode 100644 index 0000000..5bfd689 --- /dev/null +++ b/include/configs/openrd_base.h @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Simon Kagstrom simon.kagstrom@netinsight.net + * Based on sheevaplug.h written-by Prafulla Wadaskar prafulla@marvell.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_OPENRD_BASE_H +#define _CONFIG_OPENRD_BASE_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nMarvell-OpenRD_base" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration + */ +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FAT +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_USB + +/* + * Flash configuration + */ +#ifndef CONFIG_CMD_FLASH +#define CONFIG_SYS_NO_FLASH 1 /* Declare no flash (NOR/SPI) */ +#endif + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \ + "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable both ports */ +#define CONFIG_PHY_BASE_ADR 0x8 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +#endif /* _CONFIG_OPENRD_BASE_H */