[U-Boot] [PATCH v2 0/4] port for the Aspeed ast2500 FMC/SPI controllers
Hello,
This series adds a driver for the Aspeed ast2500 FMC/SPI controllers as one can find on the POWER9 OpenPOWER platforms.
It was tested on the AST2500 evb using a w25q256 flash device.
Git tree available here:
https://github.com/legoater/u-boot/commits/aspeed
Thanks,
C.
Changes since v1:
- introduced a new large update of the ast2500 DTS file from Linux - renamed variables in the read calibration algorithm - moved the ast2500 defconfig changes in the patch adding the SPI driver
Cédric Le Goater (4): aspeed: ast2500: Add AHB clock spi: Add support for the Aspeed ast2500 SPI controllers aspeed: Update ast2500 Eval Board DTS files to Linux v4.17-rc6 level aspeed: Activate SPI support on the ast2500 Eval Board
.../arm/include/asm/arch-aspeed/scu_ast2500.h | 2 + arch/arm/include/asm/arch-aspeed/spi.h | 114 + include/dt-bindings/clock/ast2500-scu.h | 1 + drivers/clk/aspeed/clk_ast2500.c | 12 + drivers/spi/aspeed_spi.c | 791 +++++++ arch/arm/dts/ast2500-evb.dts | 15 + arch/arm/dts/ast2500-u-boot.dtsi | 12 + arch/arm/dts/ast2500.dtsi | 1995 ++++++++++------- configs/evb-ast2500_defconfig | 10 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + 11 files changed, 2164 insertions(+), 797 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/spi.h create mode 100644 drivers/spi/aspeed_spi.c
The AHB clock is used by the FMC/SPI controllers.
Signed-off-by: Cédric Le Goater clg@kaod.org Reviewed-by: Joel Stanley joel@jms.id.au --- arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 2 ++ include/dt-bindings/clock/ast2500-scu.h | 1 + drivers/clk/aspeed/clk_ast2500.c | 12 ++++++++++++ 3 files changed, 15 insertions(+)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index 4988ced7ddcc..6a90ded752ad 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -11,6 +11,8 @@ #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) #define SCU_HWSTRAP_MAC1_RGMII (1 << 6) #define SCU_HWSTRAP_MAC2_RGMII (1 << 7) +#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT 9 +#define SCU_HWSTRAP_AXIAHB_DIV_MASK (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT) #define SCU_HWSTRAP_DDR4 (1 << 24) #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/ast2500-scu.h index 4803abe9f628..03e6d16d3de0 100644 --- a/include/dt-bindings/clock/ast2500-scu.h +++ b/include/dt-bindings/clock/ast2500-scu.h @@ -17,6 +17,7 @@ #define BCLK_MACCLK 103 #define BCLK_SDCLK 104 #define BCLK_ARMCLK 105 +#define BCLK_HCLK 106
#define MCLK_DDR 201
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 526470051c5d..c55f8d5ae30d 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -143,6 +143,18 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = rate / apb_div; } break; + case BCLK_HCLK: + { + ulong ahb_div = 1 + ((readl(&priv->scu->hwstrap) + & SCU_HWSTRAP_AXIAHB_DIV_MASK) + >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT); + ulong axi_div = 2; + + rate = ast2500_get_hpll_rate( + clkin, readl(&priv->scu->h_pll_param)); + rate = rate / axi_div / ahb_div; + } + break; case PCLK_UART1: rate = ast2500_get_uart_clk_rate(priv->scu, 1); break;
The Aspeed AST2500 SoC comes with three static memory controllers, all with a similar interface :
* Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0 ~ CE1) . CE2 can be of NOR type flash but this is not supported by the driver
* SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1)
Each controller has a defined AHB window for its registers and another AHB window on which all the flash devices are mapped. Each device is assigned a memory range through a set of registers called the Segment Address Registers.
Devices are controlled using two different modes: the USER command mode or the READ/WRITE command mode. When in USER command mode, accesses to the AHB window of the SPI flash device are translated into SPI command transfers. When in READ/WRITE command mode, the HW generates the SPI commands depending on the setting of the CE control register.
The following driver supports the FMC and the SPI controllers with the attached SPI flash devices. When the controller is probed, the driver performs a read timing calibration using specific DMA control registers (FMC only). The driver's primary goal is to support the first device of the FMC controller on which reside U-Boot but it should support the other controllers also.
The Aspeed FMC controller automatically detects at boot time if a flash device is in 4BYTE address mode and self configures to use the appropriate address width. This can be a problem for the U-Boot SPI Flash layer which only supports 3 byte addresses. In such a case, a warning is emitted and the address width is fixed when sent on the bus.
Signed-off-by: Cédric Le Goater clg@kaod.org Reviewed-by: Joel Stanley joel@jms.id.au ---
Changes since v1:
- renamed variables in the read calibration algorithm - moved in the ast2500 defconfig changes
arch/arm/include/asm/arch-aspeed/spi.h | 114 ++++ drivers/spi/aspeed_spi.c | 791 +++++++++++++++++++++++++ configs/evb-ast2500_defconfig | 10 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + 5 files changed, 924 insertions(+) create mode 100644 arch/arm/include/asm/arch-aspeed/spi.h create mode 100644 drivers/spi/aspeed_spi.c
diff --git a/arch/arm/include/asm/arch-aspeed/spi.h b/arch/arm/include/asm/arch-aspeed/spi.h new file mode 100644 index 000000000000..9e952933e1f1 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/spi.h @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018, IBM Corporation. + */ + +#ifndef _ASM_ARCH_ASPEED_SPI_H +#define _ASM_ARCH_ASPEED_SPI_H + +/* CE Type Setting Register */ +#define CONF_ENABLE_W2 BIT(18) +#define CONF_ENABLE_W1 BIT(17) +#define CONF_ENABLE_W0 BIT(16) +#define CONF_FLASH_TYPE2 4 +#define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ +#define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ +#define CONF_FLASH_TYPE_NOR 0x0 +#define CONF_FLASH_TYPE_SPI 0x2 + +/* CE Control Register */ +#define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ +#define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ +#define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ + +/* Interrupt Control and Status Register */ +#define INTR_CTRL_DMA_STATUS BIT(11) +#define INTR_CTRL_CMD_ABORT_STATUS BIT(10) +#define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) +#define INTR_CTRL_DMA_EN BIT(3) +#define INTR_CTRL_CMD_ABORT_EN BIT(2) +#define INTR_CTRL_WRITE_PROTECT_EN BIT(1) + +/* CEx Control Register */ +#define CE_CTRL_IO_MODE_MASK GENMASK(30, 28) +#define CE_CTRL_IO_DUAL_DATA BIT(29) +#define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) +#define CE_CTRL_CMD_SHIFT 16 +#define CE_CTRL_CMD_MASK 0xff +#define CE_CTRL_CMD(cmd) \ + (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) +#define CE_CTRL_DUMMY_HIGH_SHIFT 14 +#define CE_CTRL_CLOCK_FREQ_SHIFT 8 +#define CE_CTRL_CLOCK_FREQ_MASK 0xf +#define CE_CTRL_CLOCK_FREQ(div) \ + (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) +#define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ +#define CE_CTRL_DUMMY(dummy) \ + (((((dummy) >> 2) & 0x1) << CE_CTRL_DUMMY_HIGH_SHIFT) | \ + (((dummy) & 0x3) << CE_CTRL_DUMMY_LOW_SHIFT)) +#define CE_CTRL_STOP_ACTIVE BIT(2) +#define CE_CTRL_MODE_MASK 0x3 +#define CE_CTRL_READMODE 0x0 +#define CE_CTRL_FREADMODE 0x1 +#define CE_CTRL_WRITEMODE 0x2 +#define CE_CTRL_USERMODE 0x3 + +/* + * The Segment Register uses a 8MB unit to encode the start address + * and the end address of the ABH window of a SPI flash device. + * Default segment addresses are : + * + * CE0 0x20000000 - 0x2FFFFFFF 128MB + * CE1 0x28000000 - 0x29FFFFFF 32MB + * CE2 0x2A000000 - 0x2BFFFFFF 32MB + * + * The full address space of the AHB window of the controller is + * covered and CE0 start address and CE2 end addresses are read-only. + */ +#define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) +#define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) +#define SEGMENT_ADDR_VALUE(start, end) \ + (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) + +/* DMA Control/Status Register */ +#define DMA_CTRL_DELAY_SHIFT 8 +#define DMA_CTRL_DELAY_MASK 0xf +#define DMA_CTRL_FREQ_SHIFT 4 +#define DMA_CTRL_FREQ_MASK 0xf +#define TIMING_MASK(div, delay) \ + (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ + ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) +#define DMA_CTRL_CALIB BIT(3) +#define DMA_CTRL_CKSUM BIT(2) +#define DMA_CTRL_WRITE BIT(1) +#define DMA_CTRL_ENABLE BIT(0) + +#define ASPEED_SPI_MAX_CS 3 + +struct aspeed_spi_regs { + u32 conf; /* 0x00 CE Type Setting */ + u32 ctrl; /* 0x04 Control */ + u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ + u32 cmd_ctrl; /* 0x0C Command Control */ + u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ + u32 _reserved0[5]; /* .. */ + u32 segment_addr[ASPEED_SPI_MAX_CS]; + /* 0x30 .. 0x38 Segment Address */ + u32 _reserved1[17]; /* .. */ + u32 dma_ctrl; /* 0x80 DMA Control/Status */ + u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ + u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ + u32 dma_len; /* 0x8C DMA Length Register */ + u32 dma_checksum; /* 0x8C Checksum Calculation Result */ + u32 timings; /* 0x94 Read Timing Compensation */ + + /* not used */ + u32 soft_strap_status; /* 0x9C Software Strap Status */ + u32 write_cmd_filter_ctrl; /* 0xA0 Write Command Filter Control */ + u32 write_addr_filter_ctrl; /* 0xA4 Write Address Filter Control */ + u32 lock_ctrl_reset; /* 0xA8 Lock Control (SRST#) */ + u32 lock_ctrl_wdt; /* 0xAC Lock Control (Watchdog) */ + u32 write_addr_filter[5]; /* 0xB0 Write Address Filter */ +}; + +#endif /* _ASM_ARCH_ASPEED_SPI_H */ diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c new file mode 100644 index 000000000000..f204c6b49c64 --- /dev/null +++ b/drivers/spi/aspeed_spi.c @@ -0,0 +1,791 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ASPEED AST2500 FMC/SPI Controller driver + * + * Copyright (c) 2015-2018, IBM Corporation. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/spi.h> +#include <linux/ioport.h> +#include <spi.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct aspeed_spi_flash { + u8 cs; + bool init; /* Initialized when the SPI bus is + * first claimed + */ + void __iomem *ahb_base; /* AHB Window for this device */ + u32 ahb_size; /* AHB Window segment size */ + u32 ce_ctrl_user; /* CE Control Register for USER mode */ + u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ + u32 iomode; + + struct spi_flash *spi; /* Associated SPI Flash device */ +}; + +struct aspeed_spi_priv { + struct aspeed_spi_regs *regs; + void __iomem *ahb_base; /* AHB Window for all flash devices */ + u32 ahb_size; /* AHB Window segments size */ + + ulong hclk_rate; /* AHB clock rate */ + u32 max_hz; + u8 num_cs; + bool is_fmc; + + struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; + u32 flash_count; + + u8 cmd_buf[16]; /* SPI command in progress */ + size_t cmd_len; +}; + +static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); + u8 cs = slave_plat->cs; + + if (cs >= priv->flash_count) { + pr_err("invalid CS %u\n", cs); + return NULL; + } + + return &priv->flashes[cs]; +} + +static u32 aspeed_spi_hclk_divisor(u32 hclk_rate, u32 max_hz) +{ + /* HCLK/1 .. HCLK/16 */ + const u8 hclk_masks[] = { + 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 + }; + + u32 i; + + for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { + if (max_hz >= (hclk_rate / (i + 1))) + break; + } + + debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", + hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); + + return hclk_masks[i]; +} + +/* + * Use some address/size under the first flash device CE0 + */ +static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, u8 div, + u8 delay) +{ + u32 flash_addr = (u32)priv->ahb_base + 0x10000; + u32 flash_len = 0x200; + u32 dma_ctrl; + u32 checksum; + + writel(flash_addr, &priv->regs->dma_flash_addr); + writel(flash_len, &priv->regs->dma_len); + + /* + * When doing calibration, the SPI clock rate in the CE0 + * Control Register and the data input delay cycles in the + * Read Timing Compensation Register are replaced by bit[11:4]. + */ + dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | + TIMING_MASK(div, delay); + writel(dma_ctrl, &priv->regs->dma_ctrl); + + while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) + ; + + writel(0x0, &priv->regs->intr_ctrl); + + checksum = readl(&priv->regs->dma_checksum); + + writel(0x0, &priv->regs->dma_ctrl); + + return checksum; +} + +static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, u8 div, + u8 delay) +{ + /* TODO: the SPI controllers do not have the DMA registers. + * The algorithm is the same. + */ + if (!priv->is_fmc) { + pr_warn("No timing calibration support for SPI controllers"); + return 0xbadc0de; + } + + return aspeed_spi_fmc_checksum(priv, div, delay); +} + +#define TIMING_DELAY_DI_4NS BIT(3) +#define TIMING_DELAY_HCYCLE_MAX 5 + +static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv) +{ + /* HCLK/5 .. HCLK/1 */ + const u8 hclk_masks[] = { 13, 6, 14, 7, 15 }; + + u32 timing_reg = 0; + u32 checksum, gold_checksum; + int i, hcycle; + + debug("Read timing calibration :\n"); + + /* Compute reference checksum at lowest freq HCLK/16 */ + gold_checksum = aspeed_spi_read_checksum(priv, 0, 0); + + /* + * Set CE0 Control Register to FAST READ command mode. The + * HCLK divisor will be set through the DMA Control Register. + */ + writel(CE_CTRL_CMD(0xB) | CE_CTRL_DUMMY(1) | CE_CTRL_FREADMODE, + &priv->regs->ce_ctrl[0]); + + /* Increase HCLK freq */ + for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { + u32 hdiv = 5 - i; + u32 hshift = (hdiv - 1) << 2; + bool pass = false; + u8 delay; + + if (priv->hclk_rate / hdiv > priv->max_hz) { + debug("skipping freq %ld\n", priv->hclk_rate / hdiv); + continue; + } + + /* Increase HCLK cycles until read succeeds */ + for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { + /* Try first with a 4ns DI delay */ + delay = TIMING_DELAY_DI_4NS | hcycle; + checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], + delay); + pass = (checksum == gold_checksum); + debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", + hdiv, hcycle, pass ? "PASS" : "FAIL"); + + /* Try again with more HCLK cycles */ + if (!pass) + continue; + + /* Try without the 4ns DI delay */ + delay = hcycle; + checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], + delay); + pass = (checksum == gold_checksum); + debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", + hdiv, hcycle, pass ? "PASS" : "FAIL"); + + /* All good for this freq */ + if (pass) + break; + } + + if (pass) { + timing_reg &= ~(0xfu << hshift); + timing_reg |= delay << hshift; + } + } + + debug("Read Timing Compensation set to 0x%08x\n", timing_reg); + writel(timing_reg, &priv->regs->timings); + + /* Reset CE0 Control Register */ + writel(0x0, &priv->regs->ce_ctrl[0]); + return 0; +} + +static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) +{ + int cs, ret; + + /* + * Enable write on all flash devices as USER command mode + * requires it. + */ + setbits_le32(&priv->regs->conf, + CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); + + /* + * Set the Read Timing Compensation Register. This setting + * applies to all devices. + */ + ret = aspeed_spi_timing_calibration(priv); + if (ret) + return ret; + + /* + * Set safe default settings for each device. These will be + * tuned after the SPI flash devices are probed. + */ + for (cs = 0; cs < priv->flash_count; cs++) { + struct aspeed_spi_flash *flash = &priv->flashes[cs]; + u32 seg_addr = readl(&priv->regs->segment_addr[cs]); + + /* + * The start address of the AHB window of CE0 is + * read-only and is the same as the address of the + * overall AHB window of the controller for all flash + * devices. + */ + flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : + priv->ahb_base; + + flash->cs = cs; + flash->ce_ctrl_user = CE_CTRL_USERMODE; + flash->ce_ctrl_fread = CE_CTRL_READMODE; + } + + return 0; +} + +static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, + size_t len) +{ + size_t offset = 0; + + if (!((uintptr_t)buf % 4)) { + readsl(ahb_base, buf, len >> 2); + offset = len & ~0x3; + len -= offset; + } + readsb(ahb_base, (u8 *)buf + offset, len); + + return 0; +} + +static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, + size_t len) +{ + size_t offset = 0; + + if (!((uintptr_t)buf % 4)) { + writesl(ahb_base, buf, len >> 2); + offset = len & ~0x3; + len -= offset; + } + writesb(ahb_base, (u8 *)buf + offset, len); + + return 0; +} + +static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash) +{ + u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; + + /* Unselect CS and set USER command mode */ + writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); + + /* Select CS */ + clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); +} + +static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash) +{ + /* Unselect CS first */ + setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); + + /* Restore default command mode */ + writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); +} + +static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash, + u8 opcode, u8 *read_buf, int len) +{ + aspeed_spi_start_user(priv, flash); + aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); + aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); + aspeed_spi_stop_user(priv, flash); + return 0; +} + +static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash, + u8 opcode, const u8 *write_buf, int len) +{ + aspeed_spi_start_user(priv, flash); + aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); + aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); + aspeed_spi_stop_user(priv, flash); + return 0; +} + +static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash, + const u8 *cmdbuf, unsigned int cmdlen) +{ + int i; + u8 byte0 = 0x0; + u8 addrlen = cmdlen - 1; + + /* First, send the opcode */ + aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); + + /* + * The controller is configured for 4BYTE address mode. Fix + * the address width and send an extra byte if the SPI Flash + * layer uses 3 bytes addresses. + */ + if (addrlen == 3 && readl(&priv->regs->ctrl) & BIT(flash->cs)) + aspeed_spi_write_to_ahb(flash->ahb_base, &byte0, 1); + + /* Then the address */ + for (i = 1 ; i < cmdlen; i++) + aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); +} + +static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash, + unsigned int cmdlen, const u8 *cmdbuf, + unsigned int len, u8 *read_buf) +{ + u8 dummy = 0xFF; + int i; + + aspeed_spi_start_user(priv, flash); + + /* cmd buffer = cmd + addr + dummies */ + aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, + cmdlen - flash->spi->dummy_byte); + + for (i = 0 ; i < flash->spi->dummy_byte; i++) + aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); + + if (flash->iomode) { + clrbits_le32(&priv->regs->ce_ctrl[flash->cs], + CE_CTRL_IO_MODE_MASK); + setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->iomode); + } + + aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); + aspeed_spi_stop_user(priv, flash); + return 0; +} + +static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash, + unsigned int cmdlen, const u8 *cmdbuf, + unsigned int len, const u8 *write_buf) +{ + aspeed_spi_start_user(priv, flash); + + /* cmd buffer = cmd + addr */ + aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); + aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); + + aspeed_spi_stop_user(priv, flash); + return 0; +} + +static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, + const u8 *cmdbuf, unsigned int cmdlen) +{ + u8 addrlen = cmdlen - 1; + u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; + + /* U-Boot SPI Flash layer does not support 4BYTE address mode yet */ + if (addrlen == 4) + addr = (addr << 8) | cmdbuf[4]; + + return addr; +} + +/* TODO: add support for XFER_MMAP instead ? */ +static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash, + unsigned int cmdlen, const u8 *cmdbuf, + unsigned int len, u8 *read_buf) +{ + /* cmd buffer = cmd + addr + dummies */ + u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, + cmdlen - flash->spi->dummy_byte); + + /* + * Switch to USER command mode if the AHB window configured + * for the device is too small for the read operation + */ + if (offset + len >= flash->ahb_size) { + return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, + len, read_buf); + } + + memcpy_fromio(read_buf, flash->ahb_base + offset, len); + return 0; +} + +static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct aspeed_spi_priv *priv = dev_get_priv(bus); + struct aspeed_spi_flash *flash; + u8 *cmd_buf = priv->cmd_buf; + size_t data_bytes; + int err = 0; + + flash = aspeed_spi_get_flash(dev); + if (!flash) + return -ENODEV; + + if (flags & SPI_XFER_BEGIN) { + /* save command in progress */ + priv->cmd_len = bitlen / 8; + memcpy(cmd_buf, dout, priv->cmd_len); + } + + if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { + /* if start and end bit are set, the data bytes is 0. */ + data_bytes = 0; + } else { + data_bytes = bitlen / 8; + } + + debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, + din ? "read" : "write", priv->cmd_len, data_bytes); + + if ((flags & SPI_XFER_END) || flags == 0) { + if (priv->cmd_len == 0) { + pr_err("No command is progress !\n"); + return -1; + } + + if (din && data_bytes) { + if (priv->cmd_len == 1) + err = aspeed_spi_read_reg(priv, flash, + cmd_buf[0], + din, data_bytes); + else + err = aspeed_spi_read(priv, flash, + priv->cmd_len, + cmd_buf, data_bytes, + din); + } else if (dout) { + if (priv->cmd_len == 1) + err = aspeed_spi_write_reg(priv, flash, + cmd_buf[0], + dout, data_bytes); + else + err = aspeed_spi_write_user(priv, flash, + priv->cmd_len, + cmd_buf, data_bytes, + dout); + } + + if (flags & SPI_XFER_END) { + /* clear command */ + memset(cmd_buf, 0, sizeof(priv->cmd_buf)); + priv->cmd_len = 0; + } + } + + return err; +} + +static int aspeed_spi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", + slave_plat->cs, slave_plat->max_hz, slave_plat->mode); + + if (!aspeed_spi_get_flash(dev)) + return -ENODEV; + + return 0; +} + +/* + * It is possible to automatically define a contiguous address space + * on top of all CEs in the AHB window of the controller but it would + * require much more work. Let's start with a simple mapping scheme + * which should work fine for a single flash device. + * + * More complex schemes should probably be defined with the device + * tree. + */ +static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash) +{ + u32 seg_addr; + + /* could be configured through the device tree */ + flash->ahb_size = flash->spi->size; + + seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, + (u32)flash->ahb_base + flash->ahb_size); + + writel(seg_addr, &priv->regs->segment_addr[flash->cs]); + return 0; +} + +/* + * The Aspeed FMC controller automatically detects at boot time if a + * flash device is in 4BYTE address mode and self configures to use + * the appropriate address width. This can be a problem for the U-Boot + * SPI Flash layer which only supports 3 byte addresses. In such a + * case, a warning is emitted and the address width is fixed when sent + * on the bus. + */ +static void aspeed_spi_flash_check_4b(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash) +{ + if (readl(&priv->regs->ctrl) & BIT(flash->cs)) + pr_err("CS%u: 4BYTE address mode is active\n", flash->cs); +} + +static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, + struct aspeed_spi_flash *flash, + struct udevice *dev) +{ + struct spi_flash *spi_flash = dev_get_uclass_priv(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + u32 user_hclk; + u32 read_hclk; + + /* + * The SPI flash device slave should not change, so initialize + * it only once. + */ + if (flash->init) + return 0; + + /* + * The flash device has not been probed yet. Initial transfers + * to read the JEDEC of the device will use the initial + * default settings of the registers. + */ + if (!spi_flash->name) + return 0; + + debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d " + "cmds [ erase:%x read=%x write:%x ] dummy:%d mmap:%p\n", + flash->cs, + spi_flash->name, spi_flash->flags, spi_flash->size, + spi_flash->page_size, spi_flash->sector_size, + spi_flash->erase_size, spi_flash->erase_cmd, + spi_flash->read_cmd, spi_flash->write_cmd, + spi_flash->dummy_byte, spi_flash->memory_map); + + flash->spi = spi_flash; + + /* + * Tune the CE Control Register values for the modes the + * driver will use: + * - USER command for specific SPI commands, write and + * erase. + * - FAST READ command mode for reads. The flash device is + * directly accessed through its AHB window. + * + * TODO: introduce a DT property for writes ? + */ + user_hclk = 0; + + flash->ce_ctrl_user = CE_CTRL_CLOCK_FREQ(user_hclk) | + CE_CTRL_USERMODE; + + read_hclk = aspeed_spi_hclk_divisor(priv->hclk_rate, slave->speed); + + if (slave->mode & (SPI_RX_DUAL | SPI_TX_DUAL)) { + debug("CS%u: setting dual data mode\n", flash->cs); + flash->iomode = CE_CTRL_IO_DUAL_DATA; + } + + flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | + flash->iomode | + CE_CTRL_CMD(flash->spi->read_cmd) | + CE_CTRL_DUMMY(flash->spi->dummy_byte) | + CE_CTRL_FREADMODE; + + debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, + flash->ce_ctrl_user, flash->ce_ctrl_fread); + + /* Set the CE Control Register default (FAST READ) */ + writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); + + /* Enable 4BYTE addresses (No support in U-Boot yet) */ + if (flash->spi->size >= 16 << 20) + aspeed_spi_flash_check_4b(priv, flash); + + /* Set Address Segment Register for direct AHB accesses */ + aspeed_spi_flash_set_segment(priv, flash); + + /* All done */ + flash->init = true; + return 0; +} + +static int aspeed_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct aspeed_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct aspeed_spi_flash *flash; + + debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); + + flash = aspeed_spi_get_flash(dev); + if (!flash) + return -ENODEV; + + return aspeed_spi_flash_init(priv, flash, dev); +} + +static int aspeed_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); + + if (!aspeed_spi_get_flash(dev)) + return -ENODEV; + + return 0; +} + +static int aspeed_spi_set_mode(struct udevice *bus, uint mode) +{ + debug("%s: setting mode to %x\n", bus->name, mode); + + if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { + pr_err("%s invalid QUAD IO mode\n", bus->name); + return -EINVAL; + } + + /* The CE Control Register is set in claim_bus() */ + return 0; +} + +static int aspeed_spi_set_speed(struct udevice *bus, uint hz) +{ + debug("%s: setting speed to %u\n", bus->name, hz); + + /* The CE Control Register is set in claim_bus() */ + return 0; +} + +static int aspeed_spi_count_flash_devices(struct udevice *bus) +{ + ofnode node; + int count = 0; + + dev_for_each_subnode(node, bus) { + if (ofnode_is_available(node) && + ofnode_device_is_compatible(node, "spi-flash")) + count++; + } + + return count; +} + +static int aspeed_spi_bind(struct udevice *bus) +{ + debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, + bus->seq); + return 0; +} + +static int aspeed_spi_probe(struct udevice *bus) +{ + struct resource res_regs, res_ahb; + struct aspeed_spi_priv *priv = dev_get_priv(bus); + struct clk hclk; + int ret; + + ret = dev_read_resource(bus, 0, &res_regs); + if (ret < 0) + return ret; + + priv->regs = (void __iomem *)res_regs.start; + + ret = dev_read_resource(bus, 1, &res_ahb); + if (ret < 0) + return ret; + + priv->ahb_base = (void __iomem *)res_ahb.start; + priv->ahb_size = res_ahb.end - res_ahb.start; + + ret = clk_get_by_index(bus, 0, &hclk); + if (ret < 0) { + pr_err("%s could not get clock: %d\n", bus->name, ret); + return ret; + } + + priv->hclk_rate = clk_get_rate(&hclk); + clk_free(&hclk); + + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", + 100000000); + + priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); + + priv->flash_count = aspeed_spi_count_flash_devices(bus); + if (priv->flash_count > priv->num_cs) { + pr_err("%s has too many flash devices: %d\n", bus->name, + priv->flash_count); + return -EINVAL; + } + + if (!priv->flash_count) { + pr_err("%s has no flash devices ?!\n", bus->name); + return -ENODEV; + } + + /* + * There are some slight differences between the FMC and the + * SPI controllers + */ + priv->is_fmc = device_is_compatible(bus, "aspeed,ast2500-fmc"); + + ret = aspeed_spi_controller_init(priv); + if (ret) + return ret; + + debug("%s probed regs=%p ahb_base=%p max-hz=%d cs=%d seq=%d\n", + bus->name, priv->regs, priv->ahb_base, priv->max_hz, + priv->flash_count, bus->seq); + + return 0; +} + +static const struct dm_spi_ops aspeed_spi_ops = { + .claim_bus = aspeed_spi_claim_bus, + .release_bus = aspeed_spi_release_bus, + .set_mode = aspeed_spi_set_mode, + .set_speed = aspeed_spi_set_speed, + .xfer = aspeed_spi_xfer, +}; + +static const struct udevice_id aspeed_spi_ids[] = { + { .compatible = "aspeed,ast2500-fmc" }, + { .compatible = "aspeed,ast2500-spi" }, + { } +}; + +U_BOOT_DRIVER(aspeed_spi) = { + .name = "aspeed_spi", + .id = UCLASS_SPI, + .of_match = aspeed_spi_ids, + .ops = &aspeed_spi_ops, + .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), + .child_pre_probe = aspeed_spi_child_pre_probe, + .bind = aspeed_spi_bind, + .probe = aspeed_spi_probe, +}; diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 88230f4a12db..a418ff0e9e01 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -25,3 +25,13 @@ CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y +CONFIG_SPI=y +CONFIG_ASPEED_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dcd719ff0ac6..fd5e930ec318 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -26,6 +26,14 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera.
+config ASPEED_SPI + bool "Aspeed SPI driver" + default y if ARCH_ASPEED + help + Enable the Aspeed AST2500 FMC/SPI driver. This driver can be + used to access the SPI NOR flash on boards using the Aspeed + AST2500 SoC, such as the POWER9 OpenPOWER platforms + config ATCSPI200_SPI bool "Andestech ATCSPI200 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 728e30c5383c..40d224130ea5 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o endif
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o +obj-$(CONFIG_ASPEED_SPI) += aspeed_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
This is a large update of the AST2500 Soc DTS file bringing it to the level of commit 927c2fc2db19 :
Author: Joel Stanley joel@jms.id.au Date: Sat Jun 2 01:18:53 2018 -0700
ARM: dts: aspeed: Fix hwrng register address
There are some differences on the compatibility property names. scu, reset and clock drivers are also different.
Signed-off-by: Cédric Le Goater clg@kaod.org --- arch/arm/dts/ast2500.dtsi | 1995 ++++++++++++++++++++++--------------- 1 file changed, 1198 insertions(+), 797 deletions(-)
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index 7e0ad3a41ac5..283b695d1b0e 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -11,6 +11,29 @@ #size-cells = <1>; interrupt-parent = <&vic>;
+ aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -22,12 +45,80 @@ }; };
+ memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges;
+ fmc: flash-controller@1e620000 { + reg = < 0x1e620000 0xc4 + 0x20000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-fmc"; + status = "disabled"; + interrupts = <19>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi1: flash-controller@1e630000 { + reg = < 0x1e630000 0xc4 + 0x30000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi2: flash-controller@1e631000 { + reg = < 0x1e631000 0xc4 + 0x38000000 0x08000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2500-spi"; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + vic: interrupt-controller@1e6c0080 { compatible = "aspeed,ast2400-vic"; interrupt-controller; @@ -37,18 +128,38 @@ };
mac0: ethernet@1e660000 { - compatible = "faraday,ftgmac100"; + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; interrupts = <2>; - no-hw-checksum; status = "disabled"; };
mac1: ethernet@1e680000 { - compatible = "faraday,ftgmac100"; + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e680000 0x180>; interrupts = <3>; - no-hw-checksum; + status = "disabled"; + }; + + ehci0: usb@1e6a1000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a1000 0x100>; + interrupts = <5>; + status = "disabled"; + }; + + ehci1: usb@1e6a3000 { + compatible = "aspeed,ast2500-ehci", "generic-ehci"; + reg = <0x1e6a3000 0x100>; + interrupts = <13>; + status = "disabled"; + }; + + uhci: usb@1e6b0000 { + compatible = "aspeed,ast2500-uhci", "generic-uhci"; + reg = <0x1e6b0000 0x100>; + interrupts = <14>; + #ports = <2>; status = "disabled"; };
@@ -58,996 +169,1286 @@ #size-cells = <1>; ranges;
- clk_clkin: clk_clkin@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-clkin-clock"; - reg = <0x1e6e2070 0x04>; - }; - syscon: syscon@1e6e2000 { compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>;
pinctrl: pinctrl { compatible = "aspeed,g5-pinctrl"; aspeed,external-nodes = <&gfx &lhc>;
- pinctrl_acpi_default: acpi_default { - function = "ACPI"; - groups = "ACPI"; - }; - - pinctrl_adc0_default: adc0_default { - function = "ADC0"; - groups = "ADC0"; - }; + }; + };
- pinctrl_adc1_default: adc1_default { - function = "ADC1"; - groups = "ADC1"; - }; + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + };
- pinctrl_adc10_default: adc10_default { - function = "ADC10"; - groups = "ADC10"; - }; + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + };
- pinctrl_adc11_default: adc11_default { - function = "ADC11"; - groups = "ADC11"; - }; + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + };
- pinctrl_adc12_default: adc12_default { - function = "ADC12"; - groups = "ADC12"; - }; + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + };
- pinctrl_adc13_default: adc13_default { - function = "ADC13"; - groups = "ADC13"; - }; + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + };
- pinctrl_adc14_default: adc14_default { - function = "ADC14"; - groups = "ADC14"; - }; + rng: hwrng@1e6e2078 { + compatible = "timeriomem_rng"; + reg = <0x1e6e2078 0x4>; + period = <1>; + quality = <100>; + };
- pinctrl_adc15_default: adc15_default { - function = "ADC15"; - groups = "ADC15"; - }; + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + };
- pinctrl_adc2_default: adc2_default { - function = "ADC2"; - groups = "ADC2"; - }; + adc: adc@1e6e9000 { + compatible = "aspeed,ast2500-adc"; + reg = <0x1e6e9000 0xb0>; + #io-channel-cells = <1>; + status = "disabled"; + };
- pinctrl_adc3_default: adc3_default { - function = "ADC3"; - groups = "ADC3"; - }; + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + };
- pinctrl_adc4_default: adc4_default { - function = "ADC4"; - groups = "ADC4"; - }; + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + interrupt-controller; + };
- pinctrl_adc5_default: adc5_default { - function = "ADC5"; - groups = "ADC5"; - }; + timer: timer@1e782000 { + /* This timer is a Faraday FTTMR010 derivative */ + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers only one + // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + };
- pinctrl_adc6_default: adc6_default { - function = "ADC6"; - groups = "ADC6"; - }; + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + };
- pinctrl_adc7_default: adc7_default { - function = "ADC7"; - groups = "ADC7"; - }; + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x20>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + };
- pinctrl_adc8_default: adc8_default { - function = "ADC8"; - groups = "ADC8"; - }; + wdt1: watchdog@1e785000 { + compatible = "aspeed,wdt"; + reg = <0x1e785000 0x1c>; + interrupts = <27>; + };
- pinctrl_adc9_default: adc9_default { - function = "ADC9"; - groups = "ADC9"; - }; + wdt2: watchdog@1e785020 { + compatible = "aspeed,wdt"; + reg = <0x1e785020 0x1c>; + interrupts = <27>; + status = "disabled"; + };
- pinctrl_bmcint_default: bmcint_default { - function = "BMCINT"; - groups = "BMCINT"; - }; + wdt3: watchdog@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785040 0x1c>; + status = "disabled"; + };
- pinctrl_ddcclk_default: ddcclk_default { - function = "DDCCLK"; - groups = "DDCCLK"; - }; + pwm_tacho: pwm-tacho-controller@1e786000 { + compatible = "aspeed,ast2500-pwm-tacho"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e786000 0x1000>; + status = "disabled"; + };
- pinctrl_ddcdat_default: ddcdat_default { - function = "DDCDAT"; - groups = "DDCDAT"; - }; + vuart: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + no-loopback-test; + status = "disabled"; + };
- pinctrl_espi_default: espi_default { - function = "ESPI"; - groups = "ESPI"; - }; + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>;
- pinctrl_fwspics1_default: fwspics1_default { - function = "FWSPICS1"; - groups = "FWSPICS1"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>;
- pinctrl_fwspics2_default: fwspics2_default { - function = "FWSPICS2"; - groups = "FWSPICS2"; - }; + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2500-lpc-bmc"; + reg = <0x0 0x80>; + };
- pinctrl_gpid0_default: gpid0_default { - function = "GPID0"; - groups = "GPID0"; - }; + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>;
- pinctrl_gpid2_default: gpid2_default { - function = "GPID2"; - groups = "GPID2"; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>;
- pinctrl_gpid4_default: gpid4_default { - function = "GPID4"; - groups = "GPID4"; + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + status = "disabled"; };
- pinctrl_gpid6_default: gpid6_default { - function = "GPID6"; - groups = "GPID6"; + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2500-lpc-snoop"; + reg = <0x0 0x80>; + interrupts = <8>; + status = "disabled"; };
- pinctrl_gpie0_default: gpie0_default { - function = "GPIE0"; - groups = "GPIE0"; + lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; };
- pinctrl_gpie2_default: gpie2_default { - function = "GPIE2"; - groups = "GPIE2"; + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; };
- pinctrl_gpie4_default: gpie4_default { - function = "GPIE4"; - groups = "GPIE4"; + ibt: ibt@c0 { + compatible = "aspeed,ast2500-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <8>; + status = "disabled"; }; + }; + };
- pinctrl_gpie6_default: gpie6_default { - function = "GPIE6"; - groups = "GPIE6"; - }; + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + };
- pinctrl_i2c10_default: i2c10_default { - function = "I2C10"; - groups = "I2C10"; - }; + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + };
- pinctrl_i2c11_default: i2c11_default { - function = "I2C11"; - groups = "I2C11"; - }; + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + };
- pinctrl_i2c12_default: i2c12_default { - function = "I2C12"; - groups = "I2C12"; - }; + i2c: i2c@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + }; + }; +};
- pinctrl_i2c13_default: i2c13_default { - function = "I2C13"; - groups = "I2C13"; - }; +&i2c { + i2c_ic: interrupt-controller@0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; + };
- pinctrl_i2c14_default: i2c14_default { - function = "I2C14"; - groups = "I2C14"; - }; + i2c0: i2c-bus@40 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x40 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <0>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + };
- pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; + i2c1: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x80 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <1>; + interrupt-parent = <&i2c_ic>; + status = "disabled"; + /* Does not need pinctrl properties */ + };
- pinctrl_i2c4_default: i2c4_default { - function = "I2C4"; - groups = "I2C4"; - }; + i2c2: i2c-bus@c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0xc0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <2>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + };
- pinctrl_i2c5_default: i2c5_default { - function = "I2C5"; - groups = "I2C5"; - }; + i2c3: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x100 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <3>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + };
- pinctrl_i2c6_default: i2c6_default { - function = "I2C6"; - groups = "I2C6"; - }; + i2c4: i2c-bus@140 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x140 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <4>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + };
- pinctrl_i2c7_default: i2c7_default { - function = "I2C7"; - groups = "I2C7"; - }; + i2c5: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x180 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <5>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + };
- pinctrl_i2c8_default: i2c8_default { - function = "I2C8"; - groups = "I2C8"; - }; + i2c6: i2c-bus@1c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x1c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <6>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + };
- pinctrl_i2c9_default: i2c9_default { - function = "I2C9"; - groups = "I2C9"; - }; + i2c7: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x300 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <7>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + };
- pinctrl_lad0_default: lad0_default { - function = "LAD0"; - groups = "LAD0"; - }; + i2c8: i2c-bus@340 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x340 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <8>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + };
- pinctrl_lad1_default: lad1_default { - function = "LAD1"; - groups = "LAD1"; - }; + i2c9: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x380 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <9>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + };
- pinctrl_lad2_default: lad2_default { - function = "LAD2"; - groups = "LAD2"; - }; + i2c10: i2c-bus@3c0 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x3c0 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <10>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + };
- pinctrl_lad3_default: lad3_default { - function = "LAD3"; - groups = "LAD3"; - }; + i2c11: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x400 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <11>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + };
- pinctrl_lclk_default: lclk_default { - function = "LCLK"; - groups = "LCLK"; - }; + i2c12: i2c-bus@440 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x440 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <12>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + };
- pinctrl_lframe_default: lframe_default { - function = "LFRAME"; - groups = "LFRAME"; - }; + i2c13: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + reg = <0x480 0x40>; + compatible = "aspeed,ast2500-i2c-bus"; + bus-frequency = <100000>; + interrupts = <13>; + interrupt-parent = <&i2c_ic>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; +};
- pinctrl_lpchc_default: lpchc_default { - function = "LPCHC"; - groups = "LPCHC"; - }; +&pinctrl { + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + };
- pinctrl_lpcpd_default: lpcpd_default { - function = "LPCPD"; - groups = "LPCPD"; - }; + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + };
- pinctrl_lpcplus_default: lpcplus_default { - function = "LPCPLUS"; - groups = "LPCPLUS"; - }; + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + };
- pinctrl_lpcpme_default: lpcpme_default { - function = "LPCPME"; - groups = "LPCPME"; - }; + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + };
- pinctrl_lpcrst_default: lpcrst_default { - function = "LPCRST"; - groups = "LPCRST"; - }; + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + };
- pinctrl_lpcsmi_default: lpcsmi_default { - function = "LPCSMI"; - groups = "LPCSMI"; - }; + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + };
- pinctrl_lsirq_default: lsirq_default { - function = "LSIRQ"; - groups = "LSIRQ"; - }; + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + };
- pinctrl_mac1link_default: mac1link_default { - function = "MAC1LINK"; - groups = "MAC1LINK"; - }; + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + };
- pinctrl_mac2link_default: mac2link_default { - function = "MAC2LINK"; - groups = "MAC2LINK"; - }; + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + };
- pinctrl_mdio1_default: mdio1_default { - function = "MDIO1"; - groups = "MDIO1"; - }; + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + };
- pinctrl_mdio2_default: mdio2_default { - function = "MDIO2"; - groups = "MDIO2"; - }; + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + };
- pinctrl_ncts1_default: ncts1_default { - function = "NCTS1"; - groups = "NCTS1"; - }; + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + };
- pinctrl_ncts2_default: ncts2_default { - function = "NCTS2"; - groups = "NCTS2"; - }; + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + };
- pinctrl_ncts3_default: ncts3_default { - function = "NCTS3"; - groups = "NCTS3"; - }; + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + };
- pinctrl_ncts4_default: ncts4_default { - function = "NCTS4"; - groups = "NCTS4"; - }; + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + };
- pinctrl_ndcd1_default: ndcd1_default { - function = "NDCD1"; - groups = "NDCD1"; - }; + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + };
- pinctrl_ndcd2_default: ndcd2_default { - function = "NDCD2"; - groups = "NDCD2"; - }; + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + };
- pinctrl_ndcd3_default: ndcd3_default { - function = "NDCD3"; - groups = "NDCD3"; - }; + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + };
- pinctrl_ndcd4_default: ndcd4_default { - function = "NDCD4"; - groups = "NDCD4"; - }; + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + };
- pinctrl_ndsr1_default: ndsr1_default { - function = "NDSR1"; - groups = "NDSR1"; - }; + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + };
- pinctrl_ndsr2_default: ndsr2_default { - function = "NDSR2"; - groups = "NDSR2"; - }; + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + };
- pinctrl_ndsr3_default: ndsr3_default { - function = "NDSR3"; - groups = "NDSR3"; - }; + pinctrl_fwspics1_default: fwspics1_default { + function = "FWSPICS1"; + groups = "FWSPICS1"; + };
- pinctrl_ndsr4_default: ndsr4_default { - function = "NDSR4"; - groups = "NDSR4"; - }; + pinctrl_fwspics2_default: fwspics2_default { + function = "FWSPICS2"; + groups = "FWSPICS2"; + };
- pinctrl_ndtr1_default: ndtr1_default { - function = "NDTR1"; - groups = "NDTR1"; - }; + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + };
- pinctrl_ndtr2_default: ndtr2_default { - function = "NDTR2"; - groups = "NDTR2"; - }; + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + };
- pinctrl_ndtr3_default: ndtr3_default { - function = "NDTR3"; - groups = "NDTR3"; - }; + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + };
- pinctrl_ndtr4_default: ndtr4_default { - function = "NDTR4"; - groups = "NDTR4"; - }; + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + };
- pinctrl_nri1_default: nri1_default { - function = "NRI1"; - groups = "NRI1"; - }; + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + };
- pinctrl_nri2_default: nri2_default { - function = "NRI2"; - groups = "NRI2"; - }; + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + };
- pinctrl_nri3_default: nri3_default { - function = "NRI3"; - groups = "NRI3"; - }; + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + };
- pinctrl_nri4_default: nri4_default { - function = "NRI4"; - groups = "NRI4"; - }; + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + };
- pinctrl_nrts1_default: nrts1_default { - function = "NRTS1"; - groups = "NRTS1"; - }; + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + };
- pinctrl_nrts2_default: nrts2_default { - function = "NRTS2"; - groups = "NRTS2"; - }; + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + };
- pinctrl_nrts3_default: nrts3_default { - function = "NRTS3"; - groups = "NRTS3"; - }; + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + };
- pinctrl_nrts4_default: nrts4_default { - function = "NRTS4"; - groups = "NRTS4"; - }; + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + };
- pinctrl_oscclk_default: oscclk_default { - function = "OSCCLK"; - groups = "OSCCLK"; - }; + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + };
- pinctrl_pewake_default: pewake_default { - function = "PEWAKE"; - groups = "PEWAKE"; - }; + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + };
- pinctrl_pnor_default: pnor_default { - function = "PNOR"; - groups = "PNOR"; - }; + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + };
- pinctrl_pwm0_default: pwm0_default { - function = "PWM0"; - groups = "PWM0"; - }; + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + };
- pinctrl_pwm1_default: pwm1_default { - function = "PWM1"; - groups = "PWM1"; - }; + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + };
- pinctrl_pwm2_default: pwm2_default { - function = "PWM2"; - groups = "PWM2"; - }; + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + };
- pinctrl_pwm3_default: pwm3_default { - function = "PWM3"; - groups = "PWM3"; - }; + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + };
- pinctrl_pwm4_default: pwm4_default { - function = "PWM4"; - groups = "PWM4"; - }; + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + };
- pinctrl_pwm5_default: pwm5_default { - function = "PWM5"; - groups = "PWM5"; - }; + pinctrl_lad0_default: lad0_default { + function = "LAD0"; + groups = "LAD0"; + };
- pinctrl_pwm6_default: pwm6_default { - function = "PWM6"; - groups = "PWM6"; - }; + pinctrl_lad1_default: lad1_default { + function = "LAD1"; + groups = "LAD1"; + };
- pinctrl_pwm7_default: pwm7_default { - function = "PWM7"; - groups = "PWM7"; - }; + pinctrl_lad2_default: lad2_default { + function = "LAD2"; + groups = "LAD2"; + };
- pinctrl_rgmii1_default: rgmii1_default { - function = "RGMII1"; - groups = "RGMII1"; - }; + pinctrl_lad3_default: lad3_default { + function = "LAD3"; + groups = "LAD3"; + };
- pinctrl_rgmii2_default: rgmii2_default { - function = "RGMII2"; - groups = "RGMII2"; - }; + pinctrl_lclk_default: lclk_default { + function = "LCLK"; + groups = "LCLK"; + };
- pinctrl_rmii1_default: rmii1_default { - function = "RMII1"; - groups = "RMII1"; - }; + pinctrl_lframe_default: lframe_default { + function = "LFRAME"; + groups = "LFRAME"; + };
- pinctrl_rmii2_default: rmii2_default { - function = "RMII2"; - groups = "RMII2"; - }; + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + };
- pinctrl_rxd1_default: rxd1_default { - function = "RXD1"; - groups = "RXD1"; - }; + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + };
- pinctrl_rxd2_default: rxd2_default { - function = "RXD2"; - groups = "RXD2"; - }; + pinctrl_lpcplus_default: lpcplus_default { + function = "LPCPLUS"; + groups = "LPCPLUS"; + };
- pinctrl_rxd3_default: rxd3_default { - function = "RXD3"; - groups = "RXD3"; - }; + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + };
- pinctrl_rxd4_default: rxd4_default { - function = "RXD4"; - groups = "RXD4"; - }; + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + };
- pinctrl_salt1_default: salt1_default { - function = "SALT1"; - groups = "SALT1"; - }; + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + };
- pinctrl_salt10_default: salt10_default { - function = "SALT10"; - groups = "SALT10"; - }; + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + };
- pinctrl_salt11_default: salt11_default { - function = "SALT11"; - groups = "SALT11"; - }; + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + };
- pinctrl_salt12_default: salt12_default { - function = "SALT12"; - groups = "SALT12"; - }; + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + };
- pinctrl_salt13_default: salt13_default { - function = "SALT13"; - groups = "SALT13"; - }; + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + };
- pinctrl_salt14_default: salt14_default { - function = "SALT14"; - groups = "SALT14"; - }; + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + };
- pinctrl_salt2_default: salt2_default { - function = "SALT2"; - groups = "SALT2"; - }; + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + };
- pinctrl_salt3_default: salt3_default { - function = "SALT3"; - groups = "SALT3"; - }; + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + };
- pinctrl_salt4_default: salt4_default { - function = "SALT4"; - groups = "SALT4"; - }; + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + };
- pinctrl_salt5_default: salt5_default { - function = "SALT5"; - groups = "SALT5"; - }; + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + };
- pinctrl_salt6_default: salt6_default { - function = "SALT6"; - groups = "SALT6"; - }; + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + };
- pinctrl_salt7_default: salt7_default { - function = "SALT7"; - groups = "SALT7"; - }; + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + };
- pinctrl_salt8_default: salt8_default { - function = "SALT8"; - groups = "SALT8"; - }; + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + };
- pinctrl_salt9_default: salt9_default { - function = "SALT9"; - groups = "SALT9"; - }; + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + };
- pinctrl_scl1_default: scl1_default { - function = "SCL1"; - groups = "SCL1"; - }; + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + };
- pinctrl_scl2_default: scl2_default { - function = "SCL2"; - groups = "SCL2"; - }; + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + };
- pinctrl_sd1_default: sd1_default { - function = "SD1"; - groups = "SD1"; - }; + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + };
- pinctrl_sd2_default: sd2_default { - function = "SD2"; - groups = "SD2"; - }; + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + };
- pinctrl_sda1_default: sda1_default { - function = "SDA1"; - groups = "SDA1"; - }; + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + };
- pinctrl_sda2_default: sda2_default { - function = "SDA2"; - groups = "SDA2"; - }; + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + };
- pinctrl_sgps1_default: sgps1_default { - function = "SGPS1"; - groups = "SGPS1"; - }; + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + };
- pinctrl_sgps2_default: sgps2_default { - function = "SGPS2"; - groups = "SGPS2"; - }; + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + };
- pinctrl_sioonctrl_default: sioonctrl_default { - function = "SIOONCTRL"; - groups = "SIOONCTRL"; - }; + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + };
- pinctrl_siopbi_default: siopbi_default { - function = "SIOPBI"; - groups = "SIOPBI"; - }; + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + };
- pinctrl_siopbo_default: siopbo_default { - function = "SIOPBO"; - groups = "SIOPBO"; - }; + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + };
- pinctrl_siopwreq_default: siopwreq_default { - function = "SIOPWREQ"; - groups = "SIOPWREQ"; - }; + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + };
- pinctrl_siopwrgd_default: siopwrgd_default { - function = "SIOPWRGD"; - groups = "SIOPWRGD"; - }; + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + };
- pinctrl_sios3_default: sios3_default { - function = "SIOS3"; - groups = "SIOS3"; - }; + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + };
- pinctrl_sios5_default: sios5_default { - function = "SIOS5"; - groups = "SIOS5"; - }; + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + };
- pinctrl_siosci_default: siosci_default { - function = "SIOSCI"; - groups = "SIOSCI"; - }; + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + };
- pinctrl_spi1_default: spi1_default { - function = "SPI1"; - groups = "SPI1"; - }; + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + };
- pinctrl_spi1cs1_default: spi1cs1_default { - function = "SPI1CS1"; - groups = "SPI1CS1"; - }; + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + };
- pinctrl_spi1debug_default: spi1debug_default { - function = "SPI1DEBUG"; - groups = "SPI1DEBUG"; - }; + pinctrl_pnor_default: pnor_default { + function = "PNOR"; + groups = "PNOR"; + };
- pinctrl_spi1passthru_default: spi1passthru_default { - function = "SPI1PASSTHRU"; - groups = "SPI1PASSTHRU"; - }; + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + };
- pinctrl_spi2ck_default: spi2ck_default { - function = "SPI2CK"; - groups = "SPI2CK"; - }; + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + };
- pinctrl_spi2cs0_default: spi2cs0_default { - function = "SPI2CS0"; - groups = "SPI2CS0"; - }; + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + };
- pinctrl_spi2cs1_default: spi2cs1_default { - function = "SPI2CS1"; - groups = "SPI2CS1"; - }; + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + };
- pinctrl_spi2miso_default: spi2miso_default { - function = "SPI2MISO"; - groups = "SPI2MISO"; - }; + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + };
- pinctrl_spi2mosi_default: spi2mosi_default { - function = "SPI2MOSI"; - groups = "SPI2MOSI"; - }; + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + };
- pinctrl_timer3_default: timer3_default { - function = "TIMER3"; - groups = "TIMER3"; - }; + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + };
- pinctrl_timer4_default: timer4_default { - function = "TIMER4"; - groups = "TIMER4"; - }; + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + };
- pinctrl_timer5_default: timer5_default { - function = "TIMER5"; - groups = "TIMER5"; - }; + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + };
- pinctrl_timer6_default: timer6_default { - function = "TIMER6"; - groups = "TIMER6"; - }; + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + };
- pinctrl_timer7_default: timer7_default { - function = "TIMER7"; - groups = "TIMER7"; - }; + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + };
- pinctrl_timer8_default: timer8_default { - function = "TIMER8"; - groups = "TIMER8"; - }; + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + };
- pinctrl_txd1_default: txd1_default { - function = "TXD1"; - groups = "TXD1"; - }; + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + };
- pinctrl_txd2_default: txd2_default { - function = "TXD2"; - groups = "TXD2"; - }; + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + };
- pinctrl_txd3_default: txd3_default { - function = "TXD3"; - groups = "TXD3"; - }; + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + };
- pinctrl_txd4_default: txd4_default { - function = "TXD4"; - groups = "TXD4"; - }; + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + };
- pinctrl_uart6_default: uart6_default { - function = "UART6"; - groups = "UART6"; - }; + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + };
- pinctrl_usbcki_default: usbcki_default { - function = "USBCKI"; - groups = "USBCKI"; - }; + pinctrl_salt10_default: salt10_default { + function = "SALT10"; + groups = "SALT10"; + };
- pinctrl_vgabiosrom_default: vgabiosrom_default { - function = "VGABIOSROM"; - groups = "VGABIOSROM"; - }; + pinctrl_salt11_default: salt11_default { + function = "SALT11"; + groups = "SALT11"; + };
- pinctrl_vgahs_default: vgahs_default { - function = "VGAHS"; - groups = "VGAHS"; - }; + pinctrl_salt12_default: salt12_default { + function = "SALT12"; + groups = "SALT12"; + };
- pinctrl_vgavs_default: vgavs_default { - function = "VGAVS"; - groups = "VGAVS"; - }; + pinctrl_salt13_default: salt13_default { + function = "SALT13"; + groups = "SALT13"; + };
- pinctrl_vpi24_default: vpi24_default { - function = "VPI24"; - groups = "VPI24"; - }; + pinctrl_salt14_default: salt14_default { + function = "SALT14"; + groups = "SALT14"; + };
- pinctrl_vpo_default: vpo_default { - function = "VPO"; - groups = "VPO"; - }; + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + };
- pinctrl_wdtrst1_default: wdtrst1_default { - function = "WDTRST1"; - groups = "WDTRST1"; - }; + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + };
- pinctrl_wdtrst2_default: wdtrst2_default { - function = "WDTRST2"; - groups = "WDTRST2"; - }; + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + };
- }; - }; + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + };
- clk_hpll: clk_hpll@1e6e2024 { - #clock-cells = <0>; - compatible = "aspeed,g5-hpll-clock"; - reg = <0x1e6e2024 0x4>; - clocks = <&clk_clkin>; - }; + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + };
- clk_ahb: clk_ahb@1e6e2070 { - #clock-cells = <0>; - compatible = "aspeed,g5-ahb-clock"; - reg = <0x1e6e2070 0x4>; - clocks = <&clk_hpll>; - }; + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + };
- clk_apb: clk_apb@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,g5-apb-clock"; - reg = <0x1e6e2008 0x4>; - clocks = <&clk_hpll>; - }; + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + };
- clk_uart: clk_uart@1e6e2008 { - #clock-cells = <0>; - compatible = "aspeed,uart-clock"; - reg = <0x1e6e202c 0x4>; - }; + pinctrl_salt9_default: salt9_default { + function = "SALT9"; + groups = "SALT9"; + };
- gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - }; + pinctrl_scl1_default: scl1_default { + function = "SCL1"; + groups = "SCL1"; + };
- sram@1e720000 { - compatible = "mmio-sram"; - reg = <0x1e720000 0x9000>; // 36K - }; + pinctrl_scl2_default: scl2_default { + function = "SCL2"; + groups = "SCL2"; + };
- gpio: gpio@1e780000 { - #gpio-cells = <2>; - gpio-controller; - compatible = "aspeed,ast2500-gpio"; - reg = <0x1e780000 0x1000>; - interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; - interrupt-controller; - }; + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + };
- timer: timer@1e782000 { - compatible = "aspeed,ast2400-timer"; - reg = <0x1e782000 0x90>; - // The moxart_timer driver registers only one - // interrupt and assumes it's for timer 1 - //interrupts = <16 17 18 35 36 37 38 39>; - interrupts = <16>; - clocks = <&clk_apb>; - }; + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + };
+ pinctrl_sda1_default: sda1_default { + function = "SDA1"; + groups = "SDA1"; + };
- wdt1: wdt@1e785000 { - compatible = "aspeed,wdt"; - reg = <0x1e785000 0x1c>; - interrupts = <27>; - }; + pinctrl_sda2_default: sda2_default { + function = "SDA2"; + groups = "SDA2"; + };
- wdt2: wdt@1e785020 { - compatible = "aspeed,wdt"; - reg = <0x1e785020 0x1c>; - interrupts = <27>; - status = "disabled"; - }; + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + };
- wdt3: wdt@1e785040 { - compatible = "aspeed,wdt"; - reg = <0x1e785074 0x1c>; - status = "disabled"; - }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + };
- uart1: serial@1e783000 { - compatible = "ns16550a"; - reg = <0x1e783000 0x1000>; - reg-shift = <2>; - interrupts = <9>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + };
- lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + };
- #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1e789000 0x1000>; + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + };
- lpc_bmc: lpc-bmc@0 { - compatible = "aspeed,ast2500-lpc-bmc"; - reg = <0x0 0x80>; - }; + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + };
- lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + };
- #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x80 0x1e0>; + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + };
- reg-io-width = <4>; + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + };
- lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; - }; - }; - }; + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + };
- uart2: serial@1e78d000 { - compatible = "ns16550a"; - reg = <0x1e78d000 0x1000>; - reg-shift = <2>; - interrupts = <32>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + };
- uart3: serial@1e78e000 { - compatible = "ns16550a"; - reg = <0x1e78e000 0x1000>; - reg-shift = <2>; - interrupts = <33>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + };
- uart4: serial@1e78f000 { - compatible = "ns16550a"; - reg = <0x1e78f000 0x1000>; - reg-shift = <2>; - interrupts = <34>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + };
- uart5: serial@1e784000 { - compatible = "ns16550a"; - reg = <0x1e784000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - current-speed = <38400>; - no-loopback-test; - status = "disabled"; - }; + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + };
- uart6: serial@1e787000 { - compatible = "ns16550a"; - reg = <0x1e787000 0x1000>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - }; + pinctrl_spi2ck_default: spi2ck_default { + function = "SPI2CK"; + groups = "SPI2CK"; + }; + + pinctrl_spi2cs0_default: spi2cs0_default { + function = "SPI2CS0"; + groups = "SPI2CS0"; + }; + + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; + + pinctrl_spi2miso_default: spi2miso_default { + function = "SPI2MISO"; + groups = "SPI2MISO"; + }; + + pinctrl_spi2mosi_default: spi2mosi_default { + function = "SPI2MOSI"; + groups = "SPI2MOSI"; + }; + + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; + + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_usb2ah_default: usb2ah_default { + function = "USB2AH"; + groups = "USB2AH"; + }; + + pinctrl_usb11bhid_default: usb11bhid_default { + function = "USB11BHID"; + groups = "USB11BHID"; + }; + + pinctrl_usb2bh_default: usb2bh_default { + function = "USB2BH"; + groups = "USB2BH"; + }; + + pinctrl_vgabiosrom_default: vgabiosrom_default { + function = "VGABIOSROM"; + groups = "VGABIOSROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpo_default: vpo_default { + function = "VPO"; + groups = "VPO"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; }; };
On Fri, 21 Sep 2018 at 16:09, Cédric Le Goater clg@kaod.org wrote:
This is a large update of the AST2500 Soc DTS file bringing it to the level of commit 927c2fc2db19 :
Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register addressThere are some differences on the compatibility property names. scu, reset and clock drivers are also different.
You made the required changes in this patch? We should document those so we know how to sync it next time.
If it's possible, we can also add compatible properties to the Linux version of the device tree to make syncing easier.
Signed-off-by: Cédric Le Goater clg@kaod.org
Reviewed-by: Joel Stanley joel@jms.id.au
Cheers,
Joel
On 09/25/2018 02:21 AM, Joel Stanley wrote:
On Fri, 21 Sep 2018 at 16:09, Cédric Le Goater clg@kaod.org wrote:
This is a large update of the AST2500 Soc DTS file bringing it to the level of commit 927c2fc2db19 :
Author: Joel Stanley <joel@jms.id.au> Date: Sat Jun 2 01:18:53 2018 -0700 ARM: dts: aspeed: Fix hwrng register addressThere are some differences on the compatibility property names. scu, reset and clock drivers are also different.
You made the required changes in this patch? We should document those so we know how to sync it next time.
I only changed where the nodes were defined in the u-boot DTS file. As for the sync, it is necessarily manual :/ See below for the differences.
The clocks are defined in another DTS file in u-boot. May be there is room for improvements on both sides tough.
Syncing the "compatible" strings would be a good thing.
If it's possible, we can also add compatible properties to the Linux version of the device tree to make syncing easier.
Signed-off-by: Cédric Le Goater clg@kaod.org
Reviewed-by: Joel Stanley joel@jms.id.au
Thanks,
C.
--- linux/arch/arm/boot/dts/aspeed-g5.dtsi 2018-06-14 16:30:01.790506371 +0200 +++ u-boot/arch/arm//dts/ast2500.dtsi 2018-09-22 17:35:14.302476829 +0200 @@ -1,5 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include <dt-bindings/clock/aspeed-clock.h> +/* + * This device tree is copied from + * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/... + */ +#include "skeleton.dtsi"
/ { model = "Aspeed BMC"; @@ -59,7 +62,6 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-fmc"; - clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; interrupts = <19>; flash@0 { @@ -85,7 +87,6 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; flash@0 { reg = < 0 >; @@ -105,7 +106,6 @@ #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; - clocks = <&syscon ASPEED_CLK_AHB>; status = "disabled"; flash@0 { reg = < 0 >; @@ -131,7 +131,6 @@ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e660000 0x180>; interrupts = <2>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; status = "disabled"; };
@@ -139,7 +138,6 @@ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e680000 0x180>; interrupts = <3>; - clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; status = "disabled"; };
@@ -147,7 +145,6 @@ compatible = "aspeed,ast2500-ehci", "generic-ehci"; reg = <0x1e6a1000 0x100>; interrupts = <5>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; status = "disabled"; };
@@ -155,7 +152,6 @@ compatible = "aspeed,ast2500-ehci", "generic-ehci"; reg = <0x1e6a3000 0x100>; interrupts = <13>; - clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; status = "disabled"; };
@@ -164,7 +160,6 @@ reg = <0x1e6b0000 0x100>; interrupts = <14>; #ports = <2>; - clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; status = "disabled"; };
@@ -175,10 +170,8 @@ ranges;
syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; + compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; - #address-cells = <1>; - #size-cells = <0>; #clock-cells = <1>; #reset-cells = <1>;
@@ -189,6 +182,39 @@ }; };
+ clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + rng: hwrng@1e6e2078 { compatible = "timeriomem_rng"; reg = <0x1e6e2078 0x4>; @@ -205,8 +231,6 @@ adc: adc@1e6e9000 { compatible = "aspeed,ast2500-adc"; reg = <0x1e6e9000 0xb0>; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_ADC>; #io-channel-cells = <1>; status = "disabled"; }; @@ -223,7 +247,6 @@ reg = <0x1e780000 0x1000>; interrupts = <20>; gpio-ranges = <&pinctrl 0 0 220>; - clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; };
@@ -231,9 +254,11 @@ /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; reg = <0x1e782000 0x90>; - interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&syscon ASPEED_CLK_APB>; - clock-names = "PCLK"; + // The moxart_timer driver registers only one + // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; };
uart1: serial@1e783000 { @@ -241,8 +266,7 @@ reg = <0x1e783000 0x20>; reg-shift = <2>; interrupts = <9>; - clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; - resets = <&lpc_reset 4>; + clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; @@ -252,27 +276,28 @@ reg = <0x1e784000 0x20>; reg-shift = <2>; interrupts = <10>; - clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; + clocks = <&clk_uart>; + current-speed = <38400>; no-loopback-test; status = "disabled"; };
wdt1: watchdog@1e785000 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785000 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; + compatible = "aspeed,wdt"; + reg = <0x1e785000 0x1c>; + interrupts = <27>; };
wdt2: watchdog@1e785020 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785020 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; + compatible = "aspeed,wdt"; + reg = <0x1e785020 0x1c>; + interrupts = <27>; + status = "disabled"; };
wdt3: watchdog@1e785040 { - compatible = "aspeed,ast2500-wdt"; - reg = <0x1e785040 0x20>; - clocks = <&syscon ASPEED_CLK_APB>; + compatible = "aspeed,wdt"; + reg = <0x1e785040 0x1c>; status = "disabled"; };
@@ -281,8 +306,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x1e786000 0x1000>; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_PWM>; status = "disabled"; };
@@ -291,7 +314,6 @@ reg = <0x1e787000 0x40>; reg-shift = <2>; interrupts = <8>; - clocks = <&syscon ASPEED_CLK_APB>; no-loopback-test; status = "disabled"; }; @@ -321,7 +343,6 @@ lpc_ctrl: lpc-ctrl@0 { compatible = "aspeed,ast2500-lpc-ctrl"; reg = <0x0 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; status = "disabled"; };
@@ -357,8 +378,7 @@ reg = <0x1e78d000 0x20>; reg-shift = <2>; interrupts = <32>; - clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; - resets = <&lpc_reset 5>; + clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; @@ -368,8 +388,7 @@ reg = <0x1e78e000 0x20>; reg-shift = <2>; interrupts = <33>; - clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; - resets = <&lpc_reset 6>; + clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; @@ -379,8 +398,7 @@ reg = <0x1e78f000 0x20>; reg-shift = <2>; interrupts = <34>; - clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; - resets = <&lpc_reset 7>; + clocks = <&clk_uart>; no-loopback-test; status = "disabled"; }; @@ -411,8 +429,6 @@
reg = <0x40 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <0>; interrupt-parent = <&i2c_ic>; @@ -427,8 +443,6 @@
reg = <0x80 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <1>; interrupt-parent = <&i2c_ic>; @@ -443,8 +457,6 @@
reg = <0xc0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <2>; interrupt-parent = <&i2c_ic>; @@ -460,8 +472,6 @@
reg = <0x100 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <3>; interrupt-parent = <&i2c_ic>; @@ -477,8 +487,6 @@
reg = <0x140 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <4>; interrupt-parent = <&i2c_ic>; @@ -494,8 +502,6 @@
reg = <0x180 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <5>; interrupt-parent = <&i2c_ic>; @@ -511,8 +517,6 @@
reg = <0x1c0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <6>; interrupt-parent = <&i2c_ic>; @@ -528,8 +532,6 @@
reg = <0x300 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <7>; interrupt-parent = <&i2c_ic>; @@ -545,8 +547,6 @@
reg = <0x340 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <8>; interrupt-parent = <&i2c_ic>; @@ -562,8 +562,6 @@
reg = <0x380 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <9>; interrupt-parent = <&i2c_ic>; @@ -579,8 +577,6 @@
reg = <0x3c0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <10>; interrupt-parent = <&i2c_ic>; @@ -596,8 +592,6 @@
reg = <0x400 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <11>; interrupt-parent = <&i2c_ic>; @@ -613,8 +607,6 @@
reg = <0x440 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <12>; interrupt-parent = <&i2c_ic>; @@ -630,8 +622,6 @@
reg = <0x480 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB>; - resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <13>; interrupt-parent = <&i2c_ic>;
Signed-off-by: Cédric Le Goater clg@kaod.org Reviewed-by: Jagan Teki jagan@openedev.com ---
Changes since v1:
- moved the update of the ast2500 SoC DTS file in another patch
arch/arm/dts/ast2500-evb.dts | 15 +++++++++++++++ arch/arm/dts/ast2500-u-boot.dtsi | 12 ++++++++++++ 2 files changed, 27 insertions(+)
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index 723941ac0bee..4d891b55391b 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -11,6 +11,10 @@ chosen { stdout-path = &uart5; }; + + aliases { + spi0 = &fmc; + }; };
&uart5 { @@ -36,3 +40,14 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&fmc { + status = "okay"; + flash@0 { + compatible = "spi-flash", "sst,w25q256"; + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 7f80bad7d050..6cfdf3ba5413 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -70,3 +70,15 @@ &mac1 { clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; }; + +&fmc { + clocks = <&scu BCLK_HCLK>; +}; + +&spi1 { + clocks = <&scu BCLK_HCLK>; +}; + +&spi2 { + clocks = <&scu BCLK_HCLK>; +};
On Fri, 21 Sep 2018 at 16:09, Cédric Le Goater clg@kaod.org wrote:
Signed-off-by: Cédric Le Goater clg@kaod.org Reviewed-by: Jagan Teki jagan@openedev.com
Reviewed-by: Joel Stanley joel@jms.id.au
participants (2)
-
Cédric Le Goater -
Joel Stanley