SSD2828 can take pixel data coming from a parallel LCD interface and translate it on the flight into MIPI DSI interface for driving a MIPI compatible TFT display. SSD2828 is configured over SPI interface, which may or may not have MISO pin wired up on some hardware. So a write-only SPI mode also has to be supported.

The SSD2828 support code is implemented as a utility function and needs to be called from real display drivers, which are responsible for driving parallel LCD hardware in front of the video pipeline. The usage instructions are provided as comments in the header file.

Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- drivers/video/Makefile | 1 + drivers/video/ssd2828.c | 421 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/video/ssd2828.h | 123 ++++++++++++++ 3 files changed, 545 insertions(+) create mode 100644 drivers/video/ssd2828.c create mode 100644 drivers/video/ssd2828.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile index d4fe1aa..e29dc4f 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o +obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c new file mode 100644 index 0000000..566ec19 --- /dev/null +++ b/drivers/video/ssd2828.c @@ -0,0 +1,421 @@ +/* + * (C) 2015 Siarhei Siamashka siarhei.siamashka@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Support for the SSD2828 bridge chip, which can take pixel data coming + * from a parallel LCD interface and translate it on the flight into MIPI DSI + * interface for driving a MIPI compatible TFT display. + */ + +#include <common.h> +#include <mipi_display.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> + +#include "videomodes.h" +#include "ssd2828.h" + +#define SSD2828_DIR 0xB0 +#define SSD2828_VICR1 0xB1 +#define SSD2828_VICR2 0xB2 +#define SSD2828_VICR3 0xB3 +#define SSD2828_VICR4 0xB4 +#define SSD2828_VICR5 0xB5 +#define SSD2828_VICR6 0xB6 +#define SSD2828_CFGR 0xB7 +#define SSD2828_VCR 0xB8 +#define SSD2828_PCR 0xB9 +#define SSD2828_PLCR 0xBA +#define SSD2828_CCR 0xBB +#define SSD2828_PSCR1 0xBC +#define SSD2828_PSCR2 0xBD +#define SSD2828_PSCR3 0xBE +#define SSD2828_PDR 0xBF +#define SSD2828_OCR 0xC0 +#define SSD2828_MRSR 0xC1 +#define SSD2828_RDCR 0xC2 +#define SSD2828_ARSR 0xC3 +#define SSD2828_LCR 0xC4 +#define SSD2828_ICR 0xC5 +#define SSD2828_ISR 0xC6 +#define SSD2828_ESR 0xC7 +#define SSD2828_DAR1 0xC9 +#define SSD2828_DAR2 0xCA +#define SSD2828_DAR3 0xCB +#define SSD2828_DAR4 0xCC +#define SSD2828_DAR5 0xCD +#define SSD2828_DAR6 0xCE +#define SSD2828_HTTR1 0xCF +#define SSD2828_HTTR2 0xD0 +#define SSD2828_LRTR1 0xD1 +#define SSD2828_LRTR2 0xD2 +#define SSD2828_TSR 0xD3 +#define SSD2828_LRR 0xD4 +#define SSD2828_PLLR 0xD5 +#define SSD2828_TR 0xD6 +#define SSD2828_TECR 0xD7 +#define SSD2828_ACR1 0xD8 +#define SSD2828_ACR2 0xD9 +#define SSD2828_ACR3 0xDA +#define SSD2828_ACR4 0xDB +#define SSD2828_IOCR 0xDC +#define SSD2828_VICR7 0xDD +#define SSD2828_LCFR 0xDE +#define SSD2828_DAR7 0xDF +#define SSD2828_PUCR1 0xE0 +#define SSD2828_PUCR2 0xE1 +#define SSD2828_PUCR3 0xE2 +#define SSD2828_CBCR1 0xE9 +#define SSD2828_CBCR2 0xEA +#define SSD2828_CBSR 0xEB +#define SSD2828_ECR 0xEC +#define SSD2828_VSDR 0xED +#define SSD2828_TMR 0xEE +#define SSD2828_GPIO1 0xEF +#define SSD2828_GPIO2 0xF0 +#define SSD2828_DLYA01 0xF1 +#define SSD2828_DLYA23 0xF2 +#define SSD2828_DLYB01 0xF3 +#define SSD2828_DLYB23 0xF4 +#define SSD2828_DLYC01 0xF5 +#define SSD2828_DLYC23 0xF6 +#define SSD2828_ACR5 0xF7 +#define SSD2828_RR 0xFF + +#define SSD2828_CFGR_HS (1 << 0) +#define SSD2828_CFGR_CKE (1 << 1) +#define SSD2828_CFGR_SLP (1 << 2) +#define SSD2828_CFGR_VEN (1 << 3) +#define SSD2828_CFGR_HCLK (1 << 4) +#define SSD2828_CFGR_CSS (1 << 5) +#define SSD2828_CFGR_DCS (1 << 6) +#define SSD2828_CFGR_REN (1 << 7) +#define SSD2828_CFGR_ECD (1 << 8) +#define SSD2828_CFGR_EOT (1 << 9) +#define SSD2828_CFGR_LPE (1 << 10) +#define SSD2828_CFGR_TXD (1 << 11) + +#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2) +#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2) +#define SSD2828_VIDEO_MODE_BURST (2 << 2) + +#define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0 +#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED 1 +#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED 2 +#define SSD2828_VIDEO_PIXEL_FORMAT_24BPP 3 + +#define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F) + +/* + * SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in + * the SSD2828 documentation). The 'dout' input parameter specifies 24-bits + * of data to be written to SSD2828. Returns the lowest 16-bits of data, + * that is received back. + */ +static u32 soft_spi_xfer_24bit_3wire(const struct ssd2828_config *drv, u32 dout) +{ + int j, bitlen = 24; + u32 tmpdin = 0; + /* + * According to the "24 Bit 3 Wire SPI Interface Timing Characteristics" + * and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet, + * the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs + * at 1/8 of that after reset. So using 1 microsecond delays is safe in + * the main loop. But the delays around chip select pin manipulations + * need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in + * the worst case). + */ + const int spi_delay_us = 1; + const int spi_cs_delay_us = 2; + + gpio_set_value(drv->csx_pin, 0); + udelay(spi_cs_delay_us); + for (j = bitlen - 1; j >= 0; j--) { + gpio_set_value(drv->sck_pin, 0); + gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0); + udelay(spi_delay_us); + if (drv->sdo_pin != -1) + tmpdin = (tmpdin << 1) | gpio_get_value(drv->sdo_pin); + gpio_set_value(drv->sck_pin, 1); + udelay(spi_delay_us); + } + udelay(spi_cs_delay_us); + gpio_set_value(drv->csx_pin, 1); + udelay(spi_cs_delay_us); + return tmpdin & 0xFFFF; +} + +/* + * Read from a SSD2828 hardware register (regnum >= 0xB0) + */ +static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum) +{ + soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); + return soft_spi_xfer_24bit_3wire(cfg, 0x730000); +} + +/* + * Write to a SSD2828 hardware register (regnum >= 0xB0) + */ +static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, + u16 val) +{ + soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); + soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val); +} + +/* + * Send MIPI command to the LCD panel (cmdnum < 0xB0) + */ +static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) +{ + /* Set packet size to 1 (a single command with no parameters) */ + write_hw_register(cfg, SSD2828_PSCR1, 1); + /* Send the command */ + write_hw_register(cfg, SSD2828_PDR, cmdnum); +} + +/* + * Reset SSD2828 + */ +static void ssd2828_reset(const struct ssd2828_config *cfg) +{ + /* RESET needs 10 milliseconds according to the datasheet */ + gpio_set_value(cfg->reset_pin, 0); + mdelay(10); + gpio_set_value(cfg->reset_pin, 1); + mdelay(10); +} + +static int ssd2828_enable_gpio(const struct ssd2828_config *cfg) +{ + if (gpio_request(cfg->csx_pin, "ssd2828_csx")) { + printf("SSD2828: request for 'ssd2828_csx' pin failed\n"); + return 1; + } + if (gpio_request(cfg->sck_pin, "ssd2828_sck")) { + gpio_free(cfg->csx_pin); + printf("SSD2828: request for 'ssd2828_sck' pin failed\n"); + return 1; + } + if (gpio_request(cfg->sdi_pin, "ssd2828_sdi")) { + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + printf("SSD2828: request for 'ssd2828_sdi' pin failed\n"); + return 1; + } + if (gpio_request(cfg->reset_pin, "ssd2828_reset")) { + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + gpio_free(cfg->sdi_pin); + printf("SSD2828: request for 'ssd2828_reset' pin failed\n"); + return 1; + } + if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) { + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + gpio_free(cfg->sdi_pin); + gpio_free(cfg->reset_pin); + printf("SSD2828: request for 'ssd2828_sdo' pin failed\n"); + return 1; + } + gpio_direction_output(cfg->reset_pin, 0); + gpio_direction_output(cfg->csx_pin, 1); + gpio_direction_output(cfg->sck_pin, 1); + gpio_direction_output(cfg->sdi_pin, 1); + if (cfg->sdo_pin != -1) + gpio_direction_input(cfg->sdo_pin); + + return 0; +} + +static int ssd2828_free_gpio(const struct ssd2828_config *cfg) +{ + gpio_free(cfg->csx_pin); + gpio_free(cfg->sck_pin); + gpio_free(cfg->sdi_pin); + gpio_free(cfg->reset_pin); + if (cfg->sdo_pin != -1) + gpio_free(cfg->sdo_pin); + return 1; +} + +/* + * PLL configuration register settings. + * + * See the "PLL Configuration Register Description" in the SSD2828 datasheet. + */ +u32 construct_pll_config(u32 desired_pll_freq_kbps, u32 reference_freq_khz) +{ + u32 div_factor = 1, mul_factor, fr = 0; + u32 output_freq_kbps; + + /* The intermediate clock after division can't be less than 5MHz */ + while (reference_freq_khz / (div_factor + 1) >= 5000) + div_factor++; + if (div_factor > 31) + div_factor = 31; + + mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor, + reference_freq_khz); + + output_freq_kbps = reference_freq_khz * mul_factor / div_factor; + + if (output_freq_kbps >= 501000) + fr = 3; + else if (output_freq_kbps >= 251000) + fr = 2; + else if (output_freq_kbps >= 126000) + fr = 1; + + return (fr << 14) | (div_factor << 8) | mul_factor; +} + +static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz) +{ + u32 mul_factor = pll_config & 0xFF; + u32 div_factor = (pll_config >> 8) & 0x1F; + if (mul_factor == 0) + mul_factor = 1; + if (div_factor == 0) + div_factor = 1; + return reference_freq_khz * mul_factor / div_factor; +} + +static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg, + const struct ctfb_res_modes *mode) +{ + u32 val; + + /* RGB Interface Control Register 1 */ + write_hw_register(cfg, SSD2828_VICR1, (mode->vsync_len << 8) | + (mode->hsync_len)); + + /* RGB Interface Control Register 2 */ + u32 vbp = mode->vsync_len + mode->upper_margin; + u32 hbp = mode->hsync_len + mode->left_margin; + write_hw_register(cfg, SSD2828_VICR2, (vbp << 8) | hbp); + + /* RGB Interface Control Register 3 */ + write_hw_register(cfg, SSD2828_VICR3, (mode->lower_margin << 8) | + (mode->right_margin)); + + /* RGB Interface Control Register 4 */ + write_hw_register(cfg, SSD2828_VICR4, mode->xres); + + /* RGB Interface Control Register 5 */ + write_hw_register(cfg, SSD2828_VICR5, mode->yres); + + /* RGB Interface Control Register 6 */ + val = SSD2828_VIDEO_MODE_BURST; + switch (cfg->ssd2828_color_depth) { + case 16: + val |= SSD2828_VIDEO_PIXEL_FORMAT_16BPP; + break; + case 18: + val |= cfg->mipi_dsi_loosely_packed_pixel_format ? + SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED : + SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED; + break; + case 24: + val |= SSD2828_VIDEO_PIXEL_FORMAT_24BPP; + break; + default: + printf("SSD2828: unsupported color depth\n"); + return 1; + } + write_hw_register(cfg, SSD2828_VICR6, val); + + /* Lane Configuration Register */ + write_hw_register(cfg, SSD2828_LCFR, + cfg->mipi_dsi_number_of_data_lanes - 1); + + return 0; +} + +int ssd2828_init(const struct ssd2828_config *cfg, + const struct ctfb_res_modes *mode) +{ + u32 lp_div, pll_freq_kbps, pll_config; + /* The LP clock speed is limited by 10MHz */ + const u32 mipi_dsi_low_power_clk_khz = 10000; + /* + * This is just the reset default value of CFGR register (0x301). + * Because we are not always able to read back from SPI, have + * it initialized here. + */ + u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */ + SSD2828_CFGR_ECD | /* Disable ECC and CRC */ + SSD2828_CFGR_HS; /* Data lanes are in HS mode */ + + /* Initialize the pins */ + if (ssd2828_enable_gpio(cfg) != 0) + return 1; + + /* Reset the chip */ + ssd2828_reset(cfg); + + /* + * If there is a pin to read data back from SPI, then we are lucky. Try + * to check if SPI is configured correctly and SSD2828 is actually able + * to talk back. + */ + if (cfg->sdo_pin != -1) { + if (read_hw_register(cfg, SSD2828_DIR) != 0x2828 || + read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) { + printf("SSD2828: SPI communication failed.\n"); + ssd2828_free_gpio(cfg); + return 1; + } + } + + /* + * Setup the parallel LCD timings in the appropriate registers. + */ + if (ssd2828_configure_video_interface(cfg, mode) != 0) { + ssd2828_free_gpio(cfg); + return 1; + } + + /* Configuration Register */ + cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */ + cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */ + cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */ + write_hw_register(cfg, SSD2828_CFGR, cfgr_reg); + + /* PLL Configuration Register */ + pll_config = construct_pll_config( + cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000, + cfg->ssd2828_tx_clk_khz); + write_hw_register(cfg, SSD2828_PLCR, pll_config); + + pll_freq_kbps = decode_pll_config(pll_config, cfg->ssd2828_tx_clk_khz); + lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8); + + /* VC Control Register */ + write_hw_register(cfg, SSD2828_VCR, 0); + + /* Clock Control Register */ + write_hw_register(cfg, SSD2828_CCR, SSD2828_LP_CLOCK_DIVIDER(lp_div)); + + /* PLL Control Register */ + write_hw_register(cfg, SSD2828_PCR, 1); /* Enable PLL */ + + /* Wait for PLL lock */ + udelay(500); + + send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE); + mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms); + + send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON); + mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms); + + cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */ + cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */ + write_hw_register(cfg, SSD2828_CFGR, cfgr_reg); + + return 0; +} diff --git a/drivers/video/ssd2828.h b/drivers/video/ssd2828.h new file mode 100644 index 0000000..14b96c5 --- /dev/null +++ b/drivers/video/ssd2828.h @@ -0,0 +1,123 @@ +/* + * (C) 2015 Siarhei Siamashka siarhei.siamashka@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Support for the SSD2828 bridge chip, which can take pixel data coming + * from a parallel LCD interface and translate it on the flight into MIPI DSI + * interface for driving a MIPI compatible TFT display. + * + * Implemented as a utility function. To be used from display drivers, which are + * responsible for driving parallel LCD hardware in front of the video pipeline. + */ + +#ifndef _SSD2828_H +#define _SSD2828_H + +struct ctfb_res_modes; + +struct ssd2828_config { + /*********************************************************************/ + /* SSD2828 configuration */ + /*********************************************************************/ + + /* + * The pins, which are used for SPI communication. This is only used + * for configuring SSD2828, so the performance is irrelevant (only + * around a hundred of bytes is moved). Also these can be any arbitrary + * GPIO pins (not necessarily the pins having hardware SPI function). + * Moreover, the 'sdo' pin may be even not wired up in some devices. + * + * These configuration variables need to be set as pin numbers for + * the standard u-boot GPIO interface (gpio_get_value/gpio_set_value + * functions). Note that -1 value can be used for the pins, which are + * not really wired up. + */ + int csx_pin; + int sck_pin; + int sdi_pin; + int sdo_pin; + /* SSD2828 reset pin (shared with LCD panel reset) */ + int reset_pin; + + /* + * The SSD2828 has its own dedicated clock source 'tx_clk' (connected + * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for + * clocking SPI after reset. The exact clock speed is not strictly, + * defined, but the datasheet says that it must be somewhere in the + * 8MHz - 30MHz range (see "TX_CLK Timing" section). It is used as + * a reference clock for PLL and must be set correctly. + */ + int ssd2828_tx_clk_khz; + + /* + * This is not a property of the used LCD panel, but more like a + * property of the SSD2828 wiring. See the "SSD2828QN4 RGB data + * arrangement" table in the datasheet. The SSD2828 pins are arranged + * in such a way that 18bpp and 24bpp configurations are completely + * incompatible with each other. + * + * Depending on the color depth, this must be set to 16, 18 or 24. + */ + int ssd2828_color_depth; + + /*********************************************************************/ + /* LCD panel configuration */ + /*********************************************************************/ + + /* + * The number of lanes in the MIPI DSI interface. May vary from 1 to 4. + * + * This information can be found in the LCD panel datasheet. + */ + int mipi_dsi_number_of_data_lanes; + + /* + * Data transfer bit rate per lane. Please note that it is expected + * to be higher than the pixel clock rate of the used video mode when + * multiplied by the number of lanes. This is perfectly normal because + * MIPI DSI handles data transfers in periodic bursts, and uses the + * idle time between bursts for sending configuration information and + * commands. Or just for saving power. + * + * The necessary Mbps/lane information can be found in the LCD panel + * datasheet. Note that the transfer rate can't be always set precisely + * and it may be rounded *up* (introducing no more than 10Mbps error). + */ + int mipi_dsi_bitrate_per_data_lane_mbps; + + /* + * Setting this to 1 enforces packing of 18bpp pixel data in 24bpp + * envelope when sending it over the MIPI DSI link. + * + * If unsure, set to 0. + */ + int mipi_dsi_loosely_packed_pixel_format; + + /* + * According to the "Example for system sleep in and out" section in + * the SSD2828 datasheet, some LCD panel specific delays are necessary + * after MIPI DCS commands EXIT_SLEEP_MODE and SET_DISPLAY_ON. + * + * For example, Allwinner uses 100 milliseconds delay after + * EXIT_SLEEP_MODE and 200 milliseconds delay after SET_DISPLAY_ON. + */ + int mipi_dsi_delay_after_exit_sleep_mode_ms; + int mipi_dsi_delay_after_set_display_on_ms; +}; + +/* + * Initialize the SSD2828 chip. It needs the 'ssd2828_config' structure + * and also the video mode timings. + * + * The right place to insert this function call is after the parallel LCD + * interface is initialized and before turning on the backlight. This is + * advised in the "Example for system sleep in and out" section of the + * SSD2828 datasheet. + */ +int ssd2828_init(const struct ssd2828_config *cfg, + const struct ctfb_res_modes *mode); + +#endif

Expose the necessary configuration parameters in Kconfig. Add SSD2828 initialization between enabling the parallel LCD interface and turning on the backlight.

Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- board/sunxi/Kconfig | 60 +++++++++++++++++++++++++++++++++++++++++ drivers/video/sunxi_display.c | 3 +++ drivers/video/sunxi_lcd_panel.c | 38 ++++++++++++++++++++++++++ drivers/video/sunxi_lcd_panel.h | 3 +++ 4 files changed, 104 insertions(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index adee5ed..92dbce7 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -345,6 +345,60 @@ config VIDEO_LCD_BL_PWM Set the backlight pwm pin for the LCD panel. This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.

+config VIDEO_LCD_SPI_CS + string "SPI CS pin for LCD related config job" + depends on VIDEO_LCD_SSD2828 + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SPI_SCLK + string "SPI SCLK pin for LCD related config job" + depends on VIDEO_LCD_SSD2828 + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SPI_MOSI + string "SPI MOSI pin for LCD related config job" + depends on VIDEO_LCD_SSD2828 + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SPI_MISO + string "SPI MISO pin for LCD related config job (optional)" + depends on VIDEO_LCD_SSD2828 + default "" + ---help--- + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. If wired up, this pin may provide additional + useful functionality. Such as bi-directional communication with the + hardware and LCD panel id retrieval (if the panel can report it). The + option takes a string in the format understood by sunxi_name_to_gpio, + e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SSD2828_RESET + string "RESET pin of SSD2828" + depends on VIDEO_LCD_SSD2828 + default "" + ---help--- + The reset pin of SSD2828 chip. This takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_SSD2828 + bool + select VIDEO_LCD_IF_PARALLEL

# Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig @@ -373,6 +427,12 @@ config VIDEO_LCD_PANEL_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LCD panel" select VIDEO_LCD_IF_LVDS

+config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 + bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" + select VIDEO_LCD_SSD2828 + ---help--- + 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 + endchoice

diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index c3fc732..f11b241 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -850,6 +850,9 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, sunxi_lcdc_tcon0_mode_set(mode); sunxi_composer_enable(); sunxi_lcdc_enable(); +#ifdef CONFIG_VIDEO_LCD_SSD2828 + sunxi_ssd2828_init(mode); +#endif sunxi_lcdc_backlight_enable(); break; case sunxi_monitor_vga: diff --git a/drivers/video/sunxi_lcd_panel.c b/drivers/video/sunxi_lcd_panel.c index 9ebaff2..cdde639 100644 --- a/drivers/video/sunxi_lcd_panel.c +++ b/drivers/video/sunxi_lcd_panel.c @@ -11,6 +11,8 @@ #include <asm/arch/gpio.h> #include <asm/gpio.h> #include <asm/io.h> +#include "sunxi_lcd_panel.h" +#include "ssd2828.h"

#ifdef CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM

@@ -66,3 +68,39 @@ void sunxi_lcd_panel_hitachi_tx18d42vm_init(void) }

#endif + +#ifdef CONFIG_VIDEO_LCD_SSD2828 + +int sunxi_ssd2828_init(const struct ctfb_res_modes *mode) +{ + struct ssd2828_config cfg = { + .csx_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS), + .sck_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK), + .sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI), + .sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO), + .reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET), + .ssd2828_tx_clk_khz = 27000, + .ssd2828_color_depth = 24, +#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 + .mipi_dsi_number_of_data_lanes = 4, + .mipi_dsi_bitrate_per_data_lane_mbps = 513, + .mipi_dsi_delay_after_exit_sleep_mode_ms = 100, + .mipi_dsi_delay_after_set_display_on_ms = 200 +#else +#error MIPI LCD panel needs configuration parameters +#endif + }; + + if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) { + printf("SSD2828: SPI pins are not properly configured\n"); + return 1; + } + if (cfg.reset_pin == -1) { + printf("SSD2828: Reset pin is not properly configured\n"); + return 1; + } + + return ssd2828_init(&cfg, mode); +} + +#endif diff --git a/drivers/video/sunxi_lcd_panel.h b/drivers/video/sunxi_lcd_panel.h index 1fb9f1e..8b1bc14 100644 --- a/drivers/video/sunxi_lcd_panel.h +++ b/drivers/video/sunxi_lcd_panel.h @@ -6,4 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */

+struct ctfb_res_modes; + void sunxi_lcd_panel_hitachi_tx18d42vm_init(void); +int sunxi_ssd2828_init(const struct ctfb_res_modes *mode);

The MSI Primo81 tablet has B079XAN01/LP079X01 7.85" 768x1024 IPS MIPI display, connected to the parallel LCD interface via SSD2828 bridge chip. The panel has 18-bit color depth and needs dithering, in spite of having RGB data delivered from A31s to SSD2828 using 24-bit arrangement.

Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- configs/MSI_Primo81_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index b4b0f6d..1be6016 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -1,6 +1,15 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="" CONFIG_FDTFILE="sun6i-a31s-primo81.dtb" +CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0" +CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y +CONFIG_VIDEO_LCD_SSD2828_RESET="PA26" +CONFIG_VIDEO_LCD_SPI_CS="PH9" +CONFIG_VIDEO_LCD_SPI_SCLK="PH10" +CONFIG_VIDEO_LCD_SPI_MOSI="PH11" +CONFIG_VIDEO_LCD_SPI_MISO="PH12" +CONFIG_VIDEO_LCD_BL_EN="PA25" +CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_USB_KEYBOARD=n +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y

Instead of using the internal 'tx_clk' clock source, it is also possible to use the pixel clock signal from the parallel LCD interface ('pclk') as the reference clock for PLL.

The 'tx_clk' clock speed may be different on different boards/devices (the allowed range is 8MHz - 30MHz). Which is not very convenient, especially considering the need to know the exact 'tx_clk' clock speed. Which may be difficult to identify without having device schematics and/or accurate documentation/sources every time.

Using 'pclk' is free from all these problems.

Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- drivers/video/ssd2828.c | 20 +++++++++++++++++--- drivers/video/ssd2828.h | 11 ++++++++--- 2 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c index 566ec19..702afd9 100644 --- a/drivers/video/ssd2828.c +++ b/drivers/video/ssd2828.c @@ -339,7 +339,7 @@ static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg, int ssd2828_init(const struct ssd2828_config *cfg, const struct ctfb_res_modes *mode) { - u32 lp_div, pll_freq_kbps, pll_config; + u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config; /* The LP clock speed is limited by 10MHz */ const u32 mipi_dsi_low_power_clk_khz = 10000; /* @@ -373,6 +373,20 @@ int ssd2828_init(const struct ssd2828_config *cfg, }

/* + * Pick the reference clock for PLL. If we know the exact 'tx_clk' + * clock speed, then everything is good. If not, then we can fallback + * to 'pclk' (pixel clock from the parallel LCD interface). In the + * case of using this fallback, it is necessary to have parallel LCD + * already initialized and running at this point. + */ + reference_freq_khz = cfg->ssd2828_tx_clk_khz; + if (reference_freq_khz == 0) { + reference_freq_khz = mode->pixclock_khz; + /* Use 'pclk' as the reference clock for PLL */ + cfgr_reg |= SSD2828_CFGR_CSS; + } + + /* * Setup the parallel LCD timings in the appropriate registers. */ if (ssd2828_configure_video_interface(cfg, mode) != 0) { @@ -389,10 +403,10 @@ int ssd2828_init(const struct ssd2828_config *cfg, /* PLL Configuration Register */ pll_config = construct_pll_config( cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000, - cfg->ssd2828_tx_clk_khz); + reference_freq_khz); write_hw_register(cfg, SSD2828_PLCR, pll_config);

- pll_freq_kbps = decode_pll_config(pll_config, cfg->ssd2828_tx_clk_khz); + pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz); lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8);

/* VC Control Register */ diff --git a/drivers/video/ssd2828.h b/drivers/video/ssd2828.h index 14b96c5..1af6fa4 100644 --- a/drivers/video/ssd2828.h +++ b/drivers/video/ssd2828.h @@ -47,8 +47,12 @@ struct ssd2828_config { * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for * clocking SPI after reset. The exact clock speed is not strictly, * defined, but the datasheet says that it must be somewhere in the - * 8MHz - 30MHz range (see "TX_CLK Timing" section). It is used as - * a reference clock for PLL and must be set correctly. + * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also + * used as a reference clock for PLL. If the exact clock frequency + * is known, then it can be specified here. If it is unknown, or the + * information is not trustworthy, then it can be set to 0. + * + * If unsure, set to 0. */ int ssd2828_tx_clk_khz;

@@ -115,7 +119,8 @@ struct ssd2828_config { * The right place to insert this function call is after the parallel LCD * interface is initialized and before turning on the backlight. This is * advised in the "Example for system sleep in and out" section of the - * SSD2828 datasheet. + * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source + * for PLL, which means that the input signal must be already there. */ int ssd2828_init(const struct ssd2828_config *cfg, const struct ctfb_res_modes *mode);

So that we don't need to keep it as a hardcoded magic number in the code or the hassle exposing it as a Kconfig option.

Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- drivers/video/sunxi_lcd_panel.c | 1 - 1 file changed, 1 deletion(-)

diff --git a/drivers/video/sunxi_lcd_panel.c b/drivers/video/sunxi_lcd_panel.c index cdde639..ebc0ca5 100644 --- a/drivers/video/sunxi_lcd_panel.c +++ b/drivers/video/sunxi_lcd_panel.c @@ -79,7 +79,6 @@ int sunxi_ssd2828_init(const struct ctfb_res_modes *mode) .sdi_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI), .sdo_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO), .reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET), - .ssd2828_tx_clk_khz = 27000, .ssd2828_color_depth = 24, #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 .mipi_dsi_number_of_data_lanes = 4,

Or at least try to do this. With the possibility of bi-directional communication, it seems natural to expect that MIPI displays should be able to handle automatic configuration for the screen resolution and timings nicely. But the reality is not so pretty.

It appears that the manufacturers of MIPI LCD panels are not very disciplined and do not follow any kind of standard guidelines when it comes to providing the panel identification information. MIPI DSI even has two alternative standard DCS commands for potentially reading the vendor/panel id: MIPI_DCS_GET_DISPLAY_ID and MIPI_DCS_READ_DDB_START. But these commands do not seem to be widely implemented in real hardware. Moreover, the vendors seem to sometimes invent their own custom new commands, while ignoring the standard ones.

This particular patch just probes both of the standard DCS commands and also a few non-standard ones. With the hope to actually extract anything unique and/or meaningful from the LCD panel. This information is then printed to the u-boot console.

We don't know what the future brings. Maybe the manufacturers are going to start acting responsibly some day. And will implement proper panel identification.

Regarding what we have right now. The information retrieval DCS commands still work if reducing the clock speed to the very minimum and enabling only one lane on my MSI Primo81 tablet. Potentially it means that one could perhaps swap two different MIPI LCD panels (if they have a compatible connector) and still have the software handling this fine by doing runtime selection of the right settings (based on checking the panel id).

Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- drivers/video/ssd2828.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+)

diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c index 702afd9..cfebedd 100644 --- a/drivers/video/ssd2828.c +++ b/drivers/video/ssd2828.c @@ -98,6 +98,9 @@ #define SSD2828_CFGR_LPE (1 << 10) #define SSD2828_CFGR_TXD (1 << 11)

+#define SSD2828_ISR_READ_DATA_READY (1 << 0) +#define SSD2828_ISR_BTA_RESPONSE (1 << 2) + #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2) #define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2) #define SSD2828_VIDEO_MODE_BURST (2 << 2) @@ -167,6 +170,30 @@ static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val); }

+static int await_completion(const struct ssd2828_config *cfg, + u8 reg, u32 mask, u32 val) +{ + unsigned long tmo = timer_get_us() + 100000; + + while ((read_hw_register(cfg, reg) & mask) != val) { + if (timer_get_us() > tmo) + return 1; + } + return 0; +} + +static int await_bits_set(const struct ssd2828_config *cfg, + u8 reg, u32 val) +{ + return await_completion(cfg, reg, val, val); +} + +static int await_bits_clear(const struct ssd2828_config *cfg, + u8 reg, u32 val) +{ + return await_completion(cfg, reg, val, 0); +} + /* * Send MIPI command to the LCD panel (cmdnum < 0xB0) */ @@ -179,6 +206,79 @@ static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) }

/* + * Sends a MIPI DCS command to retrieve information from the LCD panel. + */ +static int send_mipi_dcs_read_command(const struct ssd2828_config *cfg, + u8 cmdnum, + u8 *result_buf, + int bufsize) +{ + int size, i, result = 0; + /* Save CFGR register */ + u32 old_cfgr = read_hw_register(cfg, SSD2828_CFGR); + + /* Set the read enable bit */ + write_hw_register(cfg, SSD2828_CFGR, old_cfgr | SSD2828_CFGR_REN); + /* Clear buffers and bring the state machine to its initial state */ + write_hw_register(cfg, SSD2828_OCR, 1); + if (await_bits_clear(cfg, SSD2828_OCR, 1) != 0) + goto err; + /* Clear the RW1C bits in the ISR register */ + write_hw_register(cfg, SSD2828_ISR, read_hw_register(cfg, SSD2828_ISR)); + + /* Set the payload size (only the DCS command itself) */ + write_hw_register(cfg, SSD2828_PSCR1, 1); + /* Set maximum return size */ + write_hw_register(cfg, SSD2828_MRSR, bufsize); + /* Write the command */ + write_hw_register(cfg, SSD2828_PDR, cmdnum); + + /* Wait for the response */ + if (await_bits_set(cfg, SSD2828_ISR, SSD2828_ISR_BTA_RESPONSE) != 0) + goto err; /* Timeout */ + + /* Check if there is anything in the read buffer */ + if (!(read_hw_register(cfg, SSD2828_ISR) & SSD2828_ISR_READ_DATA_READY)) + goto err; /* There is no data to read */ + + /* The size of the response packet */ + size = read_hw_register(cfg, SSD2828_RDCR); + if (size > bufsize) { + debug("SSD2828: Suspicious packet size.\n"); + size = bufsize; + } + result = size; + + /* + * This is somewhat special and does not seem to be well documented: + * 1) In order to properly read the data, all the buffer must be read + * in one go without any interruptions. For example, using individual + * reads done by the "read_hw_register" function only result in + * repeatedly getting all the same first 16-bits of data without + * advancing. + * 2) In order to empty the buffer, it is necessary to read as much + * data as was initially configured in the MRSR register. The real + * size of the packet in the RDCR register just indicates how much + * of it is actually valid. + */ + soft_spi_xfer_24bit_3wire(cfg, 0x700000 | SSD2828_RR); + for (i = 0; i < (bufsize + 1) / 2; i++) { + u16 data = soft_spi_xfer_24bit_3wire(cfg, 0x730000); + if (size-- > 0) + *result_buf++ = data & 0xFF; + if (size-- > 0) + *result_buf++ = (data >> 8) & 0xFF; + } + + if (read_hw_register(cfg, SSD2828_ISR) & SSD2828_ISR_READ_DATA_READY) + debug("SSD2828: There is still some bogus unread data.\n"); +err: + /* Restore CFGR register */ + write_hw_register(cfg, SSD2828_CFGR, old_cfgr); + return result; +} + +/* * Reset SSD2828 */ static void ssd2828_reset(const struct ssd2828_config *cfg) @@ -336,6 +436,42 @@ static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg, return 0; }

+static void ssd2828_report_dcs_read_result(const struct ssd2828_config *cfg, + u8 cmd) +{ + u8 buf[64]; + int size, i; + size = send_mipi_dcs_read_command(cfg, cmd, buf, sizeof(buf)); + if (size > 0) { + printf("DCS command 0x%02X returned %2d bytes:", cmd, size); + for (i = 0; i < size; i++) + printf(" %02X", buf[i]); + printf("\n"); + } +} + +/* + * Try to use different DCS commands to identify the panel id and + * report it in the log. + */ +static void ssd2828_report_panel_id(const struct ssd2828_config *cfg) +{ + printf("Trying standard MIPI DSI commands to identify LCD panel:\n"); + + ssd2828_report_dcs_read_result(cfg, MIPI_DCS_GET_DISPLAY_ID); + ssd2828_report_dcs_read_result(cfg, MIPI_DCS_READ_DDB_START); + + printf("Trying nonstandard MIPI DSI commands to identify LCD panel:\n"); + + /* Used by some LG panels (for example, LH350WS1-SD02.pdf) */ + ssd2828_report_dcs_read_result(cfg, 0xB1); + + /* Used by many LCD panels (for example, DA8620.pdf) */ + ssd2828_report_dcs_read_result(cfg, 0xDA); + ssd2828_report_dcs_read_result(cfg, 0xDB); + ssd2828_report_dcs_read_result(cfg, 0xDC); +} + int ssd2828_init(const struct ssd2828_config *cfg, const struct ctfb_res_modes *mode) { @@ -424,6 +560,10 @@ int ssd2828_init(const struct ssd2828_config *cfg, send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE); mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms);

+ /* If it is possible to read back, then try to retrieve the panel id */ + if (cfg->sdo_pin != -1) + ssd2828_report_panel_id(cfg); + send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON); mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms);