[U-Boot] [PATCH 00/28] socfpga: sdram.c cleanups
This entire series focuses solely on cleaning up the drivers/ddr/altera/sdram.c file. After this series, this one file is totally checkpatch clean and does not pull in any weird qts-generated macros ; all that is wrapped in the board file.
This micro-series applies on top of my previous mega-series [1]. This series is available via git at [2].
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg178890.html [2] http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/06-d...
Marek Vasut (28): ddr: altera: sdram: Switch to generic_hweight32() ddr: altera: sdram: Clean up compute_errata_rows() part 1 ddr: altera: sdram: Clean up compute_errata_rows() part 2 ddr: altera: sdram: Clean up set_sdr_ctrlcfg() ddr: altera: sdram: Clean up set_sdr_dram_timing*() ddr: altera: sdram: Clean up set_sdr_addr_rw() ddr: altera: sdram: Clean up set_sdr_static_cfg() ddr: altera: sdram: Clean up set_sdr_fifo_cfg() ddr: altera: sdram: Clean up set_sdr_mp_weight() ddr: altera: sdram: Clean up set_sdr_mp_pacing() ddr: altera: sdram: Clean up set_sdr_mp_threshold() ddr: altera: sdram: Introduce socfpga_sdram_config() structure ddr: altera: sdram: Clean up sdram_mmr_init_full() part 1 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 2 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 3 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 5 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 6 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 7 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8 ddr: altera: sdram: Introduce socfpga_sdram_get_config() ddr: altera: sdram: Clean up sdram_calculate_size() part 1 ddr: altera: sdram: Clean up sdram_calculate_size() part 2 ddr: altera: sdram: Clean up sdram_write_verify() ddr: altera: sdram: Add missing kerneldoc ddr: altera: sdram: Minor cleanup in sdram_set_rule() ddr: altera: sdram: Minor cleanup in sdram_get_rule() ddr: altera: sdram: Make sdram_start and sdram_end into u32
arch/arm/mach-socfpga/include/mach/sdram.h | 44 +- board/altera/socfpga/Makefile | 3 +- board/altera/socfpga/wrap_sdram_config.c | 185 ++++++++ drivers/ddr/altera/sdram.c | 724 +++++++++-------------------- 4 files changed, 451 insertions(+), 505 deletions(-) create mode 100644 board/altera/socfpga/wrap_sdram_config.c
Use generic function instead of CPU-specific one.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 474df42..9e6acfe 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -64,7 +64,7 @@ static int compute_errata_rows(unsigned long long memsize, int cs, int width, * Need to see if result is ordinal power of 2 before * attempting log2 of result. */ - bits = hweight32(newrows); + bits = generic_hweight32(newrows);
debug("rows workaround - bits %d\n", bits);
Clean up weird parenthesis and odd type casts from the function. Fix comment style.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 9e6acfe..c60820c 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -54,13 +54,14 @@ static int compute_errata_rows(unsigned long long memsize, int cs, int width, debug("workaround rows - banks %d\n", banks); debug("workaround rows - cols %d\n", cols);
- newrows = lldiv(memsize, (cs * (width / 8))); + newrows = lldiv(memsize, cs * (width / 8)); debug("rows workaround - term1 %lld\n", newrows);
- newrows = lldiv(newrows, ((1 << banks) * (1 << cols))); + newrows = lldiv(newrows, (1 << banks) * (1 << cols)); debug("rows workaround - term2 %lld\n", newrows);
- /* Compute the hamming weight - same as number of bits set. + /* + * Compute the hamming weight - same as number of bits set. * Need to see if result is ordinal power of 2 before * attempting log2 of result. */ @@ -78,13 +79,12 @@ static int compute_errata_rows(unsigned long long memsize, int cs, int width, return rows; }
- inewrowslog2 = __ilog2((unsigned int)newrows); + inewrowslog2 = __ilog2(newrows);
- debug("rows workaround - ilog2 %d, %d\n", inewrowslog2, - (int)newrows); + debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
if (inewrowslog2 == -1) { - printf("SDRAM workaround failed, newrows %d\n", (int)newrows); + printf("SDRAM workaround failed, newrows %lld\n", newrows); return rows; }
Remove all parameters of this function, since they are only constants passed in from another function, so make them local. Also, rename the function to get_errata_rows() as this is closer to what it does.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index c60820c..ca68528 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -17,9 +17,6 @@ */ #include "../../../board/altera/socfpga/qts/sdram_config.h"
-/* define constant for 4G memory - used for SDRAM errata workaround */ -#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) - DECLARE_GLOBAL_DATA_PTR;
struct sdram_prot_rule { @@ -40,12 +37,26 @@ static struct socfpga_system_manager *sysmgr_regs = static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
-static int compute_errata_rows(unsigned long long memsize, int cs, int width, - int rows, int banks, int cols) +/** + * get_errata_rows() - Up the number of DRAM rows to cover entire address space + * + * SDRAM Failure happens when accessing non-existent memory. Artificially + * increase the number of rows so that the memory controller thinks it has + * 4GB of RAM. This function returns such amount of rows. + */ +static int get_errata_rows(void) { + /* Define constant for 4G memory - used for SDRAM errata workaround */ +#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) + const unsigned long long memsize = MEMSIZE_4G; + const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; + const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; + const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS; + const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS; + const unsigned int width = 8; + unsigned long long newrows; - int inewrowslog2; - int bits; + int bits, inewrowslog2;
debug("workaround rows - memsize %lld\n", memsize); debug("workaround rows - cs %d\n", cs); @@ -410,12 +421,7 @@ static void set_sdr_dram_lowpwr_timing(void)
static void set_sdr_addr_rw(void) { - int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; - int width = 8; - int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; - int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS; - int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS; - unsigned long long workaround_memsize = MEMSIZE_4G; + int rows;
debug("Configuring DRAMADDRW\n"); clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK, @@ -426,8 +432,7 @@ static void set_sdr_addr_rw(void) * Update Preloader to artificially increase the number of rows so * that the memory thinks it has 4GB of RAM. */ - rows = compute_errata_rows(workaround_memsize, cs, width, rows, banks, - cols); + rows = get_errata_rows();
clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK, rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function. The big plan here is to remove all the CONFIG_HPS_SDR_ macros, hide them in QTS compatibility layer in board implementation and pass only a small structure into the driver.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 62 ++++++++++++++++++---------------------------- 1 file changed, 24 insertions(+), 38 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index ca68528..0bfd564 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -254,18 +254,29 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
static void set_sdr_ctrlcfg(void) { - int addrorder; + u32 addrorder; + u32 ctrl_cfg = + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
debug("\nConfiguring CTRLCFG\n"); - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << - SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB); - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << - SDR_CTRLGRP_CTRLCFG_MEMBL_LSB); -
- /* SDRAM Failure When Accessing Non-Existent Memory + /* + * SDRAM Failure When Accessing Non-Existent Memory * Set the addrorder field of the SDRAM control register * based on the CSBITs setting. */ @@ -273,46 +284,21 @@ static void set_sdr_ctrlcfg(void) case 1: addrorder = 0; /* chip, row, bank, column */ if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0) - debug("INFO: Changing address order to 0 (chip, row, \ - bank, column)\n"); + debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); break; case 2: addrorder = 2; /* row, chip, bank, column */ if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2) - debug("INFO: Changing address order to 2 (row, chip, \ - bank, column)\n"); + debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); break; default: addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER; break; }
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK, - addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << - SDR_CTRLGRP_CTRLCFG_ECCEN_LSB); + ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << - SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << - SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << - SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << - SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB); - - clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << - SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB); + writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); }
static void set_sdr_dram_timing1(void)
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function. Merge set_sdr_dram_timing{1,2,3,4,lowpwr}() into single function set_sdr_dram_timing() , since there's no point in keeping all this stuff separate anymore.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 146 ++++++++++++++++----------------------------- 1 file changed, 53 insertions(+), 93 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 0bfd564..f4f3545 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -301,108 +301,72 @@ static void set_sdr_ctrlcfg(void) writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); }
-static void set_sdr_dram_timing1(void) +static void set_sdr_dram_timing(void) { - debug("Configuring DRAMTIMING1\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << - SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB); + const u32 dram_timing1 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << - SDR_CTRLGRP_DRAMTIMING1_TAL_LSB); + const u32 dram_timing2 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << - SDR_CTRLGRP_DRAMTIMING1_TCL_LSB); + const u32 dram_timing3 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << - SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB); + const u32 dram_timing4 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << - SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB); + const u32 lowpwr_timing = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << - SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB); -} + debug("Configuring DRAMTIMING1\n"); + writel(dram_timing1, &sdr_ctrl->dram_timing1);
-static void set_sdr_dram_timing2(void) -{ debug("Configuring DRAMTIMING2\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << - SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << - SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << - SDR_CTRLGRP_DRAMTIMING2_TRP_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << - SDR_CTRLGRP_DRAMTIMING2_TWR_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << - SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB); -} + writel(dram_timing2, &sdr_ctrl->dram_timing2);
-static void set_sdr_dram_timing3(void) -{ debug("Configuring DRAMTIMING3\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << - SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << - SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << - SDR_CTRLGRP_DRAMTIMING3_TRC_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << - SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << - SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB); -} + writel(dram_timing3, &sdr_ctrl->dram_timing3);
-static void set_sdr_dram_timing4(void) -{ debug("Configuring DRAMTIMING4\n"); - clrsetbits_le32(&sdr_ctrl->dram_timing4, - SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << - SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_timing4, - SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << - SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB); -} + writel(dram_timing4, &sdr_ctrl->dram_timing4);
-static void set_sdr_dram_lowpwr_timing(void) -{ debug("Configuring LOWPWRTIMING\n"); - clrsetbits_le32(&sdr_ctrl->lowpwr_timing, - SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK, - CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << - SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB); - - clrsetbits_le32(&sdr_ctrl->lowpwr_timing, - SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK, - CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << - SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB); + writel(lowpwr_timing, &sdr_ctrl->lowpwr_timing); }
static void set_sdr_addr_rw(void) @@ -556,11 +520,7 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) &sysmgr_regs->iswgrp_handoff[4]); #endif set_sdr_ctrlcfg(); - set_sdr_dram_timing1(); - set_sdr_dram_timing2(); - set_sdr_dram_timing3(); - set_sdr_dram_timing4(); - set_sdr_dram_lowpwr_timing(); + set_sdr_dram_timing(); set_sdr_addr_rw();
debug("Configuring DRAMIFWIDTH\n");
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index f4f3545..143f41b 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -371,34 +371,24 @@ static void set_sdr_dram_timing(void)
static void set_sdr_addr_rw(void) { - int rows; - - debug("Configuring DRAMADDRW\n"); - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB); /* * SDRAM Failure When Accessing Non-Existent Memory - * Update Preloader to artificially increase the number of rows so - * that the memory thinks it has 4GB of RAM. - */ - rows = get_errata_rows(); - - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK, - rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB); - /* SDRAM Failure When Accessing Non-Existent Memory * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to * log2(number of chip select bits). Since there's only * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, * which is the same as "chip selects" - 1. */ - clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK, - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << + const int rows = get_errata_rows(); + const u32 dram_addrw = + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | + (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB); + debug("Configuring DRAMADDRW\n"); + writel(dram_addrw, &sdr_ctrl->dram_addrw); }
static void set_sdr_static_cfg(void)
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 143f41b..d8d04f4 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -393,15 +393,14 @@ static void set_sdr_addr_rw(void)
static void set_sdr_static_cfg(void) { - debug("Configuring STATICCFG\n"); - clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK, - CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << - SDR_CTRLGRP_STATICCFG_MEMBL_LSB); - - clrsetbits_le32(&sdr_ctrl->static_cfg, - SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK, - CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << + const u32 static_cfg = + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB); + + debug("Configuring STATICCFG\n"); + writel(static_cfg, &sdr_ctrl->static_cfg); }
static void set_sdr_fifo_cfg(void)
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index d8d04f4..8db8dde 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -405,14 +405,14 @@ static void set_sdr_static_cfg(void)
static void set_sdr_fifo_cfg(void) { - debug("Configuring FIFOCFG\n"); - clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK, - CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << - SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB); - - clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK, - CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << + const u32 fifo_cfg = + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB); + + debug("Configuring FIFOCFG\n"); + writel(fifo_cfg, &sdr_ctrl->fifo_cfg); }
static void set_sdr_mp_weight(void)
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 8db8dde..f324805 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -417,31 +417,26 @@ static void set_sdr_fifo_cfg(void)
static void set_sdr_mp_weight(void) { - debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); - clrsetbits_le32(&sdr_ctrl->mp_weight0, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << + const u32 mp_weight0 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight1, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight1, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << + const u32 mp_weight1 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight2, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << + const u32 mp_weight2 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_weight3, - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << + const u32 mp_weight3 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB); + + debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); + writel(mp_weight0, &sdr_ctrl->mp_weight0); + writel(mp_weight1, &sdr_ctrl->mp_weight1); + writel(mp_weight2, &sdr_ctrl->mp_weight2); + writel(mp_weight3, &sdr_ctrl->mp_weight3); }
static void set_sdr_mp_pacing(void)
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index f324805..e41815b 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -441,31 +441,26 @@ static void set_sdr_mp_weight(void)
static void set_sdr_mp_pacing(void) { - debug("Configuring MPPACING_MPPACING_0\n"); - clrsetbits_le32(&sdr_ctrl->mp_pacing0, - SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << + const u32 mp_pacing0 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_pacing1, - SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << - SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_pacing1, - SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << + const u32 mp_pacing1 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_pacing2, - SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << + const u32 mp_pacing2 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_pacing3, - SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << + const u32 mp_pacing3 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB); + + debug("Configuring MPPACING_MPPACING_0\n"); + writel(mp_pacing0, &sdr_ctrl->mp_pacing0); + writel(mp_pacing1, &sdr_ctrl->mp_pacing1); + writel(mp_pacing2, &sdr_ctrl->mp_pacing2); + writel(mp_pacing3, &sdr_ctrl->mp_pacing3); }
static void set_sdr_mp_threshold(void)
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index e41815b..58fe26e 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -465,23 +465,21 @@ static void set_sdr_mp_pacing(void)
static void set_sdr_mp_threshold(void) { - debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); - clrsetbits_le32(&sdr_ctrl->mp_threshold0, - SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << + const u32 mp_threshold0 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_threshold1, - SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << + const u32 mp_threshold1 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_threshold2, - SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << + const u32 mp_threshold2 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB); -}
+ debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); + writel(mp_threshold0, &sdr_ctrl->mp_threshold0); + writel(mp_threshold1, &sdr_ctrl->mp_threshold1); + writel(mp_threshold2, &sdr_ctrl->mp_threshold2); +}
/* Function to initialize SDRAM MMR */ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
Introduce this seemingly massive structure, which holds required values of all the registers of the SDRAM controller. The idea here is to avoid including the sdram.h header file, which is full of ad-hoc macros that polute the global namespace. Once the cleanup of sdram.c would be complete and all registers would be loaded from this new socfpga_sdram_config, a board file will only pass this structure into the sdram.c . This will hide all the horrors generated by QTS in the board directory.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 341 ++++++++++++++++++++++++--------------------- 1 file changed, 179 insertions(+), 162 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 58fe26e..c10e3fd 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -37,6 +37,146 @@ static struct socfpga_system_manager *sysmgr_regs = static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+static struct socfpga_sdram_config { + u32 ctrl_cfg; + u32 dram_timing1; + u32 dram_timing2; + u32 dram_timing3; + u32 dram_timing4; + u32 lowpwr_timing; + u32 dram_addrw; + u32 static_cfg; + u32 fifo_cfg; + u32 mp_weight0; + u32 mp_weight1; + u32 mp_weight2; + u32 mp_weight3; + u32 mp_pacing0; + u32 mp_pacing1; + u32 mp_pacing2; + u32 mp_pacing3; + u32 mp_threshold0; + u32 mp_threshold1; + u32 mp_threshold2; +} sdram_config = { + .ctrl_cfg = + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB), + .dram_timing1 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB), + .dram_timing2 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB), + .dram_timing3 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB), + .dram_timing4 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB), + .lowpwr_timing = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), + .dram_addrw = + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), + .static_cfg = + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), + .fifo_cfg = + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), + .mp_weight0 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), + .mp_weight1 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB), + .mp_weight2 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB), + .mp_weight3 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB), + .mp_pacing0 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB), + .mp_pacing1 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB), + .mp_pacing2 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB), + .mp_pacing3 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB), + .mp_threshold0 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << + SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB), + .mp_threshold1 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << + SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB), + .mp_threshold2 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << + SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), +}; + /** * get_errata_rows() - Up the number of DRAM rows to cover entire address space * @@ -252,26 +392,10 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value) return 0; }
-static void set_sdr_ctrlcfg(void) +static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg) { u32 addrorder; - u32 ctrl_cfg = - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << - SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << - SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << - SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << - SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << - SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << - SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << - SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << - SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB); + u32 ctrl_cfg = cfg->ctrl_cfg;
debug("\nConfiguring CTRLCFG\n");
@@ -301,75 +425,25 @@ static void set_sdr_ctrlcfg(void) writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); }
-static void set_sdr_dram_timing(void) +static void set_sdr_dram_timing(struct socfpga_sdram_config *cfg) { - const u32 dram_timing1 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << - SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << - SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << - SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << - SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << - SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << - SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB); - - const u32 dram_timing2 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << - SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << - SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << - SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << - SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << - SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB); - - const u32 dram_timing3 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << - SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << - SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << - SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << - SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << - SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB); - - const u32 dram_timing4 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << - SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << - SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB); - - const u32 lowpwr_timing = - (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << - SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << - SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB); - debug("Configuring DRAMTIMING1\n"); - writel(dram_timing1, &sdr_ctrl->dram_timing1); + writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
debug("Configuring DRAMTIMING2\n"); - writel(dram_timing2, &sdr_ctrl->dram_timing2); + writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
debug("Configuring DRAMTIMING3\n"); - writel(dram_timing3, &sdr_ctrl->dram_timing3); + writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
debug("Configuring DRAMTIMING4\n"); - writel(dram_timing4, &sdr_ctrl->dram_timing4); + writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
debug("Configuring LOWPWRTIMING\n"); - writel(lowpwr_timing, &sdr_ctrl->lowpwr_timing); + writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); }
-static void set_sdr_addr_rw(void) +static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg) { /* * SDRAM Failure When Accessing Non-Existent Memory @@ -379,106 +453,48 @@ static void set_sdr_addr_rw(void) * which is the same as "chip selects" - 1. */ const int rows = get_errata_rows(); - const u32 dram_addrw = - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | - (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | - ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB); + debug("Configuring DRAMADDRW\n"); - writel(dram_addrw, &sdr_ctrl->dram_addrw); + writel(cfg->dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB), + &sdr_ctrl->dram_addrw); }
-static void set_sdr_static_cfg(void) +static void set_sdr_static_cfg(struct socfpga_sdram_config *cfg) { - const u32 static_cfg = - (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << - SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << - SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB); - debug("Configuring STATICCFG\n"); - writel(static_cfg, &sdr_ctrl->static_cfg); + writel(cfg->static_cfg, &sdr_ctrl->static_cfg); }
-static void set_sdr_fifo_cfg(void) +static void set_sdr_fifo_cfg(struct socfpga_sdram_config *cfg) { - const u32 fifo_cfg = - (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << - SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << - SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB); - debug("Configuring FIFOCFG\n"); - writel(fifo_cfg, &sdr_ctrl->fifo_cfg); + writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); }
-static void set_sdr_mp_weight(void) +static void set_sdr_mp_weight(struct socfpga_sdram_config *cfg) { - const u32 mp_weight0 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB); - const u32 mp_weight1 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB); - const u32 mp_weight2 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB); - const u32 mp_weight3 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB); - debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); - writel(mp_weight0, &sdr_ctrl->mp_weight0); - writel(mp_weight1, &sdr_ctrl->mp_weight1); - writel(mp_weight2, &sdr_ctrl->mp_weight2); - writel(mp_weight3, &sdr_ctrl->mp_weight3); + writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); + writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); + writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); + writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); }
-static void set_sdr_mp_pacing(void) +static void set_sdr_mp_pacing(struct socfpga_sdram_config *cfg) { - const u32 mp_pacing0 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << - SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB); - const u32 mp_pacing1 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << - SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << - SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB); - const u32 mp_pacing2 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << - SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB); - const u32 mp_pacing3 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << - SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB); - debug("Configuring MPPACING_MPPACING_0\n"); - writel(mp_pacing0, &sdr_ctrl->mp_pacing0); - writel(mp_pacing1, &sdr_ctrl->mp_pacing1); - writel(mp_pacing2, &sdr_ctrl->mp_pacing2); - writel(mp_pacing3, &sdr_ctrl->mp_pacing3); + writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); + writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); + writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); + writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); }
-static void set_sdr_mp_threshold(void) +static void set_sdr_mp_threshold(struct socfpga_sdram_config *cfg) { - const u32 mp_threshold0 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << - SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB); - const u32 mp_threshold1 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << - SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB); - const u32 mp_threshold2 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << - SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB); - debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); - writel(mp_threshold0, &sdr_ctrl->mp_threshold0); - writel(mp_threshold1, &sdr_ctrl->mp_threshold1); - writel(mp_threshold2, &sdr_ctrl->mp_threshold2); + writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); + writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); + writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); }
/* Function to initialize SDRAM MMR */ @@ -486,6 +502,7 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { unsigned long reg_value; unsigned long status = 0; + struct socfpga_sdram_config *cfg = &sdram_config;
#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \ @@ -496,9 +513,9 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS, &sysmgr_regs->iswgrp_handoff[4]); #endif - set_sdr_ctrlcfg(); - set_sdr_dram_timing(); - set_sdr_addr_rw(); + set_sdr_ctrlcfg(cfg); + set_sdr_dram_timing(cfg); + set_sdr_addr_rw(cfg);
debug("Configuring DRAMIFWIDTH\n"); clrsetbits_le32(&sdr_ctrl->dram_if_width, @@ -523,7 +540,7 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
- set_sdr_static_cfg(); + set_sdr_static_cfg(cfg);
debug("Configuring CTRLWIDTH\n"); clrsetbits_le32(&sdr_ctrl->ctrl_width, @@ -536,7 +553,7 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
- set_sdr_fifo_cfg(); + set_sdr_fifo_cfg(cfg);
debug("Configuring MPPRIORITY\n"); clrsetbits_le32(&sdr_ctrl->mp_priority, @@ -544,9 +561,9 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
- set_sdr_mp_weight(); - set_sdr_mp_pacing(); - set_sdr_mp_threshold(); + set_sdr_mp_weight(cfg); + set_sdr_mp_pacing(cfg); + set_sdr_mp_threshold(cfg);
debug("Configuring PHYCTRL_PHYCTRL_0\n"); setbits_le32(&sdr_ctrl->phy_ctrl0,
Zap all the ad-hoc readbacks from the registers and other useless and broken debug output. This is really not useful and is only confusing.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 44 -------------------------------------------- 1 file changed, 44 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index c10e3fd..395b40f 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -500,7 +500,6 @@ static void set_sdr_mp_threshold(struct socfpga_sdram_config *cfg) /* Function to initialize SDRAM MMR */ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { - unsigned long reg_value; unsigned long status = 0; struct socfpga_sdram_config *cfg = &sdram_config;
@@ -574,73 +573,36 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK, CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB); - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", - (unsigned)(&sdr_ctrl->cport_width), - (unsigned)reg_value); - reg_value = readl(&sdr_ctrl->cport_width); - debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
debug("Configuring CPORTWMAP\n"); clrsetbits_le32(&sdr_ctrl->cport_wmap, SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK, CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB); - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", - (unsigned)(&sdr_ctrl->cport_wmap), - (unsigned)reg_value); - reg_value = readl(&sdr_ctrl->cport_wmap); - debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
debug("Configuring CPORTRMAP\n"); clrsetbits_le32(&sdr_ctrl->cport_rmap, SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK, CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB); - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", - (unsigned)(&sdr_ctrl->cport_rmap), - (unsigned)reg_value); - reg_value = readl(&sdr_ctrl->cport_rmap); - debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
debug("Configuring RFIFOCMAP\n"); clrsetbits_le32(&sdr_ctrl->rfifo_cmap, SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK, CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB); - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", - (unsigned)(&sdr_ctrl->rfifo_cmap), - (unsigned)reg_value); - reg_value = readl(&sdr_ctrl->rfifo_cmap); - debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
debug("Configuring WFIFOCMAP\n"); - reg_value = readl(&sdr_ctrl->wfifo_cmap); clrsetbits_le32(&sdr_ctrl->wfifo_cmap, SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK, CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB); - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", - (unsigned)(&sdr_ctrl->wfifo_cmap), - (unsigned)reg_value); - reg_value = readl(&sdr_ctrl->wfifo_cmap); - debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
debug("Configuring CPORTRDWR\n"); clrsetbits_le32(&sdr_ctrl->cport_rdwr, SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK, CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB); - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", - (unsigned)(&sdr_ctrl->cport_rdwr), - (unsigned)reg_value); - reg_value = readl(&sdr_ctrl->cport_rdwr); - debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
debug("Configuring DRAMODT\n"); clrsetbits_le32(&sdr_ctrl->dram_odt, @@ -674,12 +636,6 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) debug("Configuring STATICCFG_\n"); clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", - (unsigned)(&sdr_ctrl->static_cfg), - (unsigned)reg_value); - reg_value = readl(&sdr_ctrl->static_cfg); - debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
sdram_set_protection_config(0, sdram_calculate_size());
Suck out all the CONFIG_HPS_SDR_CTRLCFG_* from sdram_mmr_init_full() into the socfpga_sdram_config structure. There is still one ugly macro left behind, but this will be taken care of in subsequent patch.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 150 +++++++++++++++++++++++++-------------------- 1 file changed, 83 insertions(+), 67 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 395b40f..3ab552b 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -44,9 +44,24 @@ static struct socfpga_sdram_config { u32 dram_timing3; u32 dram_timing4; u32 lowpwr_timing; + u32 dram_odt; u32 dram_addrw; + u32 dram_if_width; + u32 dram_dev_width; + u32 dram_intr; + u32 lowpwr_eq; u32 static_cfg; + u32 ctrl_width; + u32 cport_width; + u32 cport_wmap; + u32 cport_rmap; + u32 rfifo_cmap; + u32 wfifo_cmap; + u32 cport_rdwr; + u32 port_cfg; + u32 fpgaport_rst; u32 fifo_cfg; + u32 mp_priority; u32 mp_weight0; u32 mp_weight1; u32 mp_weight2; @@ -58,6 +73,7 @@ static struct socfpga_sdram_config { u32 mp_threshold0; u32 mp_threshold1; u32 mp_threshold2; + u32 phy_ctrl0; } sdram_config = { .ctrl_cfg = (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << @@ -121,6 +137,11 @@ static struct socfpga_sdram_config { SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), + .dram_odt = + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << + SDR_CTRLGRP_DRAMODT_READ_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << + SDR_CTRLGRP_DRAMODT_WRITE_LSB), .dram_addrw = (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | @@ -128,16 +149,56 @@ static struct socfpga_sdram_config { SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), + .dram_if_width = + (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB), + .dram_dev_width = + (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB), + .dram_intr = + (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << + SDR_CTRLGRP_DRAMINTR_INTREN_LSB), + .lowpwr_eq = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB), .static_cfg = (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), + .ctrl_width = + (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB), + .cport_width = + (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB), + .cport_wmap = + (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB), + .cport_rmap = + (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB), + .rfifo_cmap = + (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB), + .wfifo_cmap = + (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB), + .cport_rdwr = + (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB), + .port_cfg = + (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB), + .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, .fifo_cfg = (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), + .mp_priority = + (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB), .mp_weight0 = (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), @@ -175,6 +236,7 @@ static struct socfpga_sdram_config { .mp_threshold2 = (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), + .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, };
/** @@ -517,112 +579,65 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) set_sdr_addr_rw(cfg);
debug("Configuring DRAMIFWIDTH\n"); - clrsetbits_le32(&sdr_ctrl->dram_if_width, - SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << - SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB); + writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
debug("Configuring DRAMDEVWIDTH\n"); - clrsetbits_le32(&sdr_ctrl->dram_dev_width, - SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << - SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB); + writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
debug("Configuring LOWPWREQ\n"); - clrsetbits_le32(&sdr_ctrl->lowpwr_eq, - SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK, - CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << - SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB); + writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
debug("Configuring DRAMINTR\n"); - clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << - SDR_CTRLGRP_DRAMINTR_INTREN_LSB); + writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
set_sdr_static_cfg(cfg);
debug("Configuring CTRLWIDTH\n"); - clrsetbits_le32(&sdr_ctrl->ctrl_width, - SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK, - CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << - SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB); + writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
debug("Configuring PORTCFG\n"); - clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK, - CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << - SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB); + writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
set_sdr_fifo_cfg(cfg);
debug("Configuring MPPRIORITY\n"); - clrsetbits_le32(&sdr_ctrl->mp_priority, - SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << - SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB); + writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
set_sdr_mp_weight(cfg); set_sdr_mp_pacing(cfg); set_sdr_mp_threshold(cfg);
debug("Configuring PHYCTRL_PHYCTRL_0\n"); - setbits_le32(&sdr_ctrl->phy_ctrl0, - CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0); + writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
debug("Configuring CPORTWIDTH\n"); - clrsetbits_le32(&sdr_ctrl->cport_width, - SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK, - CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << - SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB); + writel(cfg->cport_width, &sdr_ctrl->cport_width);
debug("Configuring CPORTWMAP\n"); - clrsetbits_le32(&sdr_ctrl->cport_wmap, - SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK, - CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << - SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB); + writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
debug("Configuring CPORTRMAP\n"); - clrsetbits_le32(&sdr_ctrl->cport_rmap, - SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK, - CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << - SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB); + writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
debug("Configuring RFIFOCMAP\n"); - clrsetbits_le32(&sdr_ctrl->rfifo_cmap, - SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK, - CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << - SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB); + writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
debug("Configuring WFIFOCMAP\n"); - clrsetbits_le32(&sdr_ctrl->wfifo_cmap, - SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK, - CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << - SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB); + writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
debug("Configuring CPORTRDWR\n"); - clrsetbits_le32(&sdr_ctrl->cport_rdwr, - SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK, - CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << - SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB); + writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
debug("Configuring DRAMODT\n"); - clrsetbits_le32(&sdr_ctrl->dram_odt, - SDR_CTRLGRP_DRAMODT_READ_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << - SDR_CTRLGRP_DRAMODT_READ_LSB); - - clrsetbits_le32(&sdr_ctrl->dram_odt, - SDR_CTRLGRP_DRAMODT_WRITE_MASK, - CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << - SDR_CTRLGRP_DRAMODT_WRITE_LSB); + writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ - writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, - &sysmgr_regs->iswgrp_handoff[3]); + writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
/* only enable if the FPGA is programmed */ if (fpgamgr_test_fpga_ready()) { if (sdram_write_verify(&sdr_ctrl->fpgaport_rst, - CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) { + cfg->fpgaport_rst) == 1) { status = 1; return 1; } @@ -632,9 +647,10 @@ defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) if (sdr_phy_reg != 0xffffffff) writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
-/***** Final step - apply configuration changes *****/ - debug("Configuring STATICCFG_\n"); - clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, + /* Final step - apply configuration changes */ + debug("Configuring STATICCFG\n"); + clrsetbits_le32(&sdr_ctrl->static_cfg, + SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
sdram_set_protection_config(0, sdram_calculate_size());
Pluck out the remaining CONFIG_HPS_SDR_CTRLCFG_ and put it into the socfpga_sdram_config structure.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 67 +++++++++++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 28 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 3ab552b..595f2a4 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -80,6 +80,8 @@ static struct socfpga_sdram_config { SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << @@ -145,6 +147,8 @@ static struct socfpga_sdram_config { .dram_addrw = (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << @@ -241,20 +245,29 @@ static struct socfpga_sdram_config {
/** * get_errata_rows() - Up the number of DRAM rows to cover entire address space + * @cfg: SDRAM controller configuration data * * SDRAM Failure happens when accessing non-existent memory. Artificially * increase the number of rows so that the memory controller thinks it has * 4GB of RAM. This function returns such amount of rows. */ -static int get_errata_rows(void) +static int get_errata_rows(struct socfpga_sdram_config *cfg) { /* Define constant for 4G memory - used for SDRAM errata workaround */ #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) const unsigned long long memsize = MEMSIZE_4G; - const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; - const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; - const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS; - const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS; + const unsigned int cs = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + const unsigned int rows = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + const unsigned int banks = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; + const unsigned int cols = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; const unsigned int width = 8;
unsigned long long newrows; @@ -456,7 +469,13 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg) { - u32 addrorder; + const u32 csbits = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + u32 addrorder = + (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; + u32 ctrl_cfg = cfg->ctrl_cfg;
debug("\nConfiguring CTRLCFG\n"); @@ -466,22 +485,17 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg) * Set the addrorder field of the SDRAM control register * based on the CSBITs setting. */ - switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) { - case 1: - addrorder = 0; /* chip, row, bank, column */ - if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0) + if (csbits == 1) { + if (addrorder != 0) debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); - break; - case 2: - addrorder = 2; /* row, chip, bank, column */ - if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2) + addrorder = 0; + } else if (csbits == 2) { + if (addrorder != 2) debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); - break; - default: - addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER; - break; + addrorder = 2; }
+ ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK; ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); @@ -514,10 +528,11 @@ static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg) * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, * which is the same as "chip selects" - 1. */ - const int rows = get_errata_rows(); + const int rows = get_errata_rows(cfg); + u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
debug("Configuring DRAMADDRW\n"); - writel(cfg->dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB), + writel(dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB), &sdr_ctrl->dram_addrw); }
@@ -564,16 +579,12 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { unsigned long status = 0; struct socfpga_sdram_config *cfg = &sdram_config; + const unsigned int rows = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
-#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \ -defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \ -defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \ -defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \ -defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) + writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
- writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS, - &sysmgr_regs->iswgrp_handoff[4]); -#endif set_sdr_ctrlcfg(cfg); set_sdr_dram_timing(cfg); set_sdr_addr_rw(cfg);
Merge sdr_set_*() functions which are just setting registers among the sea of register setting in sdram_mmr_init_full(). There is no need to keep them separate this way, there is nothing special about them.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 98 +++++++++++++++++----------------------------- 1 file changed, 36 insertions(+), 62 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 595f2a4..199e8b8 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -501,24 +501,6 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg) writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); }
-static void set_sdr_dram_timing(struct socfpga_sdram_config *cfg) -{ - debug("Configuring DRAMTIMING1\n"); - writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); - - debug("Configuring DRAMTIMING2\n"); - writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); - - debug("Configuring DRAMTIMING3\n"); - writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); - - debug("Configuring DRAMTIMING4\n"); - writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); - - debug("Configuring LOWPWRTIMING\n"); - writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); -} - static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg) { /* @@ -536,44 +518,6 @@ static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg) &sdr_ctrl->dram_addrw); }
-static void set_sdr_static_cfg(struct socfpga_sdram_config *cfg) -{ - debug("Configuring STATICCFG\n"); - writel(cfg->static_cfg, &sdr_ctrl->static_cfg); -} - -static void set_sdr_fifo_cfg(struct socfpga_sdram_config *cfg) -{ - debug("Configuring FIFOCFG\n"); - writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); -} - -static void set_sdr_mp_weight(struct socfpga_sdram_config *cfg) -{ - debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); - writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); - writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); - writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); - writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); -} - -static void set_sdr_mp_pacing(struct socfpga_sdram_config *cfg) -{ - debug("Configuring MPPACING_MPPACING_0\n"); - writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); - writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); - writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); - writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); -} - -static void set_sdr_mp_threshold(struct socfpga_sdram_config *cfg) -{ - debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); - writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); - writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); - writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); -} - /* Function to initialize SDRAM MMR */ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { @@ -586,7 +530,22 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
set_sdr_ctrlcfg(cfg); - set_sdr_dram_timing(cfg); + + debug("Configuring DRAMTIMING1\n"); + writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); + + debug("Configuring DRAMTIMING2\n"); + writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); + + debug("Configuring DRAMTIMING3\n"); + writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); + + debug("Configuring DRAMTIMING4\n"); + writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); + + debug("Configuring LOWPWRTIMING\n"); + writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); + set_sdr_addr_rw(cfg);
debug("Configuring DRAMIFWIDTH\n"); @@ -601,7 +560,8 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) debug("Configuring DRAMINTR\n"); writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
- set_sdr_static_cfg(cfg); + debug("Configuring STATICCFG\n"); + writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
debug("Configuring CTRLWIDTH\n"); writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width); @@ -609,14 +569,28 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) debug("Configuring PORTCFG\n"); writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
- set_sdr_fifo_cfg(cfg); + debug("Configuring FIFOCFG\n"); + writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
debug("Configuring MPPRIORITY\n"); writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
- set_sdr_mp_weight(cfg); - set_sdr_mp_pacing(cfg); - set_sdr_mp_threshold(cfg); + debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); + writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); + writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); + writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); + writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); + + debug("Configuring MPPACING_MPPACING_0\n"); + writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); + writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); + writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); + writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); + + debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); + writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); + writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); + writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
debug("Configuring PHYCTRL_PHYCTRL_0\n"); writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
On 8/1/15 4:34 PM, Marek Vasut wrote:
Merge sdr_set_*() functions which are just setting registers among the sea of register setting in sdram_mmr_init_full(). There is no need to keep them separate this way, there is nothing special about them.
Signed-off-by: Marek Vasut marex@denx.de
drivers/ddr/altera/sdram.c | 98 +++++++++++++++++----------------------------- 1 file changed, 36 insertions(+), 62 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 595f2a4..199e8b8 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -501,24 +501,6 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg) writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); }
<snip>
@@ -586,7 +530,22 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
set_sdr_ctrlcfg(cfg);
- set_sdr_dram_timing(cfg);
- debug("Configuring DRAMTIMING1\n");
- writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
- debug("Configuring DRAMTIMING2\n");
- writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
- debug("Configuring DRAMTIMING3\n");
- writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
- debug("Configuring DRAMTIMING4\n");
- writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
- debug("Configuring LOWPWRTIMING\n");
- writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
I don't think we need all of these debug prints?
Dinh
On Wednesday, August 05, 2015 at 05:59:56 PM, Dinh Nguyen wrote:
On 8/1/15 4:34 PM, Marek Vasut wrote:
Merge sdr_set_*() functions which are just setting registers among the sea of register setting in sdram_mmr_init_full(). There is no need to keep them separate this way, there is nothing special about them.
Signed-off-by: Marek Vasut marex@denx.de
drivers/ddr/altera/sdram.c | 98 +++++++++++++++++----------------------------- 1 file changed, 36 insertions(+), 62 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 595f2a4..199e8b8 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -501,24 +501,6 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
}
<snip>
@@ -586,7 +530,22 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
set_sdr_ctrlcfg(cfg);
- set_sdr_dram_timing(cfg);
- debug("Configuring DRAMTIMING1\n");
- writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
- debug("Configuring DRAMTIMING2\n");
- writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
- debug("Configuring DRAMTIMING3\n");
- writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
- debug("Configuring DRAMTIMING4\n");
- writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
- debug("Configuring LOWPWRTIMING\n");
- writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
I don't think we need all of these debug prints?
Me neither ;-) I think there's waaaay too many (useless) debug() prints throughout the entire DDR driver, not only here. I tried to preserve the debug prints in their pristine state so far.
I think that in sequencer.c, the debug prints cause even more mess, since there is a lot of code only to cater for printing debug stuff. All kinda of variables get computed only to be used in some debug() print and then discarded. I think a lot of code could be removed from there if we discard those debug() prints.
I'd be happy if someone does a debug() print cleanup once things settle. Would you like to prepare the patches ? :-)
Best regards, Marek Vasut
Rework remaining two register setting functions such that they only return the final register value. Move the register setting into the block of register I/O in sdram_mmr_init_full().
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 199e8b8..1d9324a 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -467,7 +467,7 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value) return 0; }
-static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg) +static u32 sdr_get_ctrlcfg(struct socfpga_sdram_config *cfg) { const u32 csbits = ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> @@ -478,8 +478,6 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
u32 ctrl_cfg = cfg->ctrl_cfg;
- debug("\nConfiguring CTRLCFG\n"); - /* * SDRAM Failure When Accessing Non-Existent Memory * Set the addrorder field of the SDRAM control register @@ -498,10 +496,10 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg) ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK; ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
- writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); + return ctrl_cfg; }
-static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg) +static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg) { /* * SDRAM Failure When Accessing Non-Existent Memory @@ -513,9 +511,7 @@ static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg) const int rows = get_errata_rows(cfg); u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
- debug("Configuring DRAMADDRW\n"); - writel(dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB), - &sdr_ctrl->dram_addrw); + return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); }
/* Function to initialize SDRAM MMR */ @@ -527,9 +523,13 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+ const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); + const u32 dram_addrw = sdr_get_addr_rw(cfg); + writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
- set_sdr_ctrlcfg(cfg); + debug("\nConfiguring CTRLCFG\n"); + writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
debug("Configuring DRAMTIMING1\n"); writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); @@ -546,7 +546,8 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) debug("Configuring LOWPWRTIMING\n"); writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
- set_sdr_addr_rw(cfg); + debug("Configuring DRAMADDRW\n"); + writel(dram_addrw, &sdr_ctrl->dram_addrw);
debug("Configuring DRAMIFWIDTH\n"); writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
Pull out the block of register programming into a separate function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 1d9324a..2377b45 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -514,20 +514,17 @@ static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg) return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); }
-/* Function to initialize SDRAM MMR */ -unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) +/** + * sdr_load_regs() - Load SDRAM controller registers + * @cfg: SDRAM controller configuration data + * + * This function loads the register values into the SDRAM controller block. + */ +static void sdr_load_regs(struct socfpga_sdram_config *cfg) { - unsigned long status = 0; - struct socfpga_sdram_config *cfg = &sdram_config; - const unsigned int rows = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; - const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); const u32 dram_addrw = sdr_get_addr_rw(cfg);
- writel(rows, &sysmgr_regs->iswgrp_handoff[4]); - debug("\nConfiguring CTRLCFG\n"); writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
@@ -616,6 +613,20 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
debug("Configuring DRAMODT\n"); writel(cfg->dram_odt, &sdr_ctrl->dram_odt); +} + +/* Function to initialize SDRAM MMR */ +unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) +{ + unsigned long status = 0; + struct socfpga_sdram_config *cfg = &sdram_config; + const unsigned int rows = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + + writel(rows, &sysmgr_regs->iswgrp_handoff[4]); + + sdr_load_regs(cfg);
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
Add kerneldoc.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 2377b45..295747b 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -615,7 +615,12 @@ static void sdr_load_regs(struct socfpga_sdram_config *cfg) writel(cfg->dram_odt, &sdr_ctrl->dram_odt); }
-/* Function to initialize SDRAM MMR */ +/** + * sdram_mmr_init_full() - Function to initialize SDRAM MMR + * @sdr_phy_reg: Value of the PHY control register 0 + * + * Initialize the SDRAM MMR. + */ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { unsigned long status = 0;
Fix the return value so that standard errno return values can be used.
Signed-off-by: Marek Vasut marex@denx.de --- arch/arm/mach-socfpga/include/mach/sdram.h | 2 +- drivers/ddr/altera/sdram.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index d57257d..89240b8 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -9,7 +9,7 @@ #ifndef __ASSEMBLY__
unsigned long sdram_calculate_size(void); -unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg); +int sdram_mmr_init_full(unsigned int sdr_phy_reg); int sdram_calibration_full(void);
extern int sdram_calibration(void); diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 295747b..68a9b60 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <errno.h> #include <div64.h> #include <watchdog.h> #include <asm/arch/fpga_manager.h> @@ -621,7 +622,7 @@ static void sdr_load_regs(struct socfpga_sdram_config *cfg) * * Initialize the SDRAM MMR. */ -unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) +int sdram_mmr_init_full(unsigned int sdr_phy_reg) { unsigned long status = 0; struct socfpga_sdram_config *cfg = &sdram_config;
Introduce socfpga_sdram_get_config() function implement in a board file, which returns the socfpga_sdram_config structure. This is the last step in cleaning up the socfpga_mmr_init_full(), but not the last step which allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c thus far.
Signed-off-by: Marek Vasut marex@denx.de --- arch/arm/mach-socfpga/include/mach/sdram.h | 42 ++++++ board/altera/socfpga/Makefile | 3 +- board/altera/socfpga/wrap_sdram_config.c | 185 ++++++++++++++++++++++++ drivers/ddr/altera/sdram.c | 216 +---------------------------- 4 files changed, 234 insertions(+), 212 deletions(-) create mode 100644 board/altera/socfpga/wrap_sdram_config.c
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 89240b8..0cebd50 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -73,6 +73,48 @@ struct socfpga_sdr_ctrl { u32 phy_ctrl2; };
+/* SDRAM configuration structure for the SPL. */ +struct socfpga_sdram_config { + u32 ctrl_cfg; + u32 dram_timing1; + u32 dram_timing2; + u32 dram_timing3; + u32 dram_timing4; + u32 lowpwr_timing; + u32 dram_odt; + u32 dram_addrw; + u32 dram_if_width; + u32 dram_dev_width; + u32 dram_intr; + u32 lowpwr_eq; + u32 static_cfg; + u32 ctrl_width; + u32 cport_width; + u32 cport_wmap; + u32 cport_rmap; + u32 rfifo_cmap; + u32 wfifo_cmap; + u32 cport_rdwr; + u32 port_cfg; + u32 fpgaport_rst; + u32 fifo_cfg; + u32 mp_priority; + u32 mp_weight0; + u32 mp_weight1; + u32 mp_weight2; + u32 mp_weight3; + u32 mp_pacing0; + u32 mp_pacing1; + u32 mp_pacing2; + u32 mp_pacing3; + u32 mp_threshold0; + u32 mp_threshold1; + u32 mp_threshold2; + u32 phy_ctrl0; +}; + +const struct socfpga_sdram_config *socfpga_get_sdram_config(void); + #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile index 640f629..5a15c71 100644 --- a/board/altera/socfpga/Makefile +++ b/board/altera/socfpga/Makefile @@ -7,4 +7,5 @@ #
obj-y := socfpga.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o +obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ + wrap_sdram_config.o diff --git a/board/altera/socfpga/wrap_sdram_config.c b/board/altera/socfpga/wrap_sdram_config.c new file mode 100644 index 0000000..c70854e --- /dev/null +++ b/board/altera/socfpga/wrap_sdram_config.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2015 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/sdram.h> +/* QTS output file. */ +#include "qts/sdram_config.h" + +static const struct socfpga_sdram_config sdram_config = { + .ctrl_cfg = + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << + SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << + SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << + SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << + SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << + SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << + SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << + SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << + SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB), + .dram_timing1 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << + SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << + SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << + SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << + SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << + SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << + SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB), + .dram_timing2 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << + SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << + SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << + SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << + SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << + SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB), + .dram_timing3 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << + SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << + SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << + SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << + SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << + SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB), + .dram_timing4 = + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << + SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << + SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB), + .lowpwr_timing = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << + SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << + SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), + .dram_odt = + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << + SDR_CTRLGRP_DRAMODT_READ_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << + SDR_CTRLGRP_DRAMODT_WRITE_LSB), + .dram_addrw = + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | + ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), + .dram_if_width = + (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << + SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB), + .dram_dev_width = + (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << + SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB), + .dram_intr = + (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << + SDR_CTRLGRP_DRAMINTR_INTREN_LSB), + .lowpwr_eq = + (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << + SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB), + .static_cfg = + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << + SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << + SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), + .ctrl_width = + (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << + SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB), + .cport_width = + (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << + SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB), + .cport_wmap = + (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << + SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB), + .cport_rmap = + (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << + SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB), + .rfifo_cmap = + (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << + SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB), + .wfifo_cmap = + (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << + SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB), + .cport_rdwr = + (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << + SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB), + .port_cfg = + (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << + SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB), + .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, + .fifo_cfg = + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << + SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << + SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), + .mp_priority = + (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << + SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB), + .mp_weight0 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), + .mp_weight1 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB), + .mp_weight2 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB), + .mp_weight3 = + (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << + SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB), + .mp_pacing0 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << + SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB), + .mp_pacing1 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << + SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB), + .mp_pacing2 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << + SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB), + .mp_pacing3 = + (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << + SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB), + .mp_threshold0 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << + SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB), + .mp_threshold1 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << + SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB), + .mp_threshold2 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << + SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), + .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, +}; + +const struct socfpga_sdram_config *socfpga_get_sdram_config(void) +{ + return &sdram_config; +} diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 68a9b60..5267ddc 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -38,212 +38,6 @@ static struct socfpga_system_manager *sysmgr_regs = static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
-static struct socfpga_sdram_config { - u32 ctrl_cfg; - u32 dram_timing1; - u32 dram_timing2; - u32 dram_timing3; - u32 dram_timing4; - u32 lowpwr_timing; - u32 dram_odt; - u32 dram_addrw; - u32 dram_if_width; - u32 dram_dev_width; - u32 dram_intr; - u32 lowpwr_eq; - u32 static_cfg; - u32 ctrl_width; - u32 cport_width; - u32 cport_wmap; - u32 cport_rmap; - u32 rfifo_cmap; - u32 wfifo_cmap; - u32 cport_rdwr; - u32 port_cfg; - u32 fpgaport_rst; - u32 fifo_cfg; - u32 mp_priority; - u32 mp_weight0; - u32 mp_weight1; - u32 mp_weight2; - u32 mp_weight3; - u32 mp_pacing0; - u32 mp_pacing1; - u32 mp_pacing2; - u32 mp_pacing3; - u32 mp_threshold0; - u32 mp_threshold1; - u32 mp_threshold2; - u32 phy_ctrl0; -} sdram_config = { - .ctrl_cfg = - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << - SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << - SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << - SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << - SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << - SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << - SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << - SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << - SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << - SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB), - .dram_timing1 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << - SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << - SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << - SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << - SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << - SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << - SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB), - .dram_timing2 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << - SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << - SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << - SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << - SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << - SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB), - .dram_timing3 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << - SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << - SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << - SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << - SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << - SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB), - .dram_timing4 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << - SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << - SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB), - .lowpwr_timing = - (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << - SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << - SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), - .dram_odt = - (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << - SDR_CTRLGRP_DRAMODT_READ_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << - SDR_CTRLGRP_DRAMODT_WRITE_LSB), - .dram_addrw = - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | - ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), - .dram_if_width = - (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << - SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB), - .dram_dev_width = - (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << - SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB), - .dram_intr = - (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << - SDR_CTRLGRP_DRAMINTR_INTREN_LSB), - .lowpwr_eq = - (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << - SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB), - .static_cfg = - (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << - SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << - SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), - .ctrl_width = - (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << - SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB), - .cport_width = - (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << - SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB), - .cport_wmap = - (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << - SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB), - .cport_rmap = - (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << - SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB), - .rfifo_cmap = - (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << - SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB), - .wfifo_cmap = - (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << - SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB), - .cport_rdwr = - (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << - SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB), - .port_cfg = - (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << - SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB), - .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, - .fifo_cfg = - (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << - SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << - SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), - .mp_priority = - (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << - SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB), - .mp_weight0 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), - .mp_weight1 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB), - .mp_weight2 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB), - .mp_weight3 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << - SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB), - .mp_pacing0 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << - SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB), - .mp_pacing1 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << - SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << - SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB), - .mp_pacing2 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << - SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB), - .mp_pacing3 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << - SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB), - .mp_threshold0 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << - SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB), - .mp_threshold1 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << - SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB), - .mp_threshold2 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << - SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), - .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, -}; - /** * get_errata_rows() - Up the number of DRAM rows to cover entire address space * @cfg: SDRAM controller configuration data @@ -252,7 +46,7 @@ static struct socfpga_sdram_config { * increase the number of rows so that the memory controller thinks it has * 4GB of RAM. This function returns such amount of rows. */ -static int get_errata_rows(struct socfpga_sdram_config *cfg) +static int get_errata_rows(const struct socfpga_sdram_config *cfg) { /* Define constant for 4G memory - used for SDRAM errata workaround */ #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) @@ -468,7 +262,7 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value) return 0; }
-static u32 sdr_get_ctrlcfg(struct socfpga_sdram_config *cfg) +static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) { const u32 csbits = ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> @@ -500,7 +294,7 @@ static u32 sdr_get_ctrlcfg(struct socfpga_sdram_config *cfg) return ctrl_cfg; }
-static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg) +static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) { /* * SDRAM Failure When Accessing Non-Existent Memory @@ -521,7 +315,7 @@ static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg) * * This function loads the register values into the SDRAM controller block. */ -static void sdr_load_regs(struct socfpga_sdram_config *cfg) +static void sdr_load_regs(const struct socfpga_sdram_config *cfg) { const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); const u32 dram_addrw = sdr_get_addr_rw(cfg); @@ -625,7 +419,7 @@ static void sdr_load_regs(struct socfpga_sdram_config *cfg) int sdram_mmr_init_full(unsigned int sdr_phy_reg) { unsigned long status = 0; - struct socfpga_sdram_config *cfg = &sdram_config; + const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); const unsigned int rows = (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
Pluck out all of the CONFIG_HPS_SDR_CTRLCFG_* macros. This change makes sdram.c completely clear of these macros and allows removing of the ugly include of sdram.h . The namespace is now a much nicer place!
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 5267ddc..b540c78 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -12,12 +12,6 @@ #include <asm/arch/system_manager.h> #include <asm/io.h>
-/* - * FIXME: This path is temporary until the SDRAM driver gets - * a proper thorough cleanup. - */ -#include "../../../board/altera/socfpga/qts/sdram_config.h" - DECLARE_GLOBAL_DATA_PTR;
struct sdram_prot_rule { @@ -470,6 +464,13 @@ unsigned long sdram_calculate_size(void) { unsigned long temp; unsigned long row, bank, col, cs, width; + const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); + const unsigned int csbits = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + const unsigned int rowbits = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
temp = readl(&sdr_ctrl->dram_addrw); col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> @@ -490,7 +491,7 @@ unsigned long sdram_calculate_size(void) */ row = readl(&sysmgr_regs->iswgrp_handoff[4]); if (row == 0) - row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; + row = rowbits; /* If the stored handoff value for rows is greater than * the field width in the sdr.dramaddrw register then * something is very wrong. Revert to using the the #define @@ -498,7 +499,7 @@ unsigned long sdram_calculate_size(void) * using a broken value. */ if (row > 31) - row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS; + row = rowbits;
bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; @@ -512,7 +513,7 @@ unsigned long sdram_calculate_size(void) SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB; cs += 1;
- cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS; + cs = csbits;
width = readl(&sdr_ctrl->dram_if_width); /* ECC would not be calculated as its not addressible */
Clean up coding style, mostly clean up comments, add kerneldoc. Also, zap assignment of the "cs" variable, which is outright dead code, so just remove it.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 35 ++++++++++++----------------------- 1 file changed, 12 insertions(+), 23 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index b540c78..45ae690 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -451,14 +451,11 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) return status; }
-/* - * To calculate SDRAM device size based on SDRAM controller parameters. - * Size is specified in bytes. +/** + * sdram_calculate_size() - Calculate SDRAM size * - * NOTE: - * This function is compiled and linked into the preloader and - * Uboot (there may be others). So if this function changes, the Preloader - * and UBoot must be updated simultaneously. + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. */ unsigned long sdram_calculate_size(void) { @@ -476,23 +473,17 @@ unsigned long sdram_calculate_size(void) col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
- /* SDRAM Failure When Accessing Non-Existent Memory + /* + * SDRAM Failure When Accessing Non-Existent Memory * Use ROWBITS from Quartus/QSys to calculate SDRAM size * since the FB specifies we modify ROWBITs to work around SDRAM * controller issue. - * - * If the stored handoff value for rows is 0, it probably means - * the preloader is older than UBoot. Use the - * #define from the SOCEDS Tools per Crucible review - * uboot-socfpga-204. Note that this is not a supported - * configuration and is not tested. The customer - * should be using preloader and uboot built from the - * same tag. */ row = readl(&sysmgr_regs->iswgrp_handoff[4]); if (row == 0) row = rowbits; - /* If the stored handoff value for rows is greater than + /* + * If the stored handoff value for rows is greater than * the field width in the sdr.dramaddrw register then * something is very wrong. Revert to using the the #define * value handed off by the SOCEDS tool chain instead of @@ -504,18 +495,16 @@ unsigned long sdram_calculate_size(void) bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
- /* SDRAM Failure When Accessing Non-Existent Memory + /* + * SDRAM Failure When Accessing Non-Existent Memory * Use CSBITs from Quartus/QSys to calculate SDRAM size * since the FB specifies we modify CSBITs to work around SDRAM * controller issue. */ - cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB; - cs += 1; - cs = csbits;
width = readl(&sdr_ctrl->dram_if_width); + /* ECC would not be calculated as its not addressible */ if (width == SDRAM_WIDTH_32BIT_WITH_ECC) width = 32; @@ -526,7 +515,7 @@ unsigned long sdram_calculate_size(void) temp = 1 << (row + bank + col); temp = temp * cs * (width / 8);
- debug("sdram_calculate_memory returns %ld\n", temp); + debug("%s returns %ld\n", __func__, temp);
return temp; }
Clean the function up so that it's obvious what it is doing, fix the formating strings in debug outputs, add kerneldoc. Make the function return proper errno-compliant return values and propagate this change throughout sdram.c
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 51 +++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 25 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 45ae690..fe2e753 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -231,28 +231,30 @@ static void sdram_dump_protection_config(void) } }
-/* Function to write to register and verify the write */ -static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value) +/** + * sdram_write_verify() - write to register and verify the write. + * @addr: Register address + * @val: Value to be written and verified + * + * This function writes to a register, reads back the value and compares + * the result with the written value to check if the data match. + */ +static unsigned sdram_write_verify(const u32 *addr, const u32 val) { -#ifndef SDRAM_MMR_SKIP_VERIFY - unsigned reg_value1; -#endif - debug(" Write - Address "); - debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value); - /* Write to register */ - writel(reg_value, addr); -#ifndef SDRAM_MMR_SKIP_VERIFY + u32 rval; + + debug(" Write - Address 0x%p Data 0x%08x\n", addr, val); + writel(val, addr); + debug(" Read and verify..."); - /* Read back the wrote value */ - reg_value1 = readl(addr); - /* Indicate failure if value not matched */ - if (reg_value1 != reg_value) { - debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n", - (u32)addr, reg_value, reg_value1); - return 1; + rval = readl(addr); + if (rval != val) { + debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n", + addr, val, rval); + return -EINVAL; } + debug("correct!\n"); -#endif /* SDRAM_MMR_SKIP_VERIFY */ return 0; }
@@ -412,11 +414,11 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg) */ int sdram_mmr_init_full(unsigned int sdr_phy_reg) { - unsigned long status = 0; const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); const unsigned int rows = (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + int ret;
writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
@@ -427,11 +429,10 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg)
/* only enable if the FPGA is programmed */ if (fpgamgr_test_fpga_ready()) { - if (sdram_write_verify(&sdr_ctrl->fpgaport_rst, - cfg->fpgaport_rst) == 1) { - status = 1; - return 1; - } + ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst, + cfg->fpgaport_rst); + if (ret) + return ret; }
/* Restore the SDR PHY Register if valid */ @@ -448,7 +449,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg)
sdram_dump_protection_config();
- return status; + return 0; }
/**
Add kerneldoc to functions which are missing it, but are already cleaned up.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index fe2e753..e16f116 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -258,6 +258,12 @@ static unsigned sdram_write_verify(const u32 *addr, const u32 val) return 0; }
+/** + * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register + * @cfg: SDRAM controller configuration data + * + * Return the value of DRAM CTRLCFG register. + */ static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) { const u32 csbits = @@ -290,6 +296,12 @@ static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) return ctrl_cfg; }
+/** + * sdr_get_addr_rw() - Get the value of DRAM ADDRW register + * @cfg: SDRAM controller configuration data + * + * Return the value of DRAM ADDRW register. + */ static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) { /*
Zap an obscure unneeded cast and clean other minor nits in this function.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index e16f116..da7f27f 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -117,8 +117,8 @@ static void sdram_set_rule(struct sdram_prot_rule *prule) writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
/* Obtain the address bits */ - lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF); - hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF); + lo_addr_bits = prule->sdram_start >> 20ULL; + hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
debug("sdram set rule start %x, %lld\n", lo_addr_bits, prule->sdram_start); @@ -138,7 +138,7 @@ static void sdram_set_rule(struct sdram_prot_rule *prule) &sdr_ctrl->prot_rule_data);
/* write the rule */ - writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr); + writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
/* Set rule number to 0 by default */ writel(0, &sdr_ctrl->prot_rule_rdwr); @@ -183,7 +183,7 @@ static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end writel(0x0, &sdr_ctrl->protport_default);
/* Clear all protection rules for warm boot case */ - memset(&rule, 0, sizeof(struct sdram_prot_rule)); + memset(&rule, 0, sizeof(rule));
for (rules = 0; rules < 20; rules++) { rule.rule = rules;
Fix the data types and zap unnecessary type change.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index da7f27f..22cad88 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -146,14 +146,14 @@ static void sdram_set_rule(struct sdram_prot_rule *prule)
static void sdram_get_rule(struct sdram_prot_rule *prule) { - uint32_t addr; - uint32_t id; - uint32_t data; + u32 addr; + u32 id; + u32 data; int ruleno = prule->rule;
/* Read the rule */ writel(ruleno, &sdr_ctrl->prot_rule_rdwr); - writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr); + writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
/* Get the addresses */ addr = readl(&sdr_ctrl->prot_rule_addr);
Originally, both sdram_start and sdram_end were 64b values. The sdram_start had no reason for being so, since our address space is only 32b, so switching sdram_start to u32 is simple.
The sdram_end is a bit more complex, since it can actually be set to (1 << 32) if someone really wanted to use an SoCFPGA with 4 GiB of DRAM and fixed the code around a little. But, the code handling the protection rules internally decrements the sdram_end variable anyway. Thus, instead of calling the code and passing in the address of the SDRAM end, pass in the address already decremented by one. This lets the sdram_end be 32b as well.
Signed-off-by: Marek Vasut marex@denx.de --- drivers/ddr/altera/sdram.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 22cad88..1ed2883 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct sdram_prot_rule { - u64 sdram_start; /* SDRAM start address */ - u64 sdram_end; /* SDRAM end address */ + u32 sdram_start; /* SDRAM start address */ + u32 sdram_end; /* SDRAM end address */ u32 rule; /* SDRAM protection rule number: 0-19 */ int valid; /* Rule valid or not? 1 - valid, 0 not*/
@@ -109,8 +109,8 @@ static int get_errata_rows(const struct socfpga_sdram_config *cfg) /* SDRAM protection rules vary from 0-19, a total of 20 rules. */ static void sdram_set_rule(struct sdram_prot_rule *prule) { - uint32_t lo_addr_bits; - uint32_t hi_addr_bits; + u32 lo_addr_bits; + u32 hi_addr_bits; int ruleno = prule->rule;
/* Select the rule */ @@ -118,11 +118,11 @@ static void sdram_set_rule(struct sdram_prot_rule *prule)
/* Obtain the address bits */ lo_addr_bits = prule->sdram_start >> 20ULL; - hi_addr_bits = (prule->sdram_end - 1) >> 20ULL; + hi_addr_bits = prule->sdram_end >> 20ULL;
- debug("sdram set rule start %x, %lld\n", lo_addr_bits, + debug("sdram set rule start %x, %d\n", lo_addr_bits, prule->sdram_start); - debug("sdram set rule end %x, %lld\n", hi_addr_bits, + debug("sdram set rule end %x, %d\n", hi_addr_bits, prule->sdram_end);
/* Set rule addresses */ @@ -174,7 +174,8 @@ static void sdram_get_rule(struct sdram_prot_rule *prule) prule->result = (data >> 13) & 0x1; }
-static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end) +static void +sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) { struct sdram_prot_rule rule; int rules; @@ -219,8 +220,8 @@ static void sdram_dump_protection_config(void) for (rules = 0; rules < 20; rules++) { sdram_get_rule(&rule); debug("Rule %d, rules ...\n", rules); - debug(" sdram start %llx\n", rule.sdram_start); - debug(" sdram end %llx\n", rule.sdram_end); + debug(" sdram start %x\n", rule.sdram_start); + debug(" sdram end %x\n", rule.sdram_end); debug(" low prot id %d, hi prot id %d\n", rule.lo_prot_id, rule.hi_prot_id); @@ -457,7 +458,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
- sdram_set_protection_config(0, sdram_calculate_size()); + sdram_set_protection_config(0, sdram_calculate_size() - 1);
sdram_dump_protection_config();
On Saturday, August 01, 2015 at 11:34:29 PM, Marek Vasut wrote:
This entire series focuses solely on cleaning up the drivers/ddr/altera/sdram.c file. After this series, this one file is totally checkpatch clean and does not pull in any weird qts-generated macros ; all that is wrapped in the board file.
This micro-series applies on top of my previous mega-series [1]. This series is available via git at [2].
[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg178890.html [2] http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/06 -ddr-part2
Great, looks like this and the FPGA detection (SCC manager cleanup) are the last remaining pieces of the SoCFPGA stuff before I send a PR :-)
Best regards, Marek Vasut
On 8/1/15 4:34 PM, Marek Vasut wrote:
This entire series focuses solely on cleaning up the drivers/ddr/altera/sdram.c file. After this series, this one file is totally checkpatch clean and does not pull in any weird qts-generated macros ; all that is wrapped in the board file.
This micro-series applies on top of my previous mega-series [1]. This series is available via git at [2].
My only comment for this series is that there seems to be alot of redundant debug() in the file drivers/ddr/altera/sdram.c in the function sdr_load_regs(). No big deal and can probably be cleaned up further with a separate patch.
Otherwise, for the whole series:
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Thanks, Dinh
On Wednesday, August 05, 2015 at 06:26:18 PM, Dinh Nguyen wrote:
On 8/1/15 4:34 PM, Marek Vasut wrote:
This entire series focuses solely on cleaning up the drivers/ddr/altera/sdram.c file. After this series, this one file is totally checkpatch clean and does not pull in any weird qts-generated macros ; all that is wrapped in the board file.
This micro-series applies on top of my previous mega-series [1]. This series is available via git at [2].
My only comment for this series is that there seems to be alot of redundant debug() in the file drivers/ddr/altera/sdram.c in the function sdr_load_regs(). No big deal and can probably be cleaned up further with a separate patch.
Would you like to work on that please ?
Otherwise, for the whole series:
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Excellent, thank you for keeping up with this blast of patches! :-)
Best regards, Marek Vasut
participants (2)
-
Dinh Nguyen -
Marek Vasut