The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference.

Signed-off-by: Marek Vasut marex@denx.de --- include/configs/socfpga_common.h | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 55ca0fb5b0..fbfc6b63a0 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -266,12 +266,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);

/* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif #endif

/* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +#endif #endif

/*