On 2019/7/2 上午10:05, Kever Yang wrote:

Hi Mark,

On 07/01/2019 12:01 AM, Mark Kettenis wrote:

...

The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open.

Signed-off-by: Mark Kettenis kettenis@openbsd.org

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Applied to u-boot-rockchip.

Thanks, - Kever

Thanks,

• Kever

...

---

drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 79007b8682..d9950c159b 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1080,6 +1080,18 @@ static int rk3399_clk_enable(struct clk *clk) case PCLK_GMAC: /* Required to successfully probe the Designware GMAC driver */ return 0;

• case SCLK_USB3OTG0_REF:

• case SCLK_USB3OTG1_REF:

• case SCLK_USB3OTG0_SUSPEND:

• case SCLK_USB3OTG1_SUSPEND:

• case ACLK_USB3OTG0:

• case ACLK_USB3OTG1:

• case ACLK_USB3_RKSOC_AXI_PERF:

• case ACLK_USB3:

• case ACLK_USB3_GRF:

• /* Required to successfully probe the Designware USB3 driver */
  

• return 0;
  

  }

  debug("%s: unsupported clk %ld\n", __func__, clk->id);

---

U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

On 2019/7/1 上午12:01, Mark Kettenis wrote:

Add compatible string for RK3399 and enable it by default on Rockchip platforms with USB3 support.

Signed-off-by: Mark Kettenis kettenis@openbsd.org Reviewed-by: Kever Yang kever.yang@rock-chips.com

Applied to u-boot-rockchip.

Thanks, - Kever

---

drivers/usb/host/Kconfig | 1 + drivers/usb/host/dwc3-of-simple.c | 1 + 2 files changed, 2 insertions(+)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b1188bcbf5..ac68aa2d27 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,6 +24,7 @@ config USB_XHCI_DWC3 config USB_XHCI_DWC3_OF_SIMPLE bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" depends on DM_USB

• default y if ARCH_ROCKCHIP default y if DRA7XX help Support USB2/3 functionality in simple SoC integrations with

diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index b118997f6e..45df614b09 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -92,6 +92,7 @@ static int dwc3_of_simple_remove(struct udevice *dev)

static const struct udevice_id dwc3_of_simple_ids[] = { { .compatible = "amlogic,meson-gxl-dwc3" },

• { .compatible = "rockchip,rk3399-dwc3" }, { .compatible = "ti,dwc3" }, { } };

Hi Mark,

On 07/01/2019 12:01 AM, Mark Kettenis wrote:

Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs.

Signed-off-by: Mark Kettenis kettenis@openbsd.org

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

drivers/usb/host/xhci-dwc3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)

diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 83b9f119e7..9e8cae7ae4 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -118,6 +118,8 @@ static int xhci_dwc3_probe(struct udevice *dev) struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);

• const char *phy;

• u32 reg; int ret;

  hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));

@@ -132,6 +134,24 @@ static int xhci_dwc3_probe(struct udevice *dev)

dwc3_core_init(dwc3_reg);

• /* Set dwc3 usb2 phy config */
• reg = readl(&dwc3_reg->g_usb2phycfg[0]);
• phy = dev_read_string(dev, "phy_type");
• if (phy && strcmp(phy, "utmi_wide") == 0) {

• reg |= DWC3_GUSB2PHYCFG_PHYIF;
  

• reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
  

• reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
  

• }
• if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))

• reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  

• if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))

• reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  

• writel(reg, &dwc3_reg->g_usb2phycfg[0]);
• dr_mode = usb_get_dr_mode(dev_of_offset(dev)); if (dr_mode == USB_DR_MODE_UNKNOWN) /* by default set dual role mode to HOST */