[U-Boot] [PATCH v4 0/5] enable support for x16 NAND devices

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Pekon Gupta

28 Apr 2014 28 Apr '14

1:41 p.m.

*changes v3 -> v4* [PATCH 1/5] <no update> [PATCH 2/5] <new> mtd: nand: force NAND_CMD_READID onto 8-bit bus [PATCH 3/5] <new> mtd: nand: fix GET/SET_FEATURES address on 16-bit devices [PATCH 4/5] same as [PATCH v2 2/3] rebased over http://lists.denx.de/pipermail/u-boot/2014-April/177323.html [PATCH 5/5] <no update>

*changes v2 -> v3* [PATCH v3 1/3] (new) porting Brian Norri's patch from linux tree This patch allows reading of ONFI params independent of controller configuration and NAND device width. [PATCH v3 2/2] rebase [PATCH v2 2/4] on latest release [PATCH v3 3/3] (new) cleaned remaining GPMC_NAND_ECC_LP_xx macros from OMAP3 platform Compile Tested#> ./MAKEALL -s omap3 -s omap4 -s omap5 -s dra7xx -s am33xx

*changes v1 -> v2* [PATCH v2 1/4]: - dropped NAND_BUSWIDTH_AUTO, instead using CONFIG_SYS_NAND_ONFI_DETECTION - added check in nand_flash_detect_onfi() for x8 mode [PATCH v2 2/4]: (new) Adds CONFIG_SYS_NAND_DEVICE_WIDTH - updated for auto-detection of bus-width in non-SPL and ONFI_DETECTION mode Refer: http://lists.denx.de/pipermail/u-boot/2013-September/163748.html [PATCH v2 3/4] <no update> [PATCH v2 4/4] disabled Pulls on output only I/O pads. - updated commit description to add details about NAND cape

*original v1* This series includes independent patch-sets aiming to enable x16 NAND support on AM33xx boards (like beaglebone-LT). [PATCH 1/4]: This patch is ported from linux driver/mtd/nand to allow detection device-width of NAND by reading ONFI parameter page. [PATCH 2/4]: enable NAND_BUSWIDTH_AUTO feature in omap_nand.c [PATCH 3/4]: cleaning of GPMC configs for NAND and NOR

Brian Norris (2): mtd: nand: don't use read_buf for 8-bit ONFI transfers mtd: nand: force NAND_CMD_READID onto 8-bit bus

David Mosberger (1): mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

Pekon Gupta (2): mtd: nand: omap: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT

-- 1.8.5.1.163.gd7aced9

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Pekon Gupta

28 Apr 28 Apr

1:41 p.m.

New subject: [U-Boot] [PATCH v4 1/5] mtd: nand: don't use read_buf for 8-bit ONFI transfers

From: Brian Norris computersforpeace@gmail.com

Porting below commit from linux-tree, preserving original authorship & commit log commit bd9c6e99b58255b9de1982711ac9487c9a2f18be Author: Brian Norris computersforpeace@gmail.com mtd: nand: don't use read_buf for 8-bit ONFI transfers

Use a repeated read_byte() instead of read_buf(), since for x16 buswidth devices, we need to avoid the upper I/O[16:9] bits. See the following commit for reference:

commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree) Author: Uwe Kleine-König u.kleine-koenig@pengutronix.de Date: Thu Dec 5 22:22:04 2013 +0100

mtd: nand: don't use {read,write}_buf for 8-bit transfers

Now, I think that all barriers to probing ONFI on x16 devices are removed, so remove the check from nand_flash_detect_onfi().

Signed-off-by: Pekon Gupta pekon@ti.com --- drivers/mtd/nand/nand_base.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 1ce55fd..5d3232c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2582,7 +2582,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, int *busw) { struct nand_onfi_params *p = &chip->onfi_params; - int i; + int i, j; int val;

/* Try ONFI for unknown chip or LP */ @@ -2593,7 +2593,8 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,

chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); for (i = 0; i < 3; i++) { - chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); + for (j = 0; j < sizeof(*p); j++) + ((uint8_t *)p)[j] = chip->read_byte(mtd); if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == le16_to_cpu(p->crc)) { pr_info("ONFI param page %d valid\n", i);

-- 1.8.5.1.163.gd7aced9

Pekon Gupta

1:41 p.m.

New subject: [U-Boot] [PATCH v4 2/5] mtd: nand: force NAND_CMD_READID onto 8-bit bus

From: Brian Norris computersforpeace@gmail.com

As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page."

*Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h."

Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command.

commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris computersforpeace@gmail.com (preserving authorship)

The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20).

This fixes the column address for a few drivers which imitate the nand_base defaults.

Signed-off-by: Pekon Gupta pekon@ti.com --- drivers/mtd/nand/am335x_spl_bch.c | 2 +- drivers/mtd/nand/atmel_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 6 ++++-- drivers/mtd/nand/nand_spl_simple.c | 2 +- include/linux/mtd/nand.h | 10 ++++++++++ 5 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index c84851b..86572a2 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -55,7 +55,7 @@ static int nand_command(int block, int page, uint32_t offs, }

/* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1;

/* Set ALE and clear CLE to start address cycle */ diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index e1fc48f..e73834d 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1195,7 +1195,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)

hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);

- if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1;

hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 5d3232c..376976d 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -575,7 +575,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if ((chip->options & NAND_BUSWIDTH_16) && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; @@ -668,7 +669,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if ((chip->options & NAND_BUSWIDTH_16) && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index cead4b5..e1ddead 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -78,7 +78,7 @@ static int nand_command(int block, int page, uint32_t offs, }

/* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(command)) offs >>= 1;

/* Begin command latch cycle */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 0546565..4be8858 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -719,4 +719,14 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) } #endif

+/** + * Check if the opcode's address should be sent only on the lower 8 bits + * @command: opcode to check + */ +static inline int nand_opcode_8bits(unsigned int command) +{ + return command == NAND_CMD_READID; +} + + #endif /* __LINUX_MTD_NAND_H */

-- 1.8.5.1.163.gd7aced9

Pekon Gupta

1:41 p.m.

New subject: [U-Boot] [PATCH v4 3/5] mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

From: David Mosberger davidm@egauge.net

As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need byte-addressing on 16-bit devices.

So porting following commit from linux kernel commit e34fcb07a6d57411de6e15a47724fbe92c5caa42 Author: David Mosberger davidm@egauge.net (preserving authorship) mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

Signed-off-by: Pekon Gupta pekon@ti.com --- include/linux/mtd/nand.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 4be8858..991bd8e 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -725,7 +725,16 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) */ static inline int nand_opcode_8bits(unsigned int command) { - return command == NAND_CMD_READID; + switch (command) { + case NAND_CMD_READID: + case NAND_CMD_PARAM: + case NAND_CMD_GET_FEATURES: + case NAND_CMD_SET_FEATURES: + return 1; + default: + break; + } + return 0; }

-- 1.8.5.1.163.gd7aced9

Pekon Gupta

1:41 p.m.

New subject: [U-Boot] [PATCH v4 4/5] mtd: nand: omap: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width

This patch introduces CONFIG_SYS_NAND_DEVICE_WIDTH to specify bus-width of NAND device CONFIG_SYS_NAND_DEVICE_WIDTH == 16: NAND device with x16 bus-width CONFIG_SYS_NAND_DEVICE_WIDTH == 8: NAND device with x8 bus-width

Need for a separate CONFIG_SYS_NAND_xx arise from following requirements: (1) SPL NAND drivers does not have framework to parse ONFI parameter page.

(2) GPMC controller needs to know about the bus-width of device connected to it on board. But as GPMC controller is initialized before the NAND device is probed, and there is no way of re-configuring the GPMC controller based on-chip ONFI parameters. if !defined (CONFIG_SYS_NAND_SELF_INIT) |- board_nand_init() |- nand_scan() |- nand_scan_ident() |- nand_scan_tail()

(3) Non-ONFI compliant devices need some mechanism to specify device bus-width to driver.

diff --git a/doc/README.nand b/doc/README.nand index b91f198..90d857e 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -190,6 +190,15 @@ Configuration Options: This is used by SoC platforms which do not have built-in ELM hardware engine required for BCH ECC correction.

+ CONFIG_SYS_NAND_DEVICE_WIDTH + Specifies bus-width of the default NAND device connected to SoC. + This config is useful for driver which cannot self initialize or + parse ONFI parameter (like SPL drivers), or for supporting non-ONFI + compliant devices. + This config can take following values: + - 8: x8 NAND devices is connected + - 16: x16 NAND device is connected +

Platform specific options ========================= diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 325ebfd..ba7ac2b 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -782,13 +782,18 @@ int board_nand_init(struct nand_chip *nand) nand->priv = &omap_nand_info; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; - /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) - nand->options |= NAND_BUSWIDTH_16; - nand->chip_delay = 100; nand->ecc.layout = &omap_ecclayout;

+ /* configure driver and controller based on NAND device bus-width */ + gpmc_config = readl(&gpmc_cfg->cs[cs].config1); + if (CONFIG_SYS_NAND_DEVICE_WIDTH == 16) { + nand->options |= NAND_BUSWIDTH_16; + writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1); + } else { + nand->options &= ~NAND_BUSWIDTH_16; + writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1); + } /* select ECC scheme */ #if defined(CONFIG_NAND_OMAP_ECCSCHEME) err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ea9e758..8a38cb2 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -229,6 +229,7 @@ #ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index c17327f..0563935 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -245,6 +245,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 4407b45..bc38f40 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -329,6 +329,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"

#define CONFIG_CMD_NAND #define GPMC_NAND_ECC_LP_x8_LAYOUT +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \ "1m(u-boot),1m(u-boot-env)," \ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index aae05e0..bb5dfb9 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -150,6 +150,7 @@ * Board NAND Info. */ #define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 16a00eb..8929bce 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -314,6 +314,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000

/* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0b57421..b31e907 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -422,6 +422,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"

/* Max number of NAND devices */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 - +#define CONFIG_SYS_NAND_DEVICE_WIDTH 16 /* Timeout values (in ticks) */ #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index d56d5b0..8b8583a 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -187,6 +187,7 @@

/* NAND boot config */ #ifdef CONFIG_NAND +#define CONFIG_SYS_NAND_DEVICE_WIDTH 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0d03c75..e4c09ff 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -141,6 +141,7 @@

#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 16 #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 007e27f..66e753d 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -312,6 +312,7 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"

/* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 16 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index da67787..f6cd9b0 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -133,7 +133,7 @@ /* at CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ - +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #ifdef CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index f0fa96e..29de928 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -140,6 +140,7 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 16 #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index fc25966..0a0c77f 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -127,6 +127,7 @@ #define CONFIG_CMD_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 721c4e6..3920671 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -178,6 +178,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 3522c1a..04c4b70 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -249,6 +249,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000

/* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 16 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9c04c23..7dee34e 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -141,6 +141,7 @@

#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 16 /* Environment information */ #define CONFIG_BOOTDELAY 3

diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 80985a2..0a6a456 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -362,6 +362,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000

/* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 8fb87ac..4c5f11a 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -158,6 +158,7 @@ #define CONFIG_NAND_OMAP_ELM #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048

-- 1.8.5.1.163.gd7aced9

Scott Wood

30 Apr 30 Apr

12:55 a.m.

New subject: [U-Boot] [PATCH v4 4/5] mtd: nand: omap: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width

On Mon, 2014-04-28 at 17:11 +0530, Pekon Gupta wrote:

...

CONFIG_SYS_NAND_DEVICE_WIDTH

Specifies bus-width of the default NAND device connected to SoC.

This config is useful for driver which cannot self initialize or

parse ONFI parameter (like SPL drivers), or for supporting non-ONFI

compliant devices.

This config can take following values:

8: x8 NAND devices is connected

16: x16 NAND device is connected

Please list here the drivers that pay attention to this config symbol.

I'm not sure what this has to do with CONFIG_SYS_NAND_SELF_INIT -- or did you mean something different by "self initialize"?

-Scott

Gupta, Pekon

7:12 a.m.

New subject: [U-Boot] [PATCH v4 4/5] mtd: nand: omap: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width

Hi Scott,

...

From: Scott Wood [mailto:scottwood@freescale.com]

...
On Mon, 2014-04-28 at 17:11 +0530, Pekon Gupta wrote:

CONFIG_SYS_NAND_DEVICE_WIDTH

Specifies bus-width of the default NAND device connected to SoC.

This config is useful for driver which cannot self initialize or

parse ONFI parameter (like SPL drivers), or for supporting non-ONFI

compliant devices.

This config can take following values:

8: x8 NAND devices is connected

16: x16 NAND device is connected

Please list here the drivers that pay attention to this config symbol.

Different drivers use different approach. - Some driver like omap_gpmc.c require users to hack their board file and do NAND device-width configurations by themselves. - Others drivers uses some different CONFIG_SYS_NAND_xx symbols which is not documented in doc/README.nand

- atmel_nand.c: uses CONFIG_SYS_NAND_DBW_16 - fsl_ifc_nand.c: depends on configuration done in board file - fsmc_nand.c: CONFIG_SYS_FSMC_NAND_16BIT - mpc5121_nfc.c: depends on configurations done in board file - mxc_nand.c: uses CONFIG_SYS_NAND_BUSWIDTH_16BIT - ndfc.c: uses CONFIG_SYS_NAND_BUSWIDTH_16BIT - tegra_nand.c: ??

I just realize OMAP driver can also _reuse_ CONFIG_SYS_NAND_BUSWIDTH_16BIT instead of adding new config. Is this okay ? I missed it because it wasn't documented.

...

I'm not sure what this has to do with CONFIG_SYS_NAND_SELF_INIT -- or did you mean something different by "self initialize"?

GPMC controller has a configuration bit, which needs to be programmed based on bus-width of the NAND device attached to it. This configuration has to be done at _driver_ probe itself, in board_nand_init().

*Current Implementation* Current implementation of OMAP NAND driver uses nand_init_chip() which calls board_nand_init() *before* any NAND device is scanned. So, it's not possible to do use the information from ONFI PARAMs and re-configure the controller as execution flow never return back to board_nand_init().

------- File: drivers/mtd/nand/nand.c #ifndef CONFIG_SYS_NAND_SELF_INIT static void nand_init_chip(int i) { struct mtd_info *mtd = &nand_info[i]; struct nand_chip *nand = &nand_chip[i]; ulong base_addr = base_address[i]; int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;

if (maxchips < 1) maxchips = 1;

mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;

if (board_nand_init(nand)) <-------- driver initialization happens before return;

if (nand_scan(mtd, maxchips)) <------ device scan (where ONFI params are read) return;

nand_register(i); } #endif ------- Therefore, all the drivers which need to configure controllers *before* the ONFI PARAMs are read from the device, need some or the other CONFIG_NAND_xx or board file hacks to configure their controller. This is the background of this patch.

*Alternative Implementation* An alternate to this was to use "CONFIG_SYS_NAND_SELF_INIT", which gives freedom to board_nand_init() to do device scan as required. And driver can add initialization code in-between the calls to nand_scan_ident() and nand_scan_tail()

Reference: doc/README.nand

if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL)) error out

/* * Insert here any code you wish to run after the chip has been * identified, but before any other I/O is done. */

if (nand_scan_tail(mtd)) error out

- Moving OMAP NAND driver to use CONFIG_SYS_NAND_SELF_INIT as given in alternate implementation, requires some larger changes.

- As SPL code flow does not support ONFI param scanning, so some CONFIG_NAND_xx is required to tell SPL driver about device bus-width.

with regards, pekon

Scott Wood

8:11 p.m.

New subject: [U-Boot] [PATCH v4 4/5] mtd: nand: omap: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width

On Wed, 2014-04-30 at 05:12 +0000, Gupta, Pekon wrote:

...

Hi Scott,

...
From: Scott Wood [mailto:scottwood@freescale.com]

...
On Mon, 2014-04-28 at 17:11 +0530, Pekon Gupta wrote:

CONFIG_SYS_NAND_DEVICE_WIDTH

Specifies bus-width of the default NAND device connected to SoC.

This config is useful for driver which cannot self initialize or

parse ONFI parameter (like SPL drivers), or for supporting non-ONFI

compliant devices.

This config can take following values:

8: x8 NAND devices is connected

16: x16 NAND device is connected

Please list here the drivers that pay attention to this config symbol.

Different drivers use different approach.

Precisely -- that's why I don't want it to look like this is a generic option that all drivers use.

...

Some driver like omap_gpmc.c require users to hack their board file

and do NAND device-width configurations by themselves.

I'd call it configuration rather than hacking. :-)

...

Others drivers uses some different CONFIG_SYS_NAND_xx symbols

which is not documented in doc/README.nand

atmel_nand.c: uses CONFIG_SYS_NAND_DBW_16

fsl_ifc_nand.c: depends on configuration done in board file

fsmc_nand.c: CONFIG_SYS_FSMC_NAND_16BIT

mpc5121_nfc.c: depends on configurations done in board file

mxc_nand.c: uses CONFIG_SYS_NAND_BUSWIDTH_16BIT

ndfc.c: uses CONFIG_SYS_NAND_BUSWIDTH_16BIT

tegra_nand.c: ??

I just realize OMAP driver can also _reuse_ CONFIG_SYS_NAND_BUSWIDTH_16BIT instead of adding new config. Is this okay ? I missed it because it wasn't documented.

Yes, just document it and list the drivers that use it.

-Scott

Pekon Gupta

28 Apr 28 Apr

1:41 p.m.

New subject: [U-Boot] [PATCH v4 5/5] omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT

OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros to configure GPMC controller for x7 or x8 bit device connected to its interface. Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above macros can be completely removed.

Signed-off-by: Pekon Gupta pekon@ti.com --- arch/arm/cpu/armv7/omap3/mem.c | 12 ------------ arch/arm/include/asm/arch-omap3/mem.h | 8 -------- board/compulab/cm_t35/cm_t35.c | 12 ++++++------ include/configs/cm_t335.h | 1 - include/configs/pengwyn.h | 1 - include/configs/tao3530.h | 1 - include/configs/tseries.h | 1 - 7 files changed, 6 insertions(+), 30 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index e649409..1832aff 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -21,17 +21,6 @@ struct gpmc *gpmc_cfg;

#if defined(CONFIG_CMD_NAND) -#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - SMNAND_GPMC_CONFIG1, - SMNAND_GPMC_CONFIG2, - SMNAND_GPMC_CONFIG3, - SMNAND_GPMC_CONFIG4, - SMNAND_GPMC_CONFIG5, - SMNAND_GPMC_CONFIG6, - 0, -}; -#else static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, @@ -40,7 +29,6 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG5, M_NAND_GPMC_CONFIG6, 0 }; -#endif #endif /* CONFIG_CMD_NAND */

#if defined(CONFIG_CMD_ONENAND) diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 1804191..d90fe16 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -353,14 +353,6 @@ enum {

#define GPMC_CS_ENABLE 0x1

-#define SMNAND_GPMC_CONFIG1 0x00000800 -#define SMNAND_GPMC_CONFIG2 0x00141400 -#define SMNAND_GPMC_CONFIG3 0x00141400 -#define SMNAND_GPMC_CONFIG4 0x0F010F01 -#define SMNAND_GPMC_CONFIG5 0x010C1414 -#define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -#define SMNAND_GPMC_CONFIG7 0x00000C44 - #define M_NAND_GPMC_CONFIG1 0x00001800 #define M_NAND_GPMC_CONFIG2 0x00141400 #define M_NAND_GPMC_CONFIG3 0x00141400 diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 00bcf41..0944903 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -54,12 +54,12 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = { };

static u32 gpmc_nand_config[GPMC_MAX_REG] = { - SMNAND_GPMC_CONFIG1, - SMNAND_GPMC_CONFIG2, - SMNAND_GPMC_CONFIG3, - SMNAND_GPMC_CONFIG4, - SMNAND_GPMC_CONFIG5, - SMNAND_GPMC_CONFIG6, + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, 0, };

diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 158cf8f..850f3b0 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -141,7 +141,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000

#define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x8_LAYOUT #define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 0a0c77f..289628a 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -150,7 +150,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000

-#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ "128k(SPL.backup1)," \ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 7dee34e..689a8a3 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -137,7 +137,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT

#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/tseries.h b/include/configs/tseries.h index 4c5f11a..764e3b4 100644 --- a/include/configs/tseries.h +++ b/include/configs/tseries.h @@ -157,7 +157,6 @@ /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ #define CONFIG_NAND_OMAP_ELM #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)

-- 1.8.5.1.163.gd7aced9

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Gupta, Pekon
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