The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x.

[ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ]

Signed-off-by: Chris Packham judge.packham@gmail.com --- See https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a...

I've set the value for ARMADA_3700 and ARMADA_8K to 2GHz. I'm not sure if this is correct but it is the same value that these SoCs would have had when the value was defined in soc.h.

arch/arm/mach-mvebu/Kconfig | 6 ++++++ arch/arm/mach-mvebu/include/mach/soc.h | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 6e8026bde253..7733936be540 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -36,6 +36,12 @@ config ARMADA_8K bool select ARM64

+# Armada PLL frequency (used for NAND clock generation) +config SYS_MVEBU_PLL_CLOCK + int + default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K + default "1000000000" if ARMADA_38X || ARMADA_375 + # Armada XP/38x SoC types... config MV78230 bool diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 731fe65ae4b4..0f69f3341be0 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -31,9 +31,6 @@ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ #endif

-/* Armada XP PLL frequency (used for NAND clock generation) */ -#define CONFIG_SYS_MVEBU_PLL_CLOCK 2000000000 - /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)