[U-Boot] [PATCH 00/18] rockchip: Add support for Bob Chromebook

Simon Glass

10 Jan 2019 10 Jan '19

5:24 a.m.

This series adds basic support for Bob which is based on RK3399. Quite a bit of work remains to get this into fully working condition.

This series is based on the rockchip pinctrl drivers series by David Wu.

Simon Glass (18): lib: Allow using display_buffer() in SPL clk: Improve debug message in clk_set_default_rates() gpio: Use more command-specific enums values gpio: Add a simple GPIO API for SPL rockchip: Add mention of other boards rockchip: Drop note about supporting other SoCs rockchip: Bring in device tree files for rk3399-gru rockchip: Adjust rk3399 device tree to be closer to linux rockchip: evb_rk3399: Tidy up the README rockchip: Clarify docs on SPI writing rockchip: Allow booting from SPI rockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHz rockchip: clk: Add mention of four new clocks rockchip: Tidy up board include-file ordering rockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set env rockchip: Implement spl_gpio in the GPIO driver rockchip: gru: Add extra device-tree settings rockchip: Add support for chromebook_bob

arch/arm/dts/rk3399-gru-bob.dts | 80 + arch/arm/dts/rk3399-gru-chromebook.dtsi | 398 +++++ arch/arm/dts/rk3399-gru-kevin.dts | 309 ++++ arch/arm/dts/rk3399-gru.dtsi | 844 +++++++++ arch/arm/dts/rk3399-op1-opp.dtsi | 141 ++ .../rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi | 1542 +++++++++++++++++ arch/arm/dts/rk3399.dtsi | 432 ++++- arch/arm/include/asm/arch-rockchip/gpio.h | 29 + .../arm/include/asm/arch-rockchip/sys_proto.h | 3 + arch/arm/mach-rockchip/rk3036-board.c | 2 +- arch/arm/mach-rockchip/rk3188-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3188-board.c | 2 +- arch/arm/mach-rockchip/rk322x-board.c | 2 +- arch/arm/mach-rockchip/rk3368-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3368-board-tpl.c | 4 +- arch/arm/mach-rockchip/rk3399-board-spl.c | 49 +- arch/arm/mach-rockchip/rk3399/Kconfig | 10 + arch/arm/mach-rockchip/spl-boot-order.c | 3 + board/google/gru/Kconfig | 15 + board/google/gru/MAINTAINERS | 6 + board/google/gru/Makefile | 5 + board/google/gru/gru.c | 16 + board/rockchip/evb_rk3399/README | 33 +- cmd/gpio.c | 37 +- configs/chromebook_bob_defconfig | 100 ++ doc/README.rockchip | 58 +- drivers/clk/clk-uclass.c | 4 +- drivers/clk/rockchip/clk_rk3399.c | 12 + drivers/gpio/rk_gpio.c | 46 + include/configs/gru.h | 18 + include/configs/rk3399_common.h | 5 + include/spl_gpio.h | 62 + lib/display_options.c | 4 +- 33 files changed, 4159 insertions(+), 116 deletions(-) create mode 100644 arch/arm/dts/rk3399-gru-bob.dts create mode 100644 arch/arm/dts/rk3399-gru-chromebook.dtsi create mode 100644 arch/arm/dts/rk3399-gru-kevin.dts create mode 100644 arch/arm/dts/rk3399-gru.dtsi create mode 100644 arch/arm/dts/rk3399-op1-opp.dtsi create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi create mode 100644 board/google/gru/Kconfig create mode 100644 board/google/gru/MAINTAINERS create mode 100644 board/google/gru/Makefile create mode 100644 board/google/gru/gru.c create mode 100644 configs/chromebook_bob_defconfig create mode 100644 include/configs/gru.h create mode 100644 include/spl_gpio.h

-- 2.20.1.97.g81188d93c3-goog

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Simon Glass

10 Jan 10 Jan

5:24 a.m.

New subject: [U-Boot] [PATCH 01/18] lib: Allow using display_buffer() in SPL

At present this function uses printf() format strings that are not supported in SPL, so the output just consists of %llx strings on 64-bit. machines. Fix this by adding a special case.

Signed-off-by: Simon Glass sjg@chromium.org ---

lib/display_options.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/display_options.c b/lib/display_options.c index 32849821f4..af1802ef99 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -174,7 +174,9 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, x = lb.us[i] = *(volatile uint16_t *)data; else x = lb.uc[i] = *(volatile uint8_t *)data; -#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA +#if defined(CONFIG_SPL_BUILD) + printf(" %x", (uint)x); +#elif defined(CONFIG_SYS_SUPPORT_64BIT_DATA) printf(" %0*llx", width * 2, (long long)x); #else printf(" %0*x", width * 2, x);

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 02/18] clk: Improve debug message in clk_set_default_rates()

It is helpful to print the clock number as well as the index, so that this can be looked up in the binding file. Update the debug() statement to do this.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/clk/clk-uclass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 6d7a514006..844b87cc33 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -228,8 +228,8 @@ static int clk_set_default_rates(struct udevice *dev)

ret = clk_set_rate(&clk, rates[index]); if (ret < 0) { - debug("%s: failed to set rate on clock %d for %s\n", - __func__, index, dev_read_name(dev)); + debug("%s: failed to set rate on clock index %d (%ld) for %s\n", + __func__, index, clk.id, dev_read_name(dev)); break; } }

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 03/18] gpio: Use more command-specific enums values

At present this file uses GPIO_OUTPUT and GPIO_INPUT as its sub-command values. These are pretty generic names. Add a 'C' suffix to avoid possible conflicts.

Signed-off-by: Simon Glass sjg@chromium.org ---

cmd/gpio.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/cmd/gpio.c b/cmd/gpio.c index ecdc453918..77d2573562 100644 --- a/cmd/gpio.c +++ b/cmd/gpio.c @@ -18,10 +18,10 @@ __weak int name_to_gpio(const char *name) }

enum gpio_cmd { - GPIO_INPUT, - GPIO_SET, - GPIO_CLEAR, - GPIO_TOGGLE, + GPIOC_INPUT, + GPIOC_SET, + GPIOC_CLEAR, + GPIOC_TOGGLE, };

#if defined(CONFIG_DM_GPIO) && !defined(gpio_status) @@ -158,11 +158,20 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

/* parse the behavior */ switch (*str_cmd) { - case 'i': sub_cmd = GPIO_INPUT; break; - case 's': sub_cmd = GPIO_SET; break; - case 'c': sub_cmd = GPIO_CLEAR; break; - case 't': sub_cmd = GPIO_TOGGLE; break; - default: goto show_usage; + case 'i': + sub_cmd = GPIOC_INPUT; + break; + case 's': + sub_cmd = GPIOC_SET; + break; + case 'c': + sub_cmd = GPIOC_CLEAR; + break; + case 't': + sub_cmd = GPIOC_TOGGLE; + break; + default: + goto show_usage; }

#if defined(CONFIG_DM_GPIO) @@ -192,18 +201,18 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) }

/* finally, let's do it: set direction and exec command */ - if (sub_cmd == GPIO_INPUT) { + if (sub_cmd == GPIOC_INPUT) { gpio_direction_input(gpio); value = gpio_get_value(gpio); } else { switch (sub_cmd) { - case GPIO_SET: + case GPIOC_SET: value = 1; break; - case GPIO_CLEAR: + case GPIOC_CLEAR: value = 0; break; - case GPIO_TOGGLE: + case GPIOC_TOGGLE: value = gpio_get_value(gpio); if (!IS_ERR_VALUE(value)) value = !value; @@ -218,7 +227,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("unknown (ret=%d)\n", value); else printf("%d\n", value); - if (sub_cmd != GPIO_INPUT && !IS_ERR_VALUE(value)) { + if (sub_cmd != GPIOC_INPUT && !IS_ERR_VALUE(value)) { int nval = gpio_get_value(gpio);

if (IS_ERR_VALUE(nval))

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 04/18] gpio: Add a simple GPIO API for SPL

In space-constrained environments or before driver model is available, it is sometimes necessary to set GPIO values. Add an SPL API for this, to allow early board code to change GPIOs. The caller must provide the register address, so that the drivers can be fairly generic.

This API can be implemented by GPIO drivers, behind a suitable guard, like #ifdef CONFIG_SPL_BUILD.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/spl_gpio.h | 62 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 include/spl_gpio.h

diff --git a/include/spl_gpio.h b/include/spl_gpio.h new file mode 100644 index 0000000000..e410e62914 --- /dev/null +++ b/include/spl_gpio.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Simple GPIO access from SPL. This only supports a single GPIO space, + * typically the SoC GPIO banks. + * + * Copyright 2018 Google LLC + */ + +#ifndef __SPL_GPIO_H +#define __SPL_GPIO_H + +#include <asm/gpio.h> + +/* + * The functions listed here should be implemented in the SoC GPIO driver. + * They correspond to the normal GPIO API (asm-generic/gpio.h). The GPIO + * number is encoded in an unsigned int by an SoC-specific means. Pull + * values are also SoC-specific. + * + * This API should only be used in TPL/SPL where GPIO access is needed but + * driver model is not available (yet) or adds too much overhead. + * + * The caller must supply the GPIO register base since this information is + * often specific to a particular SoC generation. This allows the GPIO + * code to be fairly generic. + * + * Only a single implementation of each of these functions can be provided. + * + * The 'gpio' value can include both a bank and a GPIO number, if desired. The + * encoding is SoC-specific. + */ + +/** + * spl_gpio_set_pull() - Set the pull up/down state of a GPIO + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @pull: Pull value (SoC-specific) + * @return return 0 if OK, -ve on error + */ +int spl_gpio_set_pull(void *regs, uint gpio, int pull); + +/** + * spl_gpio_output() - Set a GPIO as an output + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @value: 0 to set the output low, 1 to set it high + * @return return 0 if OK, -ve on error + */ +int spl_gpio_output(void *regs, uint gpio, int value); + +/** + * spl_gpio_input() - Set a GPIO as an input + * + * @regs: Pointer to GPIO registers + * @gpio: GPIO to adjust (SoC-specific) + * @return return 0 if OK, -ve on error + */ +int spl_gpio_input(void *regs, uint gpio); + +#endif /* __SPL_GPIO_H */

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 05/18] rockchip: Add mention of other boards

At present some Rockchip SoCs and boards are not mentioned in the README. So that people can see which SoCs are supported, expand the list to include everything.

Signed-off-by: Simon Glass sjg@chromium.org ---

doc/README.rockchip | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip index 51b00a9d85..2b24ce8c06 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -34,23 +34,62 @@ You will need: Building ========

-At present nine RK3288 boards are supported: +At present 12 RK3288 boards are supported:

- EVB RK3288 - use evb-rk3288 configuration - Fennec RK3288 - use fennec-rk3288 configuration - Firefly RK3288 - use firefly-rk3288 configuration - Hisense Chromebook - use chromebook_jerry configuration + - Asus C100P Chromebook - use chromebook_minnie configuration + - Asus Chromebit - use chromebook_mickey configuration - MiQi RK3288 - use miqi-rk3288 configuration - phyCORE-RK3288 RDK - use phycore-rk3288 configuration - PopMetal RK3288 - use popmetal-rk3288 configuration - Radxa Rock 2 - use rock2 configuration - Tinker RK3288 - use tinker-rk3288 configuration + - Vyasa RK3288 - use vyasa-rk3288 configuration

-Two RK3036 board are supported: +Two RK3036 boards are supported:

- EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration

+One RK3328 board is supported: + + - EVB RK3328 + +Five RK3399 boards are supported (aarch64): + + - EBV RK3399 - use evb_rk3399 configuration + - Firefly RK3399 - use the same evb_rk3399 configuration + - Puma - use puma_rk3399 configuration + - Ficus - use ficus-rk3399 configuration + - Rock960 (Vamrs) - use rock960-rk3399 configuration + +Four RK3368 boards are supported: + + - Sheep - use sheep-rk3368 configuration + - Lion - use lion-rk3368 configuration + - Geekbox - use geekbox configuration + - EVB PX5 - use evb-px5 configuration + +One RK3128 board is supported: + + - EVB RK3128 - use evb-rk3128 configuration + +One RK3229 board is supported: + + - EVB RK3229 - use evb-rk3229 configuration + +One RV1108 board is supported: + + - Elgin R1 - use elgin-rv1108 configuration + +One RV3188 baord is supported: + + - Raxda Rock - use rock configuration + + For example:

CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all

-- 2.20.1.97.g81188d93c3-goog

Mark Kettenis

11 Jan 11 Jan

3:29 p.m.

New subject: [U-Boot] [PATCH 05/18] rockchip: Add mention of other boards

...

Date: Wed, 9 Jan 2019 21:24:44 -0700 From: Simon Glass sjg@chromium.org

At present some Rockchip SoCs and boards are not mentioned in the README. So that people can see which SoCs are supported, expand the list to include everything.

Signed-off-by: Simon Glass sjg@chromium.org

doc/README.rockchip | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip index 51b00a9d85..2b24ce8c06 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -34,23 +34,62 @@ You will need: Building ========

-At present nine RK3288 boards are supported: +At present 12 RK3288 boards are supported:
- EVB RK3288 - use evb-rk3288 configuration
- Fennec RK3288 - use fennec-rk3288 configuration
- Firefly RK3288 - use firefly-rk3288 configuration
- Hisense Chromebook - use chromebook_jerry configuration
Asus C100P Chromebook - use chromebook_minnie configuration

Asus Chromebit - use chromebook_mickey configuration

MiQi RK3288 - use miqi-rk3288 configuration

phyCORE-RK3288 RDK - use phycore-rk3288 configuration

PopMetal RK3288 - use popmetal-rk3288 configuration

Radxa Rock 2 - use rock2 configuration

Tinker RK3288 - use tinker-rk3288 configuration

Vyasa RK3288 - use vyasa-rk3288 configuration

-Two RK3036 board are supported: +Two RK3036 boards are supported:
- EVB RK3036 - use evb-rk3036 configuration
- Kylin - use kylin_rk3036 configuration
+One RK3328 board is supported:

EVB RK3328

+Five RK3399 boards are supported (aarch64):

EBV RK3399 - use evb_rk3399 configuration

Firefly RK3399 - use the same evb_rk3399 configuration

That should be firefly-rk3399_defconfig

Andy Yan

21 Jan 21 Jan

2:04 a.m.

New subject: [U-Boot] [PATCH 05/18] rockchip: Add mention of other boards

Hi Simon:

Simon Glass sjg@chromium.org 于2019年1月10日周四下午12:30写道：

...

At present some Rockchip SoCs and boards are not mentioned in the README. So that people can see which SoCs are supported, expand the list to include everything.

Signed-off-by: Simon Glass sjg@chromium.org

doc/README.rockchip | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip index 51b00a9d85..2b24ce8c06 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -34,23 +34,62 @@ You will need: Building ========

-At present nine RK3288 boards are supported: +At present 12 RK3288 boards are supported:
- EVB RK3288 - use evb-rk3288 configuration
- Fennec RK3288 - use fennec-rk3288 configuration
- Firefly RK3288 - use firefly-rk3288 configuration
- Hisense Chromebook - use chromebook_jerry configuration
Asus C100P Chromebook - use chromebook_minnie configuration

Asus Chromebit - use chromebook_mickey configuration

MiQi RK3288 - use miqi-rk3288 configuration

phyCORE-RK3288 RDK - use phycore-rk3288 configuration

PopMetal RK3288 - use popmetal-rk3288 configuration

Radxa Rock 2 - use rock2 configuration

Tinker RK3288 - use tinker-rk3288 configuration

Vyasa RK3288 - use vyasa-rk3288 configuration

-Two RK3036 board are supported: +Two RK3036 boards are supported:
- EVB RK3036 - use evb-rk3036 configuration
- Kylin - use kylin_rk3036 configuration
+One RK3328 board is supported:

EVB RK3328

+Five RK3399 boards are supported (aarch64):

EBV RK3399 - use evb_rk3399 configuration

Firefly RK3399 - use the same evb_rk3399 configuration

Puma - use puma_rk3399 configuration

Ficus - use ficus-rk3399 configuration

Rock960 (Vamrs) - use rock960-rk3399 configuration

+Four RK3368 boards are supported:

Sheep - use sheep-rk3368 configuration

Lion - use lion-rk3368 configuration

Geekbox - use geekbox configuration

EVB PX5 - use evb-px5 configuration

+One RK3128 board is supported:

EVB RK3128 - use evb-rk3128 configuration

+One RK3229 board is supported:

EVB RK3229 - use evb-rk3229 configuration

+One RV1108 board is supported:

Elgin R1 - use elgin-rv1108 configuration

We also have an EVB for RV1108, see board/rockchip/evb_rv1108/README

...

+One RV3188 baord is supported:

Raxda Rock - use rock configuration

For example:
CROSS_COMPILE=arm-linux-gnueabi- make O=firefly
firefly-rk3288_defconfig all

2.20.1.97.g81188d93c3-goog

U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

Simon Glass

10 Jan 10 Jan

5:24 a.m.

New subject: [U-Boot] [PATCH 06/18] rockchip: Drop note about supporting other SoCs

Quite a wide range of Rockchip SoCs are supported in mainline U-Boot now, so drop the comment about needing to add more.

Signed-off-by: Simon Glass sjg@chromium.org ---

doc/README.rockchip | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip index 2b24ce8c06..a45b8a97b7 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -6,13 +6,7 @@ U-Boot on Rockchip ==================

-There are several repositories available with versions of U-Boot that support -many Rockchip devices [1] [2]. - -The current mainline support is experimental only and is not useful for -anything. It should provide a base on which to build. - -So far only support for the RK3288 and RK3036 is provided. +A wide range of Rockchip SoCs are supported in mainline U-Boot

Prerequisites @@ -303,7 +297,6 @@ Immediate priorities are: - USB device - Run CPU at full speed (code exists but we only see ~60 DMIPS maximum) - NAND flash -- Support for other Rockchip parts - Boot U-Boot proper over USB OTG (at present only SPL works)

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 07/18] rockchip: Bring in device tree files for rk3399-gru

Bring in these files from Linux v4.20.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/dts/rk3399-gru-bob.dts | 79 +++ arch/arm/dts/rk3399-gru-chromebook.dtsi | 397 +++++++++++ arch/arm/dts/rk3399-gru-kevin.dts | 309 +++++++++ arch/arm/dts/rk3399-gru.dtsi | 831 ++++++++++++++++++++++++ arch/arm/dts/rk3399-op1-opp.dtsi | 141 ++++ 5 files changed, 1757 insertions(+) create mode 100644 arch/arm/dts/rk3399-gru-bob.dts create mode 100644 arch/arm/dts/rk3399-gru-chromebook.dtsi create mode 100644 arch/arm/dts/rk3399-gru-kevin.dts create mode 100644 arch/arm/dts/rk3399-gru.dtsi create mode 100644 arch/arm/dts/rk3399-op1-opp.dtsi

diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts new file mode 100644 index 0000000000..1ee0dc0d9f --- /dev/null +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Bob Rev 4+ board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; +#include "rk3399-gru-chromebook.dtsi" + +/ { + model = "Google Bob"; + compatible = "google,bob-rev13", "google,bob-rev12", + "google,bob-rev11", "google,bob-rev10", + "google,bob-rev9", "google,bob-rev8", + "google,bob-rev7", "google,bob-rev6", + "google,bob-rev5", "google,bob-rev4", + "google,bob", "google,gru", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "boe,nv101wxmn51", "simple-panel"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&ap_i2c_ts { + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l &touch_reset_l>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; +}; + +&ap_i2c_tp { + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + wakeup-source; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&spi0 { + status = "okay"; +}; + +&pinctrl { + tpm { + h1_int_od_l: h1-int-od-l { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi new file mode 100644 index 0000000000..ff81dfda3b --- /dev/null +++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Chromebook shared properties + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/ { + pp900_ap: pp900-ap { + compatible = "regulator-fixed"; + regulator-name = "pp900_ap"; + + /* EC turns on w/ pp900_ap_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + /* EC turns on w/ pp900_usb_en */ + pp900_usb: pp900-ap { + }; + + /* EC turns on w/ pp900_pcie_en */ + pp900_pcie: pp900-ap { + }; + + pp3000: pp3000 { + compatible = "regulator-fixed"; + regulator-name = "pp3000"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3000_en>; + + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_centerlogic_pwm"; + + pwms = <&pwm3 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + }; + + ppvar_centerlogic: ppvar-centerlogic { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_centerlogic"; + + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + + ctrl-supply = <&ppvar_centerlogic_pwm>; + ctrl-voltage-range = <799434 1049925>; + + regulator-settling-time-up-us = <378>; + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; + }; + + /* Schematics call this PPVAR even though it's fixed */ + ppvar_logic: ppvar-logic { + compatible = "regulator-fixed"; + regulator-name = "ppvar_logic"; + + /* EC turns on w/ ppvar_logic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800_audio: pp1800-audio { + compatible = "regulator-fixed"; + regulator-name = "pp1800_audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_audio_en>; + + enable-active-high; + gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp1800>; + }; + + /* gpio is shared with pp3300_wifi_bt */ + pp1800_pcie: pp1800-pcie { + compatible = "regulator-fixed"; + regulator-name = "pp1800_pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_pd_l>; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Need to wait 1ms + ramp-up time before we can power on WiFi. + * This has been approximated as 8ms total. + */ + regulator-enable-ramp-delay = <8000>; + + vin-supply = <&pp1800>; + }; + + /* Always on; plain and simple */ + pp3000_ap: pp3000_emmc: pp3000 { + }; + + pp1500_ap_io: pp1500-ap-io { + compatible = "regulator-fixed"; + regulator-name = "pp1500_ap_io"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1500_en>; + + enable-active-high; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&pp1800>; + }; + + pp3300_disp: pp3300-disp { + compatible = "regulator-fixed"; + regulator-name = "pp3300_disp"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_disp_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <2000>; + vin-supply = <&pp3300>; + }; + + /* EC turns on w/ pp3300_usb_en_l */ + pp3300_usb: pp3300 { + }; + + /* gpio is shared with pp1800_pcie and pinctrl is set there */ + pp3300_wifi_bt: pp3300-wifi-bt { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wifi_bt"; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3300>; + }; + + /* + * This is a bit of a hack. The WiFi module should be reset at least + * 1ms after its regulators have ramped up (max rampup time is ~7ms). + * With some stretching of the imagination, we can call the 1.8V + * regulator a supply. + */ + wlan_pd_n: wlan-pd-n { + compatible = "regulator-fixed"; + regulator-name = "wlan_pd_n"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_reset_l>; + + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp1800_pcie>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 + 45 46 47 48 49 50 51 52 53 54 55 56 57 58 + 59 60 61 62 63 64 65 66 67 68 69 70 71 72 + 73 74 75 76 77 78 79 80 81 82 83 84 85 86 + 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; + default-brightness-level = <51>; + enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + power-supply = <&pp3300_disp>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwm-delay-us = <10000>; + }; +}; + +&ppvar_bigcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_litcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_gpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>, <&usbc_extcon1>; +}; + +&edp { + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +ap_i2c_mic: &i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + headsetcodec: rt5514@57 { + compatible = "realtek,rt5514"; + reg = <0x57>; + realtek,dmic-init-delay-ms = <20>; + }; +}; + +ap_i2c_tp: &i2c5 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* + * Note strange pullup enable. Apparently this avoids leakage but + * still allows us to get nice 4.7K pullups for high speed i2c + * transfers. Basically we want the pullup on whenever the ap is + * alive, so the "en" pin just gets set to output high. + */ + pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; +}; + +&cros_ec { + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + usbc_extcon1: extcon@1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + + #extcon-cells = <0>; + }; +}; + +&sound { + rockchip,codec = <&max98357a &headsetcodec + &codec &wacky_spi_audio &cdn_dp>; +}; + +&spi2 { + wacky_spi_audio: spi2@0 { + compatible = "realtek,rt5514"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mic_int>; + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + wakeup-source; + }; +}; + +&pci_rootport { + mvl_wifi: wifi@0,0 { + compatible = "pci1b4b,2b42"; + reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 + 0x83010000 0x0 0x00100000 0x0 0x00100000>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_host_wake_l>; + wakeup-source; + }; +}; + +&tcphy1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&u2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&pinctrl { + discrete-regulators { + pp1500_en: pp1500-en { + rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp1800_audio_en: pp1800-audio-en { + rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + + pp3000_en: pp3000-en { + rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp3300_disp_en: pp3300-disp-en { + rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + wlan_module_pd_l: wlan-module-pd-l { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + }; +}; + +&wifi { + wifi_perst_l: wifi-perst-l { + rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; +}; diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts new file mode 100644 index 0000000000..2cc7c47d6a --- /dev/null +++ b/arch/arm/dts/rk3399-gru-kevin.dts @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Kevin Rev 6+ board device tree source + * + * Copyright 2016-2017 Google, Inc + */ + +/dts-v1/; +#include "rk3399-gru-chromebook.dtsi" +#include <dt-bindings/input/linux-event-codes.h> + +/* + * Kevin-specific things + * + * Things in this section should use names from Kevin schematic since no + * equivalent exists in Gru schematic. If referring to signals that exist + * in Gru we use the Gru names, though. Confusing enough for you? + */ +/ { + model = "Google Kevin"; + compatible = "google,kevin-rev15", "google,kevin-rev14", + "google,kevin-rev13", "google,kevin-rev12", + "google,kevin-rev11", "google,kevin-rev10", + "google,kevin-rev9", "google,kevin-rev8", + "google,kevin-rev7", "google,kevin-rev6", + "google,kevin", "google,gru", "rockchip,rk3399"; + + /* Power tree */ + + p3_3v_dig: p3-3v-dig { + compatible = "regulator-fixed"; + regulator-name = "p3.3v_dig"; + pinctrl-names = "default"; + pinctrl-0 = <&cpu3_pen_pwr_en>; + + enable-active-high; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300>; + }; + + edp_panel: edp-panel { + compatible = "sharp,lq123p1jx31", "simple-panel"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <25500>; + pulldown-ohm = <0>; + io-channels = <&saradc 2>; + #thermal-sensor-cells = <0>; + }; + + thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <25500>; + pulldown-ohm = <0>; + io-channels = <&saradc 3>; + #thermal-sensor-cells = <0>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 1>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; + + pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + linux,code = <SW_PEN_INSERTED>; + linux,input-type = <EV_SW>; + wakeup-source; + }; +}; + +&thermal_zones { + bigcpu_reg_thermal: bigcpu-reg-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermistor_ppvar_bigcpu 0>; + sustainable-power = <4000>; + + ppvar_bigcpu_trips: trips { + ppvar_bigcpu_on: ppvar-bigcpu-on { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_bigcpu_alert: ppvar-bigcpu-alert { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_bigcpu_crit: ppvar-bigcpu-crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&ppvar_bigcpu_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&ppvar_bigcpu_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + litcpu_reg_thermal: litcpu-reg-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermistor_ppvar_litcpu 0>; + sustainable-power = <4000>; + + ppvar_litcpu_trips: trips { + ppvar_litcpu_on: ppvar-litcpu-on { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_litcpu_alert: ppvar-litcpu-alert { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_litcpu_crit: ppvar-litcpu-crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; +}; + +ap_i2c_tpm: &i2c0 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +ap_i2c_dig: &i2c2 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + digitizer: digitizer@9 { + /* wacom,w9013 */ + compatible = "hid-over-i2c"; + reg = <0x9>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>; + + vdd-supply = <&p3_3v_dig>; + post-power-on-delay-ms = <100>; + + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x1>; + }; +}; + +/* Adjustments to things in the gru baseboard */ + +&ap_i2c_tp { + trackpad@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + linux,gpio-keymap = <KEY_RESERVED + KEY_RESERVED + KEY_RESERVED + BTN_LEFT>; + wakeup-source; + }; +}; + +&ap_i2c_ts { + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ppvar_bigcpu_pwm { + regulator-min-microvolt = <798674>; + regulator-max-microvolt = <1302172>; +}; + +&ppvar_bigcpu { + regulator-min-microvolt = <798674>; + regulator-max-microvolt = <1302172>; + ctrl-voltage-range = <798674 1302172>; +}; + +&ppvar_litcpu_pwm { + regulator-min-microvolt = <799065>; + regulator-max-microvolt = <1303738>; +}; + +&ppvar_litcpu { + regulator-min-microvolt = <799065>; + regulator-max-microvolt = <1303738>; + ctrl-voltage-range = <799065 1303738>; +}; + +&ppvar_gpu_pwm { + regulator-min-microvolt = <785782>; + regulator-max-microvolt = <1217729>; +}; + +&ppvar_gpu { + regulator-min-microvolt = <785782>; + regulator-max-microvolt = <1217729>; + ctrl-voltage-range = <785782 1217729>; +}; + +&ppvar_centerlogic_pwm { + regulator-min-microvolt = <800069>; + regulator-max-microvolt = <1049692>; +}; + +&ppvar_centerlogic { + regulator-min-microvolt = <800069>; + regulator-max-microvolt = <1049692>; + ctrl-voltage-range = <800069 1049692>; +}; + +&saradc { + status = "okay"; + vref-supply = <&pp1800_ap_io>; +}; + +&mvl_wifi { + marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */ +}; + +&pinctrl { + digitizer { + /* Has external pullup */ + cpu1_dig_irq_l: cpu1-dig-irq-l { + rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* Has external pullup */ + cpu1_dig_pdct_l: cpu1-dig-pdct-l { + rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + discrete-regulators { + cpu3_pen_pwr_en: cpu3-pen-pwr-en { + rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + cpu1_pen_eject: cpu1-pen-eject { + rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi new file mode 100644 index 0000000000..7cc9b2642b --- /dev/null +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -0,0 +1,831 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru (and derivatives) board device tree source + * + * Copyright 2016-2017 Google, Inc + */ + +#include <dt-bindings/input/input.h> +#include "rk3399.dtsi" +#include "rk3399-op1-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + /* + * Power Tree + * + * In general an attempt is made to include all rails called out by + * the schematic as long as those rails interact in some way with + * the AP. AKA: + * - Rails that only connect to the EC (or devices that the EC talks to) + * are not included. + * - Rails _are_ included if the rails go to the AP even if the AP + * doesn't currently care about them / they are always on. The idea + * here is that it makes it easier to map to the schematic or extend + * later. + * + * If two rails are substantially the same from the AP's point of + * view, though, we won't create a full fixed regulator. We'll just + * put the child rail as an alias of the parent rail. Sometimes rails + * look the same to the AP because one of these is true: + * - The EC controls the enable and the EC always enables a rail as + * long as the AP is running. + * - The rails are actually connected to each other by a jumper and + * the distinction is just there to add clarity/flexibility to the + * schematic. + */ + + ppvar_sys: ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + pp1200_lpddr: pp1200-lpddr { + compatible = "regulator-fixed"; + regulator-name = "pp1200_lpddr"; + + /* EC turns on w/ lpddr_pwr_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800: pp1800 { + compatible = "regulator-fixed"; + regulator-name = "pp1800"; + + /* Always on when ppvar_sys shows power good */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300: pp3300 { + compatible = "regulator-fixed"; + regulator-name = "pp3300"; + + /* Always on; plain and simple */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&ppvar_sys>; + }; + + pp5000: pp5000 { + compatible = "regulator-fixed"; + regulator-name = "pp5000"; + + /* EC turns on w/ pp5000_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_bigcpu_pwm"; + + pwms = <&pwm1 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800107>; + regulator-max-microvolt = <1302232>; + }; + + ppvar_bigcpu: ppvar-bigcpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_bigcpu"; + + regulator-min-microvolt = <800107>; + regulator-max-microvolt = <1302232>; + + ctrl-supply = <&ppvar_bigcpu_pwm>; + ctrl-voltage-range = <800107 1302232>; + + regulator-settling-time-up-us = <322>; + }; + + ppvar_litcpu_pwm: ppvar-litcpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_litcpu_pwm"; + + pwms = <&pwm2 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <797743>; + regulator-max-microvolt = <1307837>; + }; + + ppvar_litcpu: ppvar-litcpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_litcpu"; + + regulator-min-microvolt = <797743>; + regulator-max-microvolt = <1307837>; + + ctrl-supply = <&ppvar_litcpu_pwm>; + ctrl-voltage-range = <797743 1307837>; + + regulator-settling-time-up-us = <384>; + }; + + ppvar_gpu_pwm: ppvar-gpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_gpu_pwm"; + + pwms = <&pwm0 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <786384>; + regulator-max-microvolt = <1217747>; + }; + + ppvar_gpu: ppvar-gpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_gpu"; + + regulator-min-microvolt = <786384>; + regulator-max-microvolt = <1217747>; + + ctrl-supply = <&ppvar_gpu_pwm>; + ctrl-voltage-range = <786384 1217747>; + + regulator-settling-time-up-us = <390>; + }; + + /* EC turns on w/ pp900_ddrpll_en */ + pp900_ddrpll: pp900-ap { + }; + + /* EC turns on w/ pp900_pll_en */ + pp900_pll: pp900-ap { + }; + + /* EC turns on w/ pp900_pmu_en */ + pp900_pmu: pp900-ap { + }; + + /* EC turns on w/ pp1800_s0_en_l */ + pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { + }; + + /* EC turns on w/ pp1800_avdd_en_l */ + pp1800_avdd: pp1800 { + }; + + /* EC turns on w/ pp1800_lid_en_l */ + pp1800_lid: pp1800_mic: pp1800 { + }; + + /* EC turns on w/ lpddr_pwr_en */ + pp1800_lpddr: pp1800 { + }; + + /* EC turns on w/ pp1800_pmu_en_l */ + pp1800_pmu: pp1800 { + }; + + /* EC turns on w/ pp1800_usb_en_l */ + pp1800_usb: pp1800 { + }; + + pp3000_sd_slot: pp3000-sd-slot { + compatible = "regulator-fixed"; + regulator-name = "pp3000_sd_slot"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_slot_pwr_en>; + + enable-active-high; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3000>; + }; + + /* + * Technically, this is a small abuse of 'regulator-gpio'; this + * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are + * always on though, so it is sufficient to simply control the mux + * here. + */ + ppvar_sd_card_io: ppvar-sd-card-io { + compatible = "regulator-gpio"; + regulator-name = "ppvar_sd_card_io"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; + + enable-active-high; + enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1 + 3000000 0x0>; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + /* EC turns on w/ pp3300_trackpad_en_l */ + pp3300_trackpad: pp3300-trackpad { + }; + + /* EC turns on w/ usb_a_en */ + pp5000_usb_a_vbus: pp5000 { + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + + wake_on_bt: wake-on-bt { + label = "Wake-on-Bluetooth"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + max98357a: max98357a { + compatible = "maxim,max98357a"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmode_en>; + sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sdmode-delay = <2>; + #sound-dai-cells = <0>; + status = "okay"; + }; + + sound: sound { + compatible = "rockchip,rk3399-gru-sound"; + rockchip,cpu = <&i2s0 &i2s2>; + }; +}; + +&cdn_dp { + status = "okay"; +}; + +/* + * Set some suspend operating points to avoid OVP in suspend + * + * When we go into S3 ARM Trusted Firmware will transition our PWM regulators + * from wherever they're at back to the "default" operating point (whatever + * voltage we get when we set the PWM pins to "input"). + * + * This quick transition under light load has the possibility to trigger the + * regulator "over voltage protection" (OVP). + * + * To make extra certain that we don't hit this OVP at suspend time, we'll + * transition to a voltage that's much closer to the default (~1.0 V) so that + * there will not be a big jump. Technically we only need to get within 200 mV + * of the default voltage, but the speed here should be fast enough and we need + * suspend/resume to be rock solid. + */ + +&cluster0_opp { + opp05 { + opp-suspend; + }; +}; + +&cluster1_opp { + opp06 { + opp-suspend; + }; +}; + +&cpu_l0 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l1 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l2 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l3 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_b0 { + cpu-supply = <&ppvar_bigcpu>; +}; + +&cpu_b1 { + cpu-supply = <&ppvar_bigcpu>; +}; + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; + assigned-clock-rates = + <600000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, <800000000>, + <100000000>, <50000000>, + <400000000>, <400000000>, + <200000000>, + <200000000>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&ppvar_gpu>; + status = "okay"; +}; + +ap_i2c_ts: &i2c3 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; +}; + +ap_i2c_audio: &i2c8 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + codec: da7219@1a { + compatible = "dlg,da7219"; + reg = <0x1a>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + dlg,micbias-lvl = <2600>; + dlg,mic-amp-in-sel = "diff"; + pinctrl-names = "default"; + pinctrl-0 = <&headset_int_l>; + VDD-supply = <&pp1800>; + VDDMIC-supply = <&pp3300>; + VDDIO-supply = <&pp1800>; + + da7219_aad { + dlg,adc-1bit-rpt = <1>; + dlg,btn-avg = <4>; + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; + dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-rem-deb = <1>; + + dlg,a-d-btn-thr = <0xa>; + dlg,d-b-btn-thr = <0x16>; + dlg,b-c-btn-thr = <0x21>; + dlg,c-mic-btn-thr = <0x3E>; + }; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ + bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ + gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ + sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ +}; + +&pcie0 { + status = "okay"; + + ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; + vpcie3v3-supply = <&pp3300_wifi_bt>; + vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ + vpcie0v9-supply = <&pp900_pcie>; + + pci_rootport: pcie@0,0 { + reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + /* + * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the + * same (or nearly the same) performance for all eMMC that are intended + * to be used. + */ + assigned-clock-rates = <150000000>; + + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + status = "okay"; + + /* + * Note: configure "sdmmc_cd" as card detect even though it's actually + * hooked to ground. Because we specified "cd-gpios" below dw_mmc + * should be ignoring card detect anyway. Specifying the pin as + * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) + * turned on that the system will still make sure the port is + * configured as SDMMC and not JTAG. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio + &sdmmc_bus4>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&pp3000_sd_slot>; + vqmmc-supply = <&ppvar_sd_card_io>; +}; + +&spi1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&spi1_sleep>; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + }; +}; + +&spi2 { + status = "okay"; +}; + +&spi5 { + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_ap_int_l>; + spi-max-frequency = <3000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbc_extcon0: extcon@0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + + #extcon-cells = <0>; + }; + }; +}; + +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +}; + +&tcphy0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> + +&pinctrl { + /* + * pinctrl settings for pins that have no real owners. + * + * At the moment settings are identical for S0 and S3, but if we later + * need to configure things differently for S3 we'll adjust here. + */ + pinctrl-names = "default"; + pinctrl-0 = < + &ap_pwroff /* AP will auto-assert this when in S3 */ + &clk_32k /* This pin is always 32k on gru boards */ + >; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + backlight-enable { + bl_en: bl-en { + rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cros-ec { + ec_ap_int_l: ec-ap-int-l { + rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + discrete-regulators { + sd_io_pwr_en: sd-io-pwr-en { + rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + sd_pwr_1800_sel: sd-pwr-1800-sel { + rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + sd_slot_pwr_en: sd-slot-pwr-en { + rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + }; + + codec { + /* Has external pullup */ + headset_int_l: headset-int-l { + rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mic_int: mic-int { + rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + max98357a { + sdmode_en: sdmode-en { + rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_clkreqn_cpm: pci-clkreqn-cpm { + /* + * Since our pcie doesn't support ClockPM(CPM), we want + * to hack this as gpio, so the EP could be able to + * de-assert it along and make ClockPM(CPM) work. + */ + rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * We run sdmmc at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, + <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, + <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, + <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + /* + * In our case the official card detect is hooked to ground + * to avoid getting access to JTAG just by sticking something + * in the SD card slot (see the force_jtag bit in the TRM). + * + * We still configure it as card detect because it doesn't + * hurt and dw_mmc will ignore it. We make sure to disable + * the pull though so we don't burn needless power. + */ + sdmmc_cd: sdmmc-cd { + rockchip,pins = + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + + /* This is where we actually hook up CD; has external pull */ + sdmmc_cd_gpio: sdmmc-cd-gpio { + rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + spi1 { + spi1_sleep: spi1-sleep { + /* + * Pull down SPI1 CLK/CS/RX/TX during suspend, to + * prevent leakage. + */ + rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, + <1 10 RK_FUNC_GPIO &pcfg_pull_down>, + <1 7 RK_FUNC_GPIO &pcfg_pull_down>, + <1 8 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + touchscreen { + touch_int_l: touch-int-l { + rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch_reset_l: touch-reset-l { + rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + trackpad { + ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { + rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; + }; + + trackpad_int_l: trackpad-int-l { + rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi: wifi { + wlan_module_reset_l: wlan-module-reset-l { + rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + /* Kevin has an external pull up, but Gru does not */ + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + write-protect { + ap_fw_wp: ap-fw-wp { + rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi new file mode 100644 index 0000000000..69cc9b05ba --- /dev/null +++ b/arch/arm/dts/rk3399-op1-opp.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <975000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1100000>; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1150000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <900000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <975000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1050000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1150000>; + }; + opp08 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1250000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <850000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <925000>; + }; + opp05 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1075000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +};

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 08/18] rockchip: Adjust rk3399 device tree to be closer to linux

This file has changed upstream, with some additions and changes. Move the U-Boot version towards this.

Some USB changes seem to be incompatible with how the bindings work on rockchip in U-Boot. Testing is needed to make sure that USB still works correct, and adjust the code (not device tree) if not.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/dts/rk3399.dtsi | 432 +++++++++++++++++++++++++++++++++------ 1 file changed, 371 insertions(+), 61 deletions(-)

diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 21f156782f..b53e41b4dc 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -349,45 +349,105 @@ status = "disabled"; };

- dwc3_typec0: usb@fe800000 { - compatible = "rockchip,rk3399-xhci"; - reg = <0x0 0xfe800000 0x0 0x100000>; + usbdrd3_0: dwc3_typec0: usb@fe800000 { + compatible = "rockchip,rk3399-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + resets = <&cru SRST_A_USB3_OTG0>; + reset-names = "usb3-otg"; status = "disabled"; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk;

+ usbdrd_dwc3_0: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; + status = "disabled"; + }; + }; + + dwc3_typec1: usbdrd3_1: usb@fe900000 { + compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; - hub { - compatible = "usb-hub"; - usb,device-class = <USB_CLASS_HUB>; - }; - typec_phy0 { - compatible = "rockchip,rk3399-usb3-phy"; - reg = <0x0 0xff7c0000 0x0 0x40000>; + ranges; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + resets = <&cru SRST_A_USB3_OTG1>; + reset-names = "usb3-otg"; + status = "disabled"; + + usbdrd_dwc3_1: dwc3 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe900000 0x0 0x100000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; + status = "disabled"; }; };

- dwc3_typec1: usb@fe900000 { - compatible = "rockchip,rk3399-xhci"; - reg = <0x0 0xfe900000 0x0 0x100000>; + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; + assigned-clock-rates = <100000000>, <200000000>; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + power-domains = <&power RK3399_PD_HDCP>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #sound-dai-cells = <1>; status = "disabled"; - snps,dis-enblslpm-quirk; - snps,phyif-utmi-bits = <16>; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-u2-susphy-quirk;

- #address-cells = <2>; - #size-cells = <2>; - hub { - compatible = "usb-hub"; - usb,device-class = <USB_CLASS_HUB>; - }; - typec_phy1 { - compatible = "rockchip,rk3399-usb3-phy"; - reg = <0x0 0xff800000 0x0 0x40000>; + ports { + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; }; };

@@ -1054,6 +1114,21 @@ status = "disabled"; };

+ i2c0: i2c@ff3c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3c0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C0_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c4: i2c@ff3d0000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff3d0000 0x0 0x1000>; @@ -1217,7 +1292,10 @@ <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; assigned-clock-rates = <594000000>, <800000000>, <1000000000>, @@ -1225,7 +1303,10 @@ <37500000>, <100000000>, <100000000>, <50000000>, <600000000>, - <100000000>, <50000000>; + <100000000>, <50000000>, + <400000000>, <400000000>, + <200000000>, + <200000000>; };

grf: syscon@ff770000 { @@ -1314,6 +1395,56 @@ }; };

+ tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD0>; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + status = "disabled"; + + tcphy0_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD1>; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + status = "disabled"; + + tcphy1_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy1_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + watchdog@ff848000 { compatible = "snps,dw-wdt"; reg = <0x0 0xff848000 0x0 0x100>; @@ -1340,6 +1471,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spdif_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; };

@@ -1355,6 +1487,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s0_8ch_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; };

@@ -1369,6 +1502,7 @@ pinctrl-names = "default"; pinctrl-0 = <&i2s1_2ch_bus>; power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; status = "disabled"; };

@@ -1381,21 +1515,7 @@ clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; power-domains = <&power RK3399_PD_SDIOAUDIO>; - status = "disabled"; - }; - - i2c0: i2c@ff3c0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff3c0000 0x0 0x1000>; - assigned-clocks = <&pmucru SCLK_I2C0_PMU>; - assigned-clock-rates = <200000000>; - clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; + #sound-dai-cells = <0>; status = "disabled"; };

@@ -1404,69 +1524,177 @@ compatible = "rockchip,rk3399-vop-lit"; reg = <0x0 0xff8f0000 0x0 0x3efc>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + assigned-clock-rates = <400000000>, <100000000>; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vopl_mmu>; + power-domains = <&power RK3399_PD_VOPL>; resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; reset-names = "axi", "ahb", "dclk"; status = "disabled"; + vopl_out: port { #address-cells = <1>; #size-cells = <0>; + vopl_out_mipi: endpoint@0 { - reg = <3>; + reg = <0>; remote-endpoint = <&mipi_in_vopl>; };

- vopl_out_hdmi: endpoint@1 { + vopl_out_edp: endpoint@1 { reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + + vopl_out_hdmi: endpoint@2 { + reg = <2>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopl>; + }; + + vopl_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopl>; + }; }; };

+ vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPL>; + #iommu-cells = <0>; + status = "disabled"; + }; + vopb: vop@ff900000 { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-vop-big"; reg = <0x0 0xff900000 0x0 0x3efc>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + assigned-clock-rates = <400000000>, <100000000>; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - #clock-cells = <0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vopb_mmu>; + power-domains = <&power RK3399_PD_VOPB>; resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; reset-names = "axi", "ahb", "dclk"; status = "disabled"; + vopb_out: port { #address-cells = <1>; #size-cells = <0>; - vopb_out_mipi: endpoint@0 { - reg = <3>; - remote-endpoint = <&mipi_in_vopb>; + + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_in_vopb>; };

- vopb_out_hdmi: endpoint@1 { + vopb_out_mipi: endpoint@1 { reg = <1>; + remote-endpoint = <&mipi_in_vopb>; + }; + + vopb_out_hdmi: endpoint@2 { + reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopb>; + }; + + vopb_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopb>; + }; + }; + }; + + vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPB>; + #iommu-cells = <0>; + status = "disabled"; + }; + + isp0_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "hdmi-sound"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; }; };

hdmi: hdmi@ff940000 { compatible = "rockchip,rk3399-dw-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_HDMI_CTRL>, + <&cru SCLK_HDMI_SFR>, + <&cru PLL_VPLL>, + <&cru PCLK_VIO_GRF>, + <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "vpll", "grf", "cec"; + power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_i2c_xfer>; - power-domains = <&power RK3399_PD_HDCP>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>; - clock-names = "iahb", "isfr", "vpll", "grf"; + #sound-dai-cells = <0>; status = "disabled";

ports { hdmi_in: port { #address-cells = <1>; #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; @@ -1507,6 +1735,88 @@ }; };

+ mipi_dsi1: mipi@ff968000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff968000 0x0 0x8000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI1>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi1>; + }; + + mipi1_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi1>; + }; + }; + }; + }; + + edp: edp@ff970000 { + compatible = "rockchip,rk3399-edp"; + reg = <0x0 0xff970000 0x0 0x8000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; + clock-names = "dp", "pclk", "grf"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + power-domains = <&power RK3399_PD_EDP>; + resets = <&cru SRST_P_EDP_CTRL>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + gpu: gpu@ff9a0000 { + compatible = "rockchip,rk3399-mali", "arm,mali-t860"; + reg = <0x0 0xff9a0000 0x0 0x10000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "gpu", "job", "mmu"; + clocks = <&cru ACLK_GPU>; + power-domains = <&power RK3399_PD_GPU>; + status = "disabled"; + }; + pinctrl: pinctrl { u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl"; @@ -1911,7 +2221,7 @@ <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; };

- sdmmc_cd: sdmcc-cd { + sdmmc_cd: sdmmc-cd { rockchip,pins = <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; };

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 09/18] rockchip: evb_rk3399: Tidy up the README

Add mention of a prerequisite needed to build the image. Also adjust the English wording in a few places.

Ideally this should move to using binman to produce images, and avoid the manual steps.

Signed-off-by: Simon Glass sjg@chromium.org ---

board/rockchip/evb_rk3399/README | 33 ++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README index 8321467046..6469821987 100644 --- a/board/rockchip/evb_rk3399/README +++ b/board/rockchip/evb_rk3399/README @@ -35,21 +35,29 @@ Get the Source and prebuild binary

...

git clone https://github.com/rockchip-linux/rkbin.git git clone https://github.com/rockchip-linux/rkdeveloptool.git

-Compile the ATF -=============== +Get some prerequisites +====================== + +You need the Python elftools.elf.elffile library for make_fit_atf.py to work: + + > sudo apt-get install python-pyelftools + +Compile ATF +===========

...

cd arm-trusted-firmware make realclean make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31

+ Get bl31.elf in this step, copy it to U-Boot root dir: + > cp build/rk3399/release/bl31/bl31.elf ../u-boot/ + Or you can get the bl31.elf directly from Rockchip: - cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf + > cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf

- Get bl31.elf in this step, copy it to U-Boot root dir: - > cp bl31.elf ../u-boot/

-Compile the U-Boot -================== +Compile U-Boot +==============

...

cd ../u-boot export ARCH=arm64

@@ -62,17 +70,18 @@ Compile the U-Boot

Get spl/u-boot-spl.bin and u-boot.itb in this step.

-Compile the rkdeveloptool -======================= - Follow instructions in latest README +Compile rkdeveloptool +===================== + +Get rkdeveloptool installed on your Host in this step. + +Follow instructions in latest README, example:

...

cd ../rkdeveloptool autoreconf -i ./configure make sudo make install

- Get rkdeveloptool in you Host in this step. - Both origin binaries and Tool are ready now, choose either option 1 or option 2 to deploy U-Boot.

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 10/18] rockchip: Clarify docs on SPI writing

We use every second block when creating a SPI image, so update the text to say this explicitly.

Signed-off-by: Simon Glass sjg@chromium.org ---

doc/README.rockchip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip index a45b8a97b7..9b7e4bac11 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -261,7 +261,7 @@ To write an image that boots from SPI flash (e.g. for the Haier Chromebook): dd if=out.bin of=out.bin.pad bs=4M conv=sync

This converts the SPL image to the required SPI format by adding the Rockchip -header and skipping every 2KB block. Then the U-Boot image is written at +header and skipping every second 2KB block. Then the U-Boot image is written at offset 128KB and the whole image is padded to 4MB which is the SPI flash size. The position of U-Boot is controlled with this setting in U-Boot:

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 11/18] rockchip: Allow booting from SPI

The u-boot,spl-boot-device property only allows MMC at present. Add SPI as well for boards that boot from SPI flash.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-rockchip/spl-boot-order.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 81a72cc263..0e485deda2 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -61,6 +61,9 @@ static int spl_node_to_boot_device(int node) default: return -ENOSYS; } + } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, + &parent)) { + return BOOT_DEVICE_SPI; }

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 12/18] rockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHz

This memory is used on Bob. Add settings for this, taken from coreboot.

Signed-off-by: Simon Glass sjg@chromium.org ---

.../rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi | 1542 +++++++++++++++++ 1 file changed, 1542 insertions(+) create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi

diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi new file mode 100644 index 0000000000..2a627e1be5 --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi @@ -0,0 +1,1542 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +&dmc { + rockchip,sdram-params = < + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + + 0x801d181e + 0x17050a08 + 0x00000002 + 0x00006426 + 0x0000004c + 0x00000000 + + 0x2 + 0xa + 0x3 + 0x2 + 0x2 + 0x0 + 0xf + 0xf + 1 + + 0x801d181e + 0x17050a08 + 0x00000002 + 0x00006426 + 0x0000004c + 0x00000000 + + 933 + 6 /* LPDDR3 */ + 2 + 13 + 1 + + 0x00000700 /* DENALI_CTL_00_DATA */ + 0x00000000 /* DENALI_CTL_01_DATA */ + 0x00000000 /* DENALI_CTL_02_DATA */ + 0x00000000 /* DENALI_CTL_03_DATA */ + 0x00000000 /* DENALI_CTL_04_DATA */ + 0x0000005e /* DENALI_CTL_05_DATA */ + 0x0002d976 /* DENALI_CTL_06_DATA */ + 0x000003a6 /* DENALI_CTL_07_DATA */ + 0x0000247a /* DENALI_CTL_08_DATA */ + 0x0000005e /* DENALI_CTL_09_DATA */ + 0x0002d976 /* DENALI_CTL_10_DATA */ + 0x000003a6 /* DENALI_CTL_11_DATA */ + 0x0000247a /* DENALI_CTL_12_DATA */ + 0x0000005e /* DENALI_CTL_13_DATA */ + 0x0002d976 /* DENALI_CTL_14_DATA */ + 0x000003a6 /* DENALI_CTL_15_DATA */ + 0x0100247a /* DENALI_CTL_16_DATA */ + 0x00000000 /* DENALI_CTL_17_DATA */ + 0x00000101 /* DENALI_CTL_18_DATA */ + 0x00020100 /* DENALI_CTL_19_DATA */ + 0x000000bb /* DENALI_CTL_20_DATA */ + 0x000001d3 /* DENALI_CTL_21_DATA */ + 0x00000000 /* DENALI_CTL_22_DATA */ + 0x081c0000 /* DENALI_CTL_23_DATA */ + 0x00081c00 /* DENALI_CTL_24_DATA */ + 0x0400081c /* DENALI_CTL_25_DATA */ + 0x3b0a0004 /* DENALI_CTL_26_DATA */ + 0x2f110828 /* DENALI_CTL_27_DATA */ + 0x283b0a00 /* DENALI_CTL_28_DATA */ + 0x002f1108 /* DENALI_CTL_29_DATA */ + 0x08283b0a /* DENALI_CTL_30_DATA */ + 0x08002f11 /* DENALI_CTL_31_DATA */ + 0x00000a0a /* DENALI_CTL_32_DATA */ + 0x0800ff4f /* DENALI_CTL_33_DATA */ + 0x0a0a080f /* DENALI_CTL_34_DATA */ + 0x0800ff4f /* DENALI_CTL_35_DATA */ + 0x0a0a080f /* DENALI_CTL_36_DATA */ + 0x0800ff4f /* DENALI_CTL_37_DATA */ + 0x0203000f /* DENALI_CTL_38_DATA */ + 0x110f1100 /* DENALI_CTL_39_DATA */ + 0x040f110f /* DENALI_CTL_40_DATA */ + 0x14000a0a /* DENALI_CTL_41_DATA */ + 0x03030a0a /* DENALI_CTL_42_DATA */ + 0x00010003 /* DENALI_CTL_43_DATA */ + 0x03212121 /* DENALI_CTL_44_DATA */ + 0x00141414 /* DENALI_CTL_45_DATA */ + 0x00000000 /* DENALI_CTL_46_DATA */ + 0x03010000 /* DENALI_CTL_47_DATA */ + 0x0e3100c5 /* DENALI_CTL_48_DATA */ + 0x0e3100c5 /* DENALI_CTL_49_DATA */ + 0x0e3100c5 /* DENALI_CTL_50_DATA */ + 0x00000000 /* DENALI_CTL_51_DATA */ + 0x00080008 /* DENALI_CTL_52_DATA */ + 0x00170008 /* DENALI_CTL_53_DATA */ + 0x00170017 /* DENALI_CTL_54_DATA */ + 0x00111111 /* DENALI_CTL_55_DATA */ + 0x00000000 /* DENALI_CTL_56_DATA */ + 0x00000000 /* DENALI_CTL_57_DATA */ + 0x00000000 /* DENALI_CTL_58_DATA */ + 0x00ce0000 /* DENALI_CTL_59_DATA */ + 0x00ce00ce /* DENALI_CTL_60_DATA */ + 0x00ce00ce /* DENALI_CTL_61_DATA */ + 0x000000ce /* DENALI_CTL_62_DATA */ + 0x00000000 /* DENALI_CTL_63_DATA */ + 0x00000000 /* DENALI_CTL_64_DATA */ + 0x00000000 /* DENALI_CTL_65_DATA */ + 0x00000000 /* DENALI_CTL_66_DATA */ + 0x00000000 /* DENALI_CTL_67_DATA */ + 0x00000000 /* DENALI_CTL_68_DATA */ + 0x00000301 /* DENALI_CTL_69_DATA */ + 0x00000001 /* DENALI_CTL_70_DATA */ + 0x00000000 /* DENALI_CTL_71_DATA */ + 0x00000000 /* DENALI_CTL_72_DATA */ + 0x01000000 /* DENALI_CTL_73_DATA */ + 0x80104002 /* DENALI_CTL_74_DATA */ + 0x00040003 /* DENALI_CTL_75_DATA */ + 0x00040005 /* DENALI_CTL_76_DATA */ + 0x00030000 /* DENALI_CTL_77_DATA */ + 0x00050004 /* DENALI_CTL_78_DATA */ + 0x00000004 /* DENALI_CTL_79_DATA */ + 0x00040003 /* DENALI_CTL_80_DATA */ + 0x00040005 /* DENALI_CTL_81_DATA */ + 0x38c40000 /* DENALI_CTL_82_DATA */ + 0x00001c62 /* DENALI_CTL_83_DATA */ + 0x1c6238c4 /* DENALI_CTL_84_DATA */ + 0x38c40000 /* DENALI_CTL_85_DATA */ + 0x00001c62 /* DENALI_CTL_86_DATA */ + 0x00000000 /* DENALI_CTL_87_DATA */ + 0x00000000 /* DENALI_CTL_88_DATA */ + 0x00000000 /* DENALI_CTL_89_DATA */ + 0x00000000 /* DENALI_CTL_90_DATA */ + 0x00000000 /* DENALI_CTL_91_DATA */ + 0x02020200 /* DENALI_CTL_92_DATA */ + 0x00020202 /* DENALI_CTL_93_DATA */ + 0x00030200 /* DENALI_CTL_94_DATA */ + 0x00040700 /* DENALI_CTL_95_DATA */ + 0x00000302 /* DENALI_CTL_96_DATA */ + 0x02000407 /* DENALI_CTL_97_DATA */ + 0x00000003 /* DENALI_CTL_98_DATA */ + 0x00030f04 /* DENALI_CTL_99_DATA */ + 0x00070004 /* DENALI_CTL_100_DATA */ + 0x00000000 /* DENALI_CTL_101_DATA */ + 0x00000000 /* DENALI_CTL_102_DATA */ + 0x00000000 /* DENALI_CTL_103_DATA */ + 0x00000000 /* DENALI_CTL_104_DATA */ + 0x00000000 /* DENALI_CTL_105_DATA */ + 0x00000000 /* DENALI_CTL_106_DATA */ + 0x00000000 /* DENALI_CTL_107_DATA */ + 0x00010000 /* DENALI_CTL_108_DATA */ + 0x20040020 /* DENALI_CTL_109_DATA */ + 0x00200400 /* DENALI_CTL_110_DATA */ + 0x01000400 /* DENALI_CTL_111_DATA */ + 0x00000b80 /* DENALI_CTL_112_DATA */ + 0x00000000 /* DENALI_CTL_113_DATA */ + 0x00000001 /* DENALI_CTL_114_DATA */ + 0x00000002 /* DENALI_CTL_115_DATA */ + 0x0000000e /* DENALI_CTL_116_DATA */ + 0x00000000 /* DENALI_CTL_117_DATA */ + 0x00000000 /* DENALI_CTL_118_DATA */ + 0x00000000 /* DENALI_CTL_119_DATA */ + 0x00000000 /* DENALI_CTL_120_DATA */ + 0x00000000 /* DENALI_CTL_121_DATA */ + 0x00bb0000 /* DENALI_CTL_122_DATA */ + 0x00ea005e /* DENALI_CTL_123_DATA */ + 0x00ea0000 /* DENALI_CTL_124_DATA */ + 0x005e00bb /* DENALI_CTL_125_DATA */ + 0x000000ea /* DENALI_CTL_126_DATA */ + 0x00bb00ea /* DENALI_CTL_127_DATA */ + 0x00ea005e /* DENALI_CTL_128_DATA */ + 0x00ea0000 /* DENALI_CTL_129_DATA */ + 0x00000000 /* DENALI_CTL_130_DATA */ + 0x00000000 /* DENALI_CTL_131_DATA */ + 0x00000000 /* DENALI_CTL_132_DATA */ + 0x00c30000 /* DENALI_CTL_133_DATA */ + 0x0000001c /* DENALI_CTL_134_DATA */ + 0x001c00c3 /* DENALI_CTL_135_DATA */ + 0x00c30000 /* DENALI_CTL_136_DATA */ + 0x0000001c /* DENALI_CTL_137_DATA */ + 0x00010001 /* DENALI_CTL_138_DATA */ + 0x06000001 /* DENALI_CTL_139_DATA */ + 0x00000606 /* DENALI_CTL_140_DATA */ + 0x00000000 /* DENALI_CTL_141_DATA */ + 0x00000000 /* DENALI_CTL_142_DATA */ + 0x00000000 /* DENALI_CTL_143_DATA */ + 0x00000000 /* DENALI_CTL_144_DATA */ + 0x00000000 /* DENALI_CTL_145_DATA */ + 0x00000000 /* DENALI_CTL_146_DATA */ + 0x00c30000 /* DENALI_CTL_147_DATA */ + 0x0000001c /* DENALI_CTL_148_DATA */ + 0x001c00c3 /* DENALI_CTL_149_DATA */ + 0x00c30000 /* DENALI_CTL_150_DATA */ + 0x0000001c /* DENALI_CTL_151_DATA */ + 0x00010001 /* DENALI_CTL_152_DATA */ + 0x06000001 /* DENALI_CTL_153_DATA */ + 0x00000606 /* DENALI_CTL_154_DATA */ + 0x00000000 /* DENALI_CTL_155_DATA */ + 0x00000000 /* DENALI_CTL_156_DATA */ + 0x00000000 /* DENALI_CTL_157_DATA */ + 0x00000000 /* DENALI_CTL_158_DATA */ + 0x00000000 /* DENALI_CTL_159_DATA */ + 0x00000000 /* DENALI_CTL_160_DATA */ + 0x01000000 /* DENALI_CTL_161_DATA */ + 0x00000000 /* DENALI_CTL_162_DATA */ + 0x00000000 /* DENALI_CTL_163_DATA */ + 0x18151100 /* DENALI_CTL_164_DATA */ + 0x0000000c /* DENALI_CTL_165_DATA */ + 0x00000000 /* DENALI_CTL_166_DATA */ + 0x00000000 /* DENALI_CTL_167_DATA */ + 0x00000000 /* DENALI_CTL_168_DATA */ + 0x00000000 /* DENALI_CTL_169_DATA */ + 0x00000000 /* DENALI_CTL_170_DATA */ + 0x00000000 /* DENALI_CTL_171_DATA */ + 0x00000000 /* DENALI_CTL_172_DATA */ + 0x00000000 /* DENALI_CTL_173_DATA */ + 0x00000000 /* DENALI_CTL_174_DATA */ + 0x00000000 /* DENALI_CTL_175_DATA */ + 0x00000000 /* DENALI_CTL_176_DATA */ + 0x00000000 /* DENALI_CTL_177_DATA */ + 0x00000000 /* DENALI_CTL_178_DATA */ + 0x0003a603 /* DENALI_CTL_179_DATA */ + 0x00550151 /* DENALI_CTL_180_DATA */ + 0x00000000 /* DENALI_CTL_181_DATA */ + 0x015103a6 /* DENALI_CTL_182_DATA */ + 0x00000055 /* DENALI_CTL_183_DATA */ + 0x0003a600 /* DENALI_CTL_184_DATA */ + 0x00550151 /* DENALI_CTL_185_DATA */ + 0x00000000 /* DENALI_CTL_186_DATA */ + 0x002f0000 /* DENALI_CTL_187_DATA */ + 0x002f002f /* DENALI_CTL_188_DATA */ + 0x01010100 /* DENALI_CTL_189_DATA */ + 0x01000202 /* DENALI_CTL_190_DATA */ + 0x0a000002 /* DENALI_CTL_191_DATA */ + 0x01000f0f /* DENALI_CTL_192_DATA */ + 0x00000000 /* DENALI_CTL_193_DATA */ + 0x00000000 /* DENALI_CTL_194_DATA */ + 0x00010003 /* DENALI_CTL_195_DATA */ + 0x00000c03 /* DENALI_CTL_196_DATA */ + 0x00000100 /* DENALI_CTL_197_DATA */ + 0x00010000 /* DENALI_CTL_198_DATA */ + 0x01000000 /* DENALI_CTL_199_DATA */ + 0x00010000 /* DENALI_CTL_200_DATA */ + 0x00000001 /* DENALI_CTL_201_DATA */ + 0x00000000 /* DENALI_CTL_202_DATA */ + 0x00000000 /* DENALI_CTL_203_DATA */ + 0x00000000 /* DENALI_CTL_204_DATA */ + 0x00000000 /* DENALI_CTL_205_DATA */ + 0x00000000 /* DENALI_CTL_206_DATA */ + 0x00000000 /* DENALI_CTL_207_DATA */ + 0x00000000 /* DENALI_CTL_208_DATA */ + 0x00000000 /* DENALI_CTL_209_DATA */ + 0x00000000 /* DENALI_CTL_210_DATA */ + 0x00010000 /* DENALI_CTL_211_DATA */ + 0x04040401 /* DENALI_CTL_212_DATA */ + 0x01010808 /* DENALI_CTL_213_DATA */ + 0x04040001 /* DENALI_CTL_214_DATA */ + 0x0c0c0c04 /* DENALI_CTL_215_DATA */ + 0x08080808 /* DENALI_CTL_216_DATA */ + 0x08050103 /* DENALI_CTL_217_DATA */ + 0x02050103 /* DENALI_CTL_218_DATA */ + 0x00050103 /* DENALI_CTL_219_DATA */ + 0x00020202 /* DENALI_CTL_220_DATA */ + 0x06030600 /* DENALI_CTL_221_DATA */ + 0x00030603 /* DENALI_CTL_222_DATA */ + 0x00000000 /* DENALI_CTL_223_DATA */ + 0x00000000 /* DENALI_CTL_224_DATA */ + 0x0d000001 /* DENALI_CTL_225_DATA */ + 0x00010028 /* DENALI_CTL_226_DATA */ + 0x00010000 /* DENALI_CTL_227_DATA */ + 0x00000003 /* DENALI_CTL_228_DATA */ + 0x00000000 /* DENALI_CTL_229_DATA */ + 0x00000000 /* DENALI_CTL_230_DATA */ + 0x00000000 /* DENALI_CTL_231_DATA */ + 0x00000000 /* DENALI_CTL_232_DATA */ + 0x00000000 /* DENALI_CTL_233_DATA */ + 0x00000000 /* DENALI_CTL_234_DATA */ + 0x00000000 /* DENALI_CTL_235_DATA */ + 0x00000000 /* DENALI_CTL_236_DATA */ + 0x00010100 /* DENALI_CTL_237_DATA */ + 0x01000000 /* DENALI_CTL_238_DATA */ + 0x00000001 /* DENALI_CTL_239_DATA */ + 0x00000303 /* DENALI_CTL_240_DATA */ + 0x00000000 /* DENALI_CTL_241_DATA */ + 0x00000000 /* DENALI_CTL_242_DATA */ + 0x00000000 /* DENALI_CTL_243_DATA */ + 0x00000000 /* DENALI_CTL_244_DATA */ + 0x00000000 /* DENALI_CTL_245_DATA */ + 0x00000000 /* DENALI_CTL_246_DATA */ + 0x00000000 /* DENALI_CTL_247_DATA */ + 0x00000000 /* DENALI_CTL_248_DATA */ + 0x00000000 /* DENALI_CTL_249_DATA */ + 0x00000000 /* DENALI_CTL_250_DATA */ + 0x00000000 /* DENALI_CTL_251_DATA */ + 0x00000000 /* DENALI_CTL_252_DATA */ + 0x00000000 /* DENALI_CTL_253_DATA */ + 0x00000000 /* DENALI_CTL_254_DATA */ + 0x00000000 /* DENALI_CTL_255_DATA */ + 0x000fffff /* DENALI_CTL_256_DATA */ + 0x00000000 /* DENALI_CTL_257_DATA */ + 0x000556aa /* DENALI_CTL_258_DATA */ + 0x000aaaaa /* DENALI_CTL_259_DATA */ + 0x000b3133 /* DENALI_CTL_260_DATA */ + 0x0004cd33 /* DENALI_CTL_261_DATA */ + 0x0004cecc /* DENALI_CTL_262_DATA */ + 0x000b32cc /* DENALI_CTL_263_DATA */ + 0x00010300 /* DENALI_CTL_264_DATA */ + 0x03000100 /* DENALI_CTL_265_DATA */ + 0x00000000 /* DENALI_CTL_266_DATA */ + 0x00000000 /* DENALI_CTL_267_DATA */ + 0x00000000 /* DENALI_CTL_268_DATA */ + 0x00000000 /* DENALI_CTL_269_DATA */ + 0x00000000 /* DENALI_CTL_270_DATA */ + 0x00000000 /* DENALI_CTL_271_DATA */ + 0x00000000 /* DENALI_CTL_272_DATA */ + 0x00000000 /* DENALI_CTL_273_DATA */ + 0x00ffff00 /* DENALI_CTL_274_DATA */ + 0x20200000 /* DENALI_CTL_275_DATA */ + 0x08000020 /* DENALI_CTL_276_DATA */ + 0x00001c62 /* DENALI_CTL_277_DATA */ + 0x00000200 /* DENALI_CTL_278_DATA */ + 0x00000200 /* DENALI_CTL_279_DATA */ + 0x00000200 /* DENALI_CTL_280_DATA */ + 0x00000200 /* DENALI_CTL_281_DATA */ + 0x00001c62 /* DENALI_CTL_282_DATA */ + 0x00011bd4 /* DENALI_CTL_283_DATA */ + 0x1c62070c /* DENALI_CTL_284_DATA */ + 0x00000200 /* DENALI_CTL_285_DATA */ + 0x00000200 /* DENALI_CTL_286_DATA */ + 0x00000200 /* DENALI_CTL_287_DATA */ + 0x00000200 /* DENALI_CTL_288_DATA */ + 0x00001c62 /* DENALI_CTL_289_DATA */ + 0x00011bd4 /* DENALI_CTL_290_DATA */ + 0x1c62070c /* DENALI_CTL_291_DATA */ + 0x00000200 /* DENALI_CTL_292_DATA */ + 0x00000200 /* DENALI_CTL_293_DATA */ + 0x00000200 /* DENALI_CTL_294_DATA */ + 0x00000200 /* DENALI_CTL_295_DATA */ + 0x00001c62 /* DENALI_CTL_296_DATA */ + 0x00011bd4 /* DENALI_CTL_297_DATA */ + 0x0202070c /* DENALI_CTL_298_DATA */ + 0x03030202 /* DENALI_CTL_299_DATA */ + 0x00000018 /* DENALI_CTL_300_DATA */ + 0x00000000 /* DENALI_CTL_301_DATA */ + 0x00000000 /* DENALI_CTL_302_DATA */ + 0x00001403 /* DENALI_CTL_303_DATA */ + 0x00000000 /* DENALI_CTL_304_DATA */ + 0x00000000 /* DENALI_CTL_305_DATA */ + 0x00000000 /* DENALI_CTL_306_DATA */ + 0x00030000 /* DENALI_CTL_307_DATA */ + 0x000f0021 /* DENALI_CTL_308_DATA */ + 0x000f0021 /* DENALI_CTL_309_DATA */ + 0x000f0021 /* DENALI_CTL_310_DATA */ + 0x00000000 /* DENALI_CTL_311_DATA */ + 0x00000000 /* DENALI_CTL_312_DATA */ + 0x01000000 /* DENALI_CTL_313_DATA */ + 0x02090209 /* DENALI_CTL_314_DATA */ + 0x00050209 /* DENALI_CTL_315_DATA */ + 0x00000000 /* DENALI_CTL_316_DATA */ + 0x00000000 /* DENALI_CTL_317_DATA */ + 0x00000000 /* DENALI_CTL_318_DATA */ + 0x00000000 /* DENALI_CTL_319_DATA */ + 0x00000000 /* DENALI_CTL_320_DATA */ + 0x00000000 /* DENALI_CTL_321_DATA */ + 0x00000000 /* DENALI_CTL_322_DATA */ + 0x00000000 /* DENALI_CTL_323_DATA */ + 0x01000101 /* DENALI_CTL_324_DATA */ + 0x01010101 /* DENALI_CTL_325_DATA */ + 0x01000101 /* DENALI_CTL_326_DATA */ + 0x01000100 /* DENALI_CTL_327_DATA */ + 0x00010001 /* DENALI_CTL_328_DATA */ + 0x00010002 /* DENALI_CTL_329_DATA */ + 0x00020100 /* DENALI_CTL_330_DATA */ + 0x00000002 /* DENALI_CTL_331_DATA */ + + 0x00000700 /* DENALI_PI_00_DATA */ + 0x00000000 /* DENALI_PI_01_DATA */ + 0x000038c4 /* DENALI_PI_02_DATA */ + 0x00001c62 /* DENALI_PI_03_DATA */ + 0x000038c4 /* DENALI_PI_04_DATA */ + 0x00001c62 /* DENALI_PI_05_DATA */ + 0x000038c4 /* DENALI_PI_06_DATA */ + 0x1c621c62 /* DENALI_PI_07_DATA */ + 0x00000200 /* DENALI_PI_08_DATA */ + 0x00000200 /* DENALI_PI_09_DATA */ + 0x00000200 /* DENALI_PI_10_DATA */ + 0x00000200 /* DENALI_PI_11_DATA */ + 0x00001c62 /* DENALI_PI_12_DATA */ + 0x00000200 /* DENALI_PI_13_DATA */ + 0x00000200 /* DENALI_PI_14_DATA */ + 0x00000200 /* DENALI_PI_15_DATA */ + 0x00000200 /* DENALI_PI_16_DATA */ + 0x00001c62 /* DENALI_PI_17_DATA */ + 0x00000200 /* DENALI_PI_18_DATA */ + 0x00000200 /* DENALI_PI_19_DATA */ + 0x00000200 /* DENALI_PI_20_DATA */ + 0x00000200 /* DENALI_PI_21_DATA */ + 0x00010000 /* DENALI_PI_22_DATA */ + 0x00000007 /* DENALI_PI_23_DATA */ + 0x81000001 /* DENALI_PI_24_DATA */ + 0x0f0003f0 /* DENALI_PI_25_DATA */ + 0x3fffffff /* DENALI_PI_26_DATA */ + 0x0f0000a0 /* DENALI_PI_27_DATA */ + 0x377ff000 /* DENALI_PI_28_DATA */ + 0x0f000020 /* DENALI_PI_29_DATA */ + 0x377ff000 /* DENALI_PI_30_DATA */ + 0x0f000030 /* DENALI_PI_31_DATA */ + 0x377ff000 /* DENALI_PI_32_DATA */ + 0x0f0000b0 /* DENALI_PI_33_DATA */ + 0x377ff000 /* DENALI_PI_34_DATA */ + 0x0f000100 /* DENALI_PI_35_DATA */ + 0x377ff000 /* DENALI_PI_36_DATA */ + 0x0f000110 /* DENALI_PI_37_DATA */ + 0x377ff000 /* DENALI_PI_38_DATA */ + 0x0f000010 /* DENALI_PI_39_DATA */ + 0x377ff000 /* DENALI_PI_40_DATA */ + 0x03000101 /* DENALI_PI_41_DATA */ + 0x04323232 /* DENALI_PI_42_DATA */ + 0x081c0008 /* DENALI_PI_43_DATA */ + 0x00081c00 /* DENALI_PI_44_DATA */ + 0x0000001c /* DENALI_PI_45_DATA */ + 0x0e3100c5 /* DENALI_PI_46_DATA */ + 0x0e3100c5 /* DENALI_PI_47_DATA */ + 0x0e3100c5 /* DENALI_PI_48_DATA */ + 0x00000500 /* DENALI_PI_49_DATA */ + 0x00000000 /* DENALI_PI_50_DATA */ + 0x00000000 /* DENALI_PI_51_DATA */ + 0x00000000 /* DENALI_PI_52_DATA */ + 0x00000000 /* DENALI_PI_53_DATA */ + 0x00000000 /* DENALI_PI_54_DATA */ + 0x00000000 /* DENALI_PI_55_DATA */ + 0x00000000 /* DENALI_PI_56_DATA */ + 0x00000000 /* DENALI_PI_57_DATA */ + 0x04040000 /* DENALI_PI_58_DATA */ + 0x0d000004 /* DENALI_PI_59_DATA */ + 0x00000128 /* DENALI_PI_60_DATA */ + 0x00000000 /* DENALI_PI_61_DATA */ + 0x00030003 /* DENALI_PI_62_DATA */ + 0x00000018 /* DENALI_PI_63_DATA */ + 0x00000000 /* DENALI_PI_64_DATA */ + 0x00000000 /* DENALI_PI_65_DATA */ + 0x04060002 /* DENALI_PI_66_DATA */ + 0x04010401 /* DENALI_PI_67_DATA */ + 0x00080801 /* DENALI_PI_68_DATA */ + 0x00020001 /* DENALI_PI_69_DATA */ + 0x00080004 /* DENALI_PI_70_DATA */ + 0x00000000 /* DENALI_PI_71_DATA */ + 0x04040000 /* DENALI_PI_72_DATA */ + 0x0c0c0c04 /* DENALI_PI_73_DATA */ + 0x00000000 /* DENALI_PI_74_DATA */ + 0x00000000 /* DENALI_PI_75_DATA */ + 0x00000000 /* DENALI_PI_76_DATA */ + 0x00030300 /* DENALI_PI_77_DATA */ + 0x00000014 /* DENALI_PI_78_DATA */ + 0x00000000 /* DENALI_PI_79_DATA */ + 0x01010300 /* DENALI_PI_80_DATA */ + 0x00000000 /* DENALI_PI_81_DATA */ + 0x00000000 /* DENALI_PI_82_DATA */ + 0x01000000 /* DENALI_PI_83_DATA */ + 0x00000101 /* DENALI_PI_84_DATA */ + 0x55555a5a /* DENALI_PI_85_DATA */ + 0x55555a5a /* DENALI_PI_86_DATA */ + 0x55555a5a /* DENALI_PI_87_DATA */ + 0x55555a5a /* DENALI_PI_88_DATA */ + 0x0c0c0001 /* DENALI_PI_89_DATA */ + 0x0707000c /* DENALI_PI_90_DATA */ + 0x02020007 /* DENALI_PI_91_DATA */ + 0x00000102 /* DENALI_PI_92_DATA */ + 0x00030000 /* DENALI_PI_93_DATA */ + 0x17030000 /* DENALI_PI_94_DATA */ + 0x000f0021 /* DENALI_PI_95_DATA */ + 0x000f0021 /* DENALI_PI_96_DATA */ + 0x000f0021 /* DENALI_PI_97_DATA */ + 0x00000000 /* DENALI_PI_98_DATA */ + 0x00000000 /* DENALI_PI_99_DATA */ + 0x00000100 /* DENALI_PI_100_DATA */ + 0x140a0000 /* DENALI_PI_101_DATA */ + 0x000a030a /* DENALI_PI_102_DATA */ + 0x03000a03 /* DENALI_PI_103_DATA */ + 0x010a000a /* DENALI_PI_104_DATA */ + 0x00000100 /* DENALI_PI_105_DATA */ + 0x01000000 /* DENALI_PI_106_DATA */ + 0x00000000 /* DENALI_PI_107_DATA */ + 0x00000100 /* DENALI_PI_108_DATA */ + 0x1e1a0000 /* DENALI_PI_109_DATA */ + 0x10010204 /* DENALI_PI_110_DATA */ + 0x07070705 /* DENALI_PI_111_DATA */ + 0x20000202 /* DENALI_PI_112_DATA */ + 0x00201000 /* DENALI_PI_113_DATA */ + 0x00201000 /* DENALI_PI_114_DATA */ + 0x04041000 /* DENALI_PI_115_DATA */ + 0x12120100 /* DENALI_PI_116_DATA */ + 0x00010112 /* DENALI_PI_117_DATA */ + 0x004b004a /* DENALI_PI_118_DATA */ + 0x1a030000 /* DENALI_PI_119_DATA */ + 0x0102041e /* DENALI_PI_120_DATA */ + 0x34000000 /* DENALI_PI_121_DATA */ + 0x00000000 /* DENALI_PI_122_DATA */ + 0x00000000 /* DENALI_PI_123_DATA */ + 0x00000000 /* DENALI_PI_124_DATA */ + 0x0000c300 /* DENALI_PI_125_DATA */ + 0x0001001c /* DENALI_PI_126_DATA */ + 0x004d4d07 /* DENALI_PI_127_DATA */ + 0x001c00c3 /* DENALI_PI_128_DATA */ + 0x4d070001 /* DENALI_PI_129_DATA */ + 0x0000c34d /* DENALI_PI_130_DATA */ + 0x0001001c /* DENALI_PI_131_DATA */ + 0x004d4d07 /* DENALI_PI_132_DATA */ + 0x001c00c3 /* DENALI_PI_133_DATA */ + 0x4d070001 /* DENALI_PI_134_DATA */ + 0x0000c34d /* DENALI_PI_135_DATA */ + 0x0001001c /* DENALI_PI_136_DATA */ + 0x004d4d07 /* DENALI_PI_137_DATA */ + 0x001c00c3 /* DENALI_PI_138_DATA */ + 0x4d070001 /* DENALI_PI_139_DATA */ + 0x00c3004d /* DENALI_PI_140_DATA */ + 0x0001001c /* DENALI_PI_141_DATA */ + 0x004d4d07 /* DENALI_PI_142_DATA */ + 0x001c00c3 /* DENALI_PI_143_DATA */ + 0x4d070001 /* DENALI_PI_144_DATA */ + 0x0000c34d /* DENALI_PI_145_DATA */ + 0x0001001c /* DENALI_PI_146_DATA */ + 0x004d4d07 /* DENALI_PI_147_DATA */ + 0x001c00c3 /* DENALI_PI_148_DATA */ + 0x4d070001 /* DENALI_PI_149_DATA */ + 0x0000c34d /* DENALI_PI_150_DATA */ + 0x0001001c /* DENALI_PI_151_DATA */ + 0x004d4d07 /* DENALI_PI_152_DATA */ + 0x001c00c3 /* DENALI_PI_153_DATA */ + 0x4d070001 /* DENALI_PI_154_DATA */ + 0x0100004d /* DENALI_PI_155_DATA */ + 0x00ea00ea /* DENALI_PI_156_DATA */ + 0x080400ea /* DENALI_PI_157_DATA */ + 0x0f081114 /* DENALI_PI_158_DATA */ + 0x2800fcc1 /* DENALI_PI_159_DATA */ + 0x0a0e2006 /* DENALI_PI_160_DATA */ + 0x1114080a /* DENALI_PI_161_DATA */ + 0x00000f08 /* DENALI_PI_162_DATA */ + 0x2800fcc1 /* DENALI_PI_163_DATA */ + 0x0a0e2006 /* DENALI_PI_164_DATA */ + 0x1114080a /* DENALI_PI_165_DATA */ + 0x00000f08 /* DENALI_PI_166_DATA */ + 0x2800fcc1 /* DENALI_PI_167_DATA */ + 0x0a0e2006 /* DENALI_PI_168_DATA */ + 0x0200020a /* DENALI_PI_169_DATA */ + 0x02000200 /* DENALI_PI_170_DATA */ + 0x02000200 /* DENALI_PI_171_DATA */ + 0x02000200 /* DENALI_PI_172_DATA */ + 0x02000200 /* DENALI_PI_173_DATA */ + 0x00000000 /* DENALI_PI_174_DATA */ + 0x00000000 /* DENALI_PI_175_DATA */ + 0x00000000 /* DENALI_PI_176_DATA */ + 0x00000000 /* DENALI_PI_177_DATA */ + 0x00000000 /* DENALI_PI_178_DATA */ + 0x00000000 /* DENALI_PI_179_DATA */ + 0x00000000 /* DENALI_PI_180_DATA */ + 0x00000000 /* DENALI_PI_181_DATA */ + 0x00000000 /* DENALI_PI_182_DATA */ + 0x00000000 /* DENALI_PI_183_DATA */ + 0x00000000 /* DENALI_PI_184_DATA */ + 0x00000000 /* DENALI_PI_185_DATA */ + 0x01000300 /* DENALI_PI_186_DATA */ + 0x001c6200 /* DENALI_PI_187_DATA */ + 0x00011bd4 /* DENALI_PI_188_DATA */ + 0x00001c62 /* DENALI_PI_189_DATA */ + 0x00011bd4 /* DENALI_PI_190_DATA */ + 0x00001c62 /* DENALI_PI_191_DATA */ + 0x00011bd4 /* DENALI_PI_192_DATA */ + 0x08000000 /* DENALI_PI_193_DATA */ + 0x00000100 /* DENALI_PI_194_DATA */ + 0x00000000 /* DENALI_PI_195_DATA */ + 0x00000000 /* DENALI_PI_196_DATA */ + 0x00000000 /* DENALI_PI_197_DATA */ + 0x00000000 /* DENALI_PI_198_DATA */ + 0x00000002 /* DENALI_PI_199_DATA */ + + 0x76543210 /* DENALI_PHY_00_DATA */ + 0x0004c008 /* DENALI_PHY_01_DATA */ + 0x000001a2 /* DENALI_PHY_02_DATA */ + 0x00000000 /* DENALI_PHY_03_DATA */ + 0x00000000 /* DENALI_PHY_04_DATA */ + 0x00010000 /* DENALI_PHY_05_DATA */ + 0x01665555 /* DENALI_PHY_06_DATA */ + 0x00665555 /* DENALI_PHY_07_DATA */ + 0x00010f00 /* DENALI_PHY_08_DATA */ + 0x06010200 /* DENALI_PHY_09_DATA */ + 0x00000003 /* DENALI_PHY_10_DATA */ + 0x001700c0 /* DENALI_PHY_11_DATA */ + 0x00cc0101 /* DENALI_PHY_12_DATA */ + 0x00030066 /* DENALI_PHY_13_DATA */ + 0x00000000 /* DENALI_PHY_14_DATA */ + 0x00000000 /* DENALI_PHY_15_DATA */ + 0x00000000 /* DENALI_PHY_16_DATA */ + 0x00000000 /* DENALI_PHY_17_DATA */ + 0x00000000 /* DENALI_PHY_18_DATA */ + 0x00000000 /* DENALI_PHY_19_DATA */ + 0x00000000 /* DENALI_PHY_20_DATA */ + 0x00000000 /* DENALI_PHY_21_DATA */ + 0x04080000 /* DENALI_PHY_22_DATA */ + 0x04080400 /* DENALI_PHY_23_DATA */ + 0x08000000 /* DENALI_PHY_24_DATA */ + 0x0c00c007 /* DENALI_PHY_25_DATA */ + 0x00000100 /* DENALI_PHY_26_DATA */ + 0x00000100 /* DENALI_PHY_27_DATA */ + 0x55555555 /* DENALI_PHY_28_DATA */ + 0xaaaaaaaa /* DENALI_PHY_29_DATA */ + 0x55555555 /* DENALI_PHY_30_DATA */ + 0xaaaaaaaa /* DENALI_PHY_31_DATA */ + 0x00005555 /* DENALI_PHY_32_DATA */ + 0x00000000 /* DENALI_PHY_33_DATA */ + 0x00000000 /* DENALI_PHY_34_DATA */ + 0x00000000 /* DENALI_PHY_35_DATA */ + 0x00000000 /* DENALI_PHY_36_DATA */ + 0x00000000 /* DENALI_PHY_37_DATA */ + 0x00000000 /* DENALI_PHY_38_DATA */ + 0x00000000 /* DENALI_PHY_39_DATA */ + 0x00000000 /* DENALI_PHY_40_DATA */ + 0x00000000 /* DENALI_PHY_41_DATA */ + 0x00000000 /* DENALI_PHY_42_DATA */ + 0x00000000 /* DENALI_PHY_43_DATA */ + 0x00000000 /* DENALI_PHY_44_DATA */ + 0x00000000 /* DENALI_PHY_45_DATA */ + 0x00000000 /* DENALI_PHY_46_DATA */ + 0x00000000 /* DENALI_PHY_47_DATA */ + 0x00000000 /* DENALI_PHY_48_DATA */ + 0x00000000 /* DENALI_PHY_49_DATA */ + 0x00000000 /* DENALI_PHY_50_DATA */ + 0x00000000 /* DENALI_PHY_51_DATA */ + 0x00200000 /* DENALI_PHY_52_DATA */ + 0x00000000 /* DENALI_PHY_53_DATA */ + 0x00000000 /* DENALI_PHY_54_DATA */ + 0x00000000 /* DENALI_PHY_55_DATA */ + 0x00000000 /* DENALI_PHY_56_DATA */ + 0x00000000 /* DENALI_PHY_57_DATA */ + 0x00000000 /* DENALI_PHY_58_DATA */ + 0x02700270 /* DENALI_PHY_59_DATA */ + 0x02700270 /* DENALI_PHY_60_DATA */ + 0x02700270 /* DENALI_PHY_61_DATA */ + 0x02700270 /* DENALI_PHY_62_DATA */ + 0x00000270 /* DENALI_PHY_63_DATA */ + 0x00000000 /* DENALI_PHY_64_DATA */ + 0x00000000 /* DENALI_PHY_65_DATA */ + 0x00000000 /* DENALI_PHY_66_DATA */ + 0x00000000 /* DENALI_PHY_67_DATA */ + 0x00800000 /* DENALI_PHY_68_DATA */ + 0x00800080 /* DENALI_PHY_69_DATA */ + 0x00800080 /* DENALI_PHY_70_DATA */ + 0x00800080 /* DENALI_PHY_71_DATA */ + 0x00800080 /* DENALI_PHY_72_DATA */ + 0x00800080 /* DENALI_PHY_73_DATA */ + 0x00800080 /* DENALI_PHY_74_DATA */ + 0x00800080 /* DENALI_PHY_75_DATA */ + 0x00800080 /* DENALI_PHY_76_DATA */ + 0x01a20080 /* DENALI_PHY_77_DATA */ + 0x00000003 /* DENALI_PHY_78_DATA */ + 0x00000000 /* DENALI_PHY_79_DATA */ + 0x00030000 /* DENALI_PHY_80_DATA */ + 0x00000200 /* DENALI_PHY_81_DATA */ + 0x00000000 /* DENALI_PHY_82_DATA */ + 0x51315152 /* DENALI_PHY_83_DATA */ + 0xc0013150 /* DENALI_PHY_84_DATA */ + 0x020000c0 /* DENALI_PHY_85_DATA */ + 0x00100001 /* DENALI_PHY_86_DATA */ + 0x07064208 /* DENALI_PHY_87_DATA */ + 0x000f0c18 /* DENALI_PHY_88_DATA */ + 0x01000140 /* DENALI_PHY_89_DATA */ + 0x00000c20 /* DENALI_PHY_90_DATA */ + 0x00000000 /* DENALI_PHY_91_DATA */ + 0x00000000 /* DENALI_PHY_92_DATA */ + 0x00000000 /* DENALI_PHY_93_DATA */ + 0x00000000 /* DENALI_PHY_94_DATA */ + 0x00000000 /* DENALI_PHY_95_DATA */ + 0x00000000 /* DENALI_PHY_96_DATA */ + 0x00000000 /* DENALI_PHY_97_DATA */ + 0x00000000 /* DENALI_PHY_98_DATA */ + 0x00000000 /* DENALI_PHY_99_DATA */ + 0x00000000 /* DENALI_PHY_100_DATA */ + 0x00000000 /* DENALI_PHY_101_DATA */ + 0x00000000 /* DENALI_PHY_102_DATA */ + 0x00000000 /* DENALI_PHY_103_DATA */ + 0x00000000 /* DENALI_PHY_104_DATA */ + 0x00000000 /* DENALI_PHY_105_DATA */ + 0x00000000 /* DENALI_PHY_106_DATA */ + 0x00000000 /* DENALI_PHY_107_DATA */ + 0x00000000 /* DENALI_PHY_108_DATA */ + 0x00000000 /* DENALI_PHY_109_DATA */ + 0x00000000 /* DENALI_PHY_110_DATA */ + 0x00000000 /* DENALI_PHY_111_DATA */ + 0x00000000 /* DENALI_PHY_112_DATA */ + 0x00000000 /* DENALI_PHY_113_DATA */ + 0x00000000 /* DENALI_PHY_114_DATA */ + 0x00000000 /* DENALI_PHY_115_DATA */ + 0x00000000 /* DENALI_PHY_116_DATA */ + 0x00000000 /* DENALI_PHY_117_DATA */ + 0x00000000 /* DENALI_PHY_118_DATA */ + 0x00000000 /* DENALI_PHY_119_DATA */ + 0x00000000 /* DENALI_PHY_120_DATA */ + 0x00000000 /* DENALI_PHY_121_DATA */ + 0x00000000 /* DENALI_PHY_122_DATA */ + 0x00000000 /* DENALI_PHY_123_DATA */ + 0x00000000 /* DENALI_PHY_124_DATA */ + 0x00000000 /* DENALI_PHY_125_DATA */ + 0x00000000 /* DENALI_PHY_126_DATA */ + 0x00000000 /* DENALI_PHY_127_DATA */ + 0x76543210 /* DENALI_PHY_128_DATA */ + 0x0004c008 /* DENALI_PHY_129_DATA */ + 0x000001a2 /* DENALI_PHY_130_DATA */ + 0x00000000 /* DENALI_PHY_131_DATA */ + 0x00000000 /* DENALI_PHY_132_DATA */ + 0x00010000 /* DENALI_PHY_133_DATA */ + 0x01665555 /* DENALI_PHY_134_DATA */ + 0x00665555 /* DENALI_PHY_135_DATA */ + 0x00010f00 /* DENALI_PHY_136_DATA */ + 0x06010200 /* DENALI_PHY_137_DATA */ + 0x00000003 /* DENALI_PHY_138_DATA */ + 0x001700c0 /* DENALI_PHY_139_DATA */ + 0x00cc0101 /* DENALI_PHY_140_DATA */ + 0x00030066 /* DENALI_PHY_141_DATA */ + 0x00000000 /* DENALI_PHY_142_DATA */ + 0x00000000 /* DENALI_PHY_143_DATA */ + 0x00000000 /* DENALI_PHY_144_DATA */ + 0x00000000 /* DENALI_PHY_145_DATA */ + 0x00000000 /* DENALI_PHY_146_DATA */ + 0x00000000 /* DENALI_PHY_147_DATA */ + 0x00000000 /* DENALI_PHY_148_DATA */ + 0x00000000 /* DENALI_PHY_149_DATA */ + 0x04080000 /* DENALI_PHY_150_DATA */ + 0x04080400 /* DENALI_PHY_151_DATA */ + 0x08000000 /* DENALI_PHY_152_DATA */ + 0x0c00c007 /* DENALI_PHY_153_DATA */ + 0x00000100 /* DENALI_PHY_154_DATA */ + 0x00000100 /* DENALI_PHY_155_DATA */ + 0x55555555 /* DENALI_PHY_156_DATA */ + 0xaaaaaaaa /* DENALI_PHY_157_DATA */ + 0x55555555 /* DENALI_PHY_158_DATA */ + 0xaaaaaaaa /* DENALI_PHY_159_DATA */ + 0x00005555 /* DENALI_PHY_160_DATA */ + 0x00000000 /* DENALI_PHY_161_DATA */ + 0x00000000 /* DENALI_PHY_162_DATA */ + 0x00000000 /* DENALI_PHY_163_DATA */ + 0x00000000 /* DENALI_PHY_164_DATA */ + 0x00000000 /* DENALI_PHY_165_DATA */ + 0x00000000 /* DENALI_PHY_166_DATA */ + 0x00000000 /* DENALI_PHY_167_DATA */ + 0x00000000 /* DENALI_PHY_168_DATA */ + 0x00000000 /* DENALI_PHY_169_DATA */ + 0x00000000 /* DENALI_PHY_170_DATA */ + 0x00000000 /* DENALI_PHY_171_DATA */ + 0x00000000 /* DENALI_PHY_172_DATA */ + 0x00000000 /* DENALI_PHY_173_DATA */ + 0x00000000 /* DENALI_PHY_174_DATA */ + 0x00000000 /* DENALI_PHY_175_DATA */ + 0x00000000 /* DENALI_PHY_176_DATA */ + 0x00000000 /* DENALI_PHY_177_DATA */ + 0x00000000 /* DENALI_PHY_178_DATA */ + 0x00000000 /* DENALI_PHY_179_DATA */ + 0x00200000 /* DENALI_PHY_180_DATA */ + 0x00000000 /* DENALI_PHY_181_DATA */ + 0x00000000 /* DENALI_PHY_182_DATA */ + 0x00000000 /* DENALI_PHY_183_DATA */ + 0x00000000 /* DENALI_PHY_184_DATA */ + 0x00000000 /* DENALI_PHY_185_DATA */ + 0x00000000 /* DENALI_PHY_186_DATA */ + 0x02700270 /* DENALI_PHY_187_DATA */ + 0x02700270 /* DENALI_PHY_188_DATA */ + 0x02700270 /* DENALI_PHY_189_DATA */ + 0x02700270 /* DENALI_PHY_190_DATA */ + 0x00000270 /* DENALI_PHY_191_DATA */ + 0x00000000 /* DENALI_PHY_192_DATA */ + 0x00000000 /* DENALI_PHY_193_DATA */ + 0x00000000 /* DENALI_PHY_194_DATA */ + 0x00000000 /* DENALI_PHY_195_DATA */ + 0x00800000 /* DENALI_PHY_196_DATA */ + 0x00800080 /* DENALI_PHY_197_DATA */ + 0x00800080 /* DENALI_PHY_198_DATA */ + 0x00800080 /* DENALI_PHY_199_DATA */ + 0x00800080 /* DENALI_PHY_200_DATA */ + 0x00800080 /* DENALI_PHY_201_DATA */ + 0x00800080 /* DENALI_PHY_202_DATA */ + 0x00800080 /* DENALI_PHY_203_DATA */ + 0x00800080 /* DENALI_PHY_204_DATA */ + 0x01a20080 /* DENALI_PHY_205_DATA */ + 0x00000003 /* DENALI_PHY_206_DATA */ + 0x00000000 /* DENALI_PHY_207_DATA */ + 0x00030000 /* DENALI_PHY_208_DATA */ + 0x00000200 /* DENALI_PHY_209_DATA */ + 0x00000000 /* DENALI_PHY_210_DATA */ + 0x51315152 /* DENALI_PHY_211_DATA */ + 0xc0013150 /* DENALI_PHY_212_DATA */ + 0x020000c0 /* DENALI_PHY_213_DATA */ + 0x00100001 /* DENALI_PHY_214_DATA */ + 0x07064208 /* DENALI_PHY_215_DATA */ + 0x000f0c18 /* DENALI_PHY_216_DATA */ + 0x01000140 /* DENALI_PHY_217_DATA */ + 0x00000c20 /* DENALI_PHY_218_DATA */ + 0x00000000 /* DENALI_PHY_219_DATA */ + 0x00000000 /* DENALI_PHY_220_DATA */ + 0x00000000 /* DENALI_PHY_221_DATA */ + 0x00000000 /* DENALI_PHY_222_DATA */ + 0x00000000 /* DENALI_PHY_223_DATA */ + 0x00000000 /* DENALI_PHY_224_DATA */ + 0x00000000 /* DENALI_PHY_225_DATA */ + 0x00000000 /* DENALI_PHY_226_DATA */ + 0x00000000 /* DENALI_PHY_227_DATA */ + 0x00000000 /* DENALI_PHY_228_DATA */ + 0x00000000 /* DENALI_PHY_229_DATA */ + 0x00000000 /* DENALI_PHY_230_DATA */ + 0x00000000 /* DENALI_PHY_231_DATA */ + 0x00000000 /* DENALI_PHY_232_DATA */ + 0x00000000 /* DENALI_PHY_233_DATA */ + 0x00000000 /* DENALI_PHY_234_DATA */ + 0x00000000 /* DENALI_PHY_235_DATA */ + 0x00000000 /* DENALI_PHY_236_DATA */ + 0x00000000 /* DENALI_PHY_237_DATA */ + 0x00000000 /* DENALI_PHY_238_DATA */ + 0x00000000 /* DENALI_PHY_239_DATA */ + 0x00000000 /* DENALI_PHY_240_DATA */ + 0x00000000 /* DENALI_PHY_241_DATA */ + 0x00000000 /* DENALI_PHY_242_DATA */ + 0x00000000 /* DENALI_PHY_243_DATA */ + 0x00000000 /* DENALI_PHY_244_DATA */ + 0x00000000 /* DENALI_PHY_245_DATA */ + 0x00000000 /* DENALI_PHY_246_DATA */ + 0x00000000 /* DENALI_PHY_247_DATA */ + 0x00000000 /* DENALI_PHY_248_DATA */ + 0x00000000 /* DENALI_PHY_249_DATA */ + 0x00000000 /* DENALI_PHY_250_DATA */ + 0x00000000 /* DENALI_PHY_251_DATA */ + 0x00000000 /* DENALI_PHY_252_DATA */ + 0x00000000 /* DENALI_PHY_253_DATA */ + 0x00000000 /* DENALI_PHY_254_DATA */ + 0x00000000 /* DENALI_PHY_255_DATA */ + 0x76543210 /* DENALI_PHY_256_DATA */ + 0x0004c008 /* DENALI_PHY_257_DATA */ + 0x000001a2 /* DENALI_PHY_258_DATA */ + 0x00000000 /* DENALI_PHY_259_DATA */ + 0x00000000 /* DENALI_PHY_260_DATA */ + 0x00010000 /* DENALI_PHY_261_DATA */ + 0x01665555 /* DENALI_PHY_262_DATA */ + 0x00665555 /* DENALI_PHY_263_DATA */ + 0x00010f00 /* DENALI_PHY_264_DATA */ + 0x06010200 /* DENALI_PHY_265_DATA */ + 0x00000003 /* DENALI_PHY_266_DATA */ + 0x001700c0 /* DENALI_PHY_267_DATA */ + 0x00cc0101 /* DENALI_PHY_268_DATA */ + 0x00030066 /* DENALI_PHY_269_DATA */ + 0x00000000 /* DENALI_PHY_270_DATA */ + 0x00000000 /* DENALI_PHY_271_DATA */ + 0x00000000 /* DENALI_PHY_272_DATA */ + 0x00000000 /* DENALI_PHY_273_DATA */ + 0x00000000 /* DENALI_PHY_274_DATA */ + 0x00000000 /* DENALI_PHY_275_DATA */ + 0x00000000 /* DENALI_PHY_276_DATA */ + 0x00000000 /* DENALI_PHY_277_DATA */ + 0x04080000 /* DENALI_PHY_278_DATA */ + 0x04080400 /* DENALI_PHY_279_DATA */ + 0x08000000 /* DENALI_PHY_280_DATA */ + 0x0c00c007 /* DENALI_PHY_281_DATA */ + 0x00000100 /* DENALI_PHY_282_DATA */ + 0x00000100 /* DENALI_PHY_283_DATA */ + 0x55555555 /* DENALI_PHY_284_DATA */ + 0xaaaaaaaa /* DENALI_PHY_285_DATA */ + 0x55555555 /* DENALI_PHY_286_DATA */ + 0xaaaaaaaa /* DENALI_PHY_287_DATA */ + 0x00005555 /* DENALI_PHY_288_DATA */ + 0x00000000 /* DENALI_PHY_289_DATA */ + 0x00000000 /* DENALI_PHY_290_DATA */ + 0x00000000 /* DENALI_PHY_291_DATA */ + 0x00000000 /* DENALI_PHY_292_DATA */ + 0x00000000 /* DENALI_PHY_293_DATA */ + 0x00000000 /* DENALI_PHY_294_DATA */ + 0x00000000 /* DENALI_PHY_295_DATA */ + 0x00000000 /* DENALI_PHY_296_DATA */ + 0x00000000 /* DENALI_PHY_297_DATA */ + 0x00000000 /* DENALI_PHY_298_DATA */ + 0x00000000 /* DENALI_PHY_299_DATA */ + 0x00000000 /* DENALI_PHY_300_DATA */ + 0x00000000 /* DENALI_PHY_301_DATA */ + 0x00000000 /* DENALI_PHY_302_DATA */ + 0x00000000 /* DENALI_PHY_303_DATA */ + 0x00000000 /* DENALI_PHY_304_DATA */ + 0x00000000 /* DENALI_PHY_305_DATA */ + 0x00000000 /* DENALI_PHY_306_DATA */ + 0x00000000 /* DENALI_PHY_307_DATA */ + 0x00200000 /* DENALI_PHY_308_DATA */ + 0x00000000 /* DENALI_PHY_309_DATA */ + 0x00000000 /* DENALI_PHY_310_DATA */ + 0x00000000 /* DENALI_PHY_311_DATA */ + 0x00000000 /* DENALI_PHY_312_DATA */ + 0x00000000 /* DENALI_PHY_313_DATA */ + 0x00000000 /* DENALI_PHY_314_DATA */ + 0x02700270 /* DENALI_PHY_315_DATA */ + 0x02700270 /* DENALI_PHY_316_DATA */ + 0x02700270 /* DENALI_PHY_317_DATA */ + 0x02700270 /* DENALI_PHY_318_DATA */ + 0x00000270 /* DENALI_PHY_319_DATA */ + 0x00000000 /* DENALI_PHY_320_DATA */ + 0x00000000 /* DENALI_PHY_321_DATA */ + 0x00000000 /* DENALI_PHY_322_DATA */ + 0x00000000 /* DENALI_PHY_323_DATA */ + 0x00800000 /* DENALI_PHY_324_DATA */ + 0x00800080 /* DENALI_PHY_325_DATA */ + 0x00800080 /* DENALI_PHY_326_DATA */ + 0x00800080 /* DENALI_PHY_327_DATA */ + 0x00800080 /* DENALI_PHY_328_DATA */ + 0x00800080 /* DENALI_PHY_329_DATA */ + 0x00800080 /* DENALI_PHY_330_DATA */ + 0x00800080 /* DENALI_PHY_331_DATA */ + 0x00800080 /* DENALI_PHY_332_DATA */ + 0x01a20080 /* DENALI_PHY_333_DATA */ + 0x00000003 /* DENALI_PHY_334_DATA */ + 0x00000000 /* DENALI_PHY_335_DATA */ + 0x00030000 /* DENALI_PHY_336_DATA */ + 0x00000200 /* DENALI_PHY_337_DATA */ + 0x00000000 /* DENALI_PHY_338_DATA */ + 0x51315152 /* DENALI_PHY_339_DATA */ + 0xc0013150 /* DENALI_PHY_340_DATA */ + 0x020000c0 /* DENALI_PHY_341_DATA */ + 0x00100001 /* DENALI_PHY_342_DATA */ + 0x07064208 /* DENALI_PHY_343_DATA */ + 0x000f0c18 /* DENALI_PHY_344_DATA */ + 0x01000140 /* DENALI_PHY_345_DATA */ + 0x00000c20 /* DENALI_PHY_346_DATA */ + 0x00000000 /* DENALI_PHY_347_DATA */ + 0x00000000 /* DENALI_PHY_348_DATA */ + 0x00000000 /* DENALI_PHY_349_DATA */ + 0x00000000 /* DENALI_PHY_350_DATA */ + 0x00000000 /* DENALI_PHY_351_DATA */ + 0x00000000 /* DENALI_PHY_352_DATA */ + 0x00000000 /* DENALI_PHY_353_DATA */ + 0x00000000 /* DENALI_PHY_354_DATA */ + 0x00000000 /* DENALI_PHY_355_DATA */ + 0x00000000 /* DENALI_PHY_356_DATA */ + 0x00000000 /* DENALI_PHY_357_DATA */ + 0x00000000 /* DENALI_PHY_358_DATA */ + 0x00000000 /* DENALI_PHY_359_DATA */ + 0x00000000 /* DENALI_PHY_360_DATA */ + 0x00000000 /* DENALI_PHY_361_DATA */ + 0x00000000 /* DENALI_PHY_362_DATA */ + 0x00000000 /* DENALI_PHY_363_DATA */ + 0x00000000 /* DENALI_PHY_364_DATA */ + 0x00000000 /* DENALI_PHY_365_DATA */ + 0x00000000 /* DENALI_PHY_366_DATA */ + 0x00000000 /* DENALI_PHY_367_DATA */ + 0x00000000 /* DENALI_PHY_368_DATA */ + 0x00000000 /* DENALI_PHY_369_DATA */ + 0x00000000 /* DENALI_PHY_370_DATA */ + 0x00000000 /* DENALI_PHY_371_DATA */ + 0x00000000 /* DENALI_PHY_372_DATA */ + 0x00000000 /* DENALI_PHY_373_DATA */ + 0x00000000 /* DENALI_PHY_374_DATA */ + 0x00000000 /* DENALI_PHY_375_DATA */ + 0x00000000 /* DENALI_PHY_376_DATA */ + 0x00000000 /* DENALI_PHY_377_DATA */ + 0x00000000 /* DENALI_PHY_378_DATA */ + 0x00000000 /* DENALI_PHY_379_DATA */ + 0x00000000 /* DENALI_PHY_380_DATA */ + 0x00000000 /* DENALI_PHY_381_DATA */ + 0x00000000 /* DENALI_PHY_382_DATA */ + 0x00000000 /* DENALI_PHY_383_DATA */ + 0x76543210 /* DENALI_PHY_384_DATA */ + 0x0004c008 /* DENALI_PHY_385_DATA */ + 0x000001a2 /* DENALI_PHY_386_DATA */ + 0x00000000 /* DENALI_PHY_387_DATA */ + 0x00000000 /* DENALI_PHY_388_DATA */ + 0x00010000 /* DENALI_PHY_389_DATA */ + 0x01665555 /* DENALI_PHY_390_DATA */ + 0x00665555 /* DENALI_PHY_391_DATA */ + 0x00010f00 /* DENALI_PHY_392_DATA */ + 0x06010200 /* DENALI_PHY_393_DATA */ + 0x00000003 /* DENALI_PHY_394_DATA */ + 0x001700c0 /* DENALI_PHY_395_DATA */ + 0x00cc0101 /* DENALI_PHY_396_DATA */ + 0x00030066 /* DENALI_PHY_397_DATA */ + 0x00000000 /* DENALI_PHY_398_DATA */ + 0x00000000 /* DENALI_PHY_399_DATA */ + 0x00000000 /* DENALI_PHY_400_DATA */ + 0x00000000 /* DENALI_PHY_401_DATA */ + 0x00000000 /* DENALI_PHY_402_DATA */ + 0x00000000 /* DENALI_PHY_403_DATA */ + 0x00000000 /* DENALI_PHY_404_DATA */ + 0x00000000 /* DENALI_PHY_405_DATA */ + 0x04080000 /* DENALI_PHY_406_DATA */ + 0x04080400 /* DENALI_PHY_407_DATA */ + 0x08000000 /* DENALI_PHY_408_DATA */ + 0x0c00c007 /* DENALI_PHY_409_DATA */ + 0x00000100 /* DENALI_PHY_410_DATA */ + 0x00000100 /* DENALI_PHY_411_DATA */ + 0x55555555 /* DENALI_PHY_412_DATA */ + 0xaaaaaaaa /* DENALI_PHY_413_DATA */ + 0x55555555 /* DENALI_PHY_414_DATA */ + 0xaaaaaaaa /* DENALI_PHY_415_DATA */ + 0x00005555 /* DENALI_PHY_416_DATA */ + 0x00000000 /* DENALI_PHY_417_DATA */ + 0x00000000 /* DENALI_PHY_418_DATA */ + 0x00000000 /* DENALI_PHY_419_DATA */ + 0x00000000 /* DENALI_PHY_420_DATA */ + 0x00000000 /* DENALI_PHY_421_DATA */ + 0x00000000 /* DENALI_PHY_422_DATA */ + 0x00000000 /* DENALI_PHY_423_DATA */ + 0x00000000 /* DENALI_PHY_424_DATA */ + 0x00000000 /* DENALI_PHY_425_DATA */ + 0x00000000 /* DENALI_PHY_426_DATA */ + 0x00000000 /* DENALI_PHY_427_DATA */ + 0x00000000 /* DENALI_PHY_428_DATA */ + 0x00000000 /* DENALI_PHY_429_DATA */ + 0x00000000 /* DENALI_PHY_430_DATA */ + 0x00000000 /* DENALI_PHY_431_DATA */ + 0x00000000 /* DENALI_PHY_432_DATA */ + 0x00000000 /* DENALI_PHY_433_DATA */ + 0x00000000 /* DENALI_PHY_434_DATA */ + 0x00000000 /* DENALI_PHY_435_DATA */ + 0x00200000 /* DENALI_PHY_436_DATA */ + 0x00000000 /* DENALI_PHY_437_DATA */ + 0x00000000 /* DENALI_PHY_438_DATA */ + 0x00000000 /* DENALI_PHY_439_DATA */ + 0x00000000 /* DENALI_PHY_440_DATA */ + 0x00000000 /* DENALI_PHY_441_DATA */ + 0x00000000 /* DENALI_PHY_442_DATA */ + 0x02700270 /* DENALI_PHY_443_DATA */ + 0x02700270 /* DENALI_PHY_444_DATA */ + 0x02700270 /* DENALI_PHY_445_DATA */ + 0x02700270 /* DENALI_PHY_446_DATA */ + 0x00000270 /* DENALI_PHY_447_DATA */ + 0x00000000 /* DENALI_PHY_448_DATA */ + 0x00000000 /* DENALI_PHY_449_DATA */ + 0x00000000 /* DENALI_PHY_450_DATA */ + 0x00000000 /* DENALI_PHY_451_DATA */ + 0x00800000 /* DENALI_PHY_452_DATA */ + 0x00800080 /* DENALI_PHY_453_DATA */ + 0x00800080 /* DENALI_PHY_454_DATA */ + 0x00800080 /* DENALI_PHY_455_DATA */ + 0x00800080 /* DENALI_PHY_456_DATA */ + 0x00800080 /* DENALI_PHY_457_DATA */ + 0x00800080 /* DENALI_PHY_458_DATA */ + 0x00800080 /* DENALI_PHY_459_DATA */ + 0x00800080 /* DENALI_PHY_460_DATA */ + 0x01a20080 /* DENALI_PHY_461_DATA */ + 0x00000003 /* DENALI_PHY_462_DATA */ + 0x00000000 /* DENALI_PHY_463_DATA */ + 0x00030000 /* DENALI_PHY_464_DATA */ + 0x00000200 /* DENALI_PHY_465_DATA */ + 0x00000000 /* DENALI_PHY_466_DATA */ + 0x51315152 /* DENALI_PHY_467_DATA */ + 0xc0013150 /* DENALI_PHY_468_DATA */ + 0x020000c0 /* DENALI_PHY_469_DATA */ + 0x00100001 /* DENALI_PHY_470_DATA */ + 0x07064208 /* DENALI_PHY_471_DATA */ + 0x000f0c18 /* DENALI_PHY_472_DATA */ + 0x01000140 /* DENALI_PHY_473_DATA */ + 0x00000c20 /* DENALI_PHY_474_DATA */ + 0x00000000 /* DENALI_PHY_475_DATA */ + 0x00000000 /* DENALI_PHY_476_DATA */ + 0x00000000 /* DENALI_PHY_477_DATA */ + 0x00000000 /* DENALI_PHY_478_DATA */ + 0x00000000 /* DENALI_PHY_479_DATA */ + 0x00000000 /* DENALI_PHY_480_DATA */ + 0x00000000 /* DENALI_PHY_481_DATA */ + 0x00000000 /* DENALI_PHY_482_DATA */ + 0x00000000 /* DENALI_PHY_483_DATA */ + 0x00000000 /* DENALI_PHY_484_DATA */ + 0x00000000 /* DENALI_PHY_485_DATA */ + 0x00000000 /* DENALI_PHY_486_DATA */ + 0x00000000 /* DENALI_PHY_487_DATA */ + 0x00000000 /* DENALI_PHY_488_DATA */ + 0x00000000 /* DENALI_PHY_489_DATA */ + 0x00000000 /* DENALI_PHY_490_DATA */ + 0x00000000 /* DENALI_PHY_491_DATA */ + 0x00000000 /* DENALI_PHY_492_DATA */ + 0x00000000 /* DENALI_PHY_493_DATA */ + 0x00000000 /* DENALI_PHY_494_DATA */ + 0x00000000 /* DENALI_PHY_495_DATA */ + 0x00000000 /* DENALI_PHY_496_DATA */ + 0x00000000 /* DENALI_PHY_497_DATA */ + 0x00000000 /* DENALI_PHY_498_DATA */ + 0x00000000 /* DENALI_PHY_499_DATA */ + 0x00000000 /* DENALI_PHY_500_DATA */ + 0x00000000 /* DENALI_PHY_501_DATA */ + 0x00000000 /* DENALI_PHY_502_DATA */ + 0x00000000 /* DENALI_PHY_503_DATA */ + 0x00000000 /* DENALI_PHY_504_DATA */ + 0x00000000 /* DENALI_PHY_505_DATA */ + 0x00000000 /* DENALI_PHY_506_DATA */ + 0x00000000 /* DENALI_PHY_507_DATA */ + 0x00000000 /* DENALI_PHY_508_DATA */ + 0x00000000 /* DENALI_PHY_509_DATA */ + 0x00000000 /* DENALI_PHY_510_DATA */ + 0x00000000 /* DENALI_PHY_511_DATA */ + 0x00000000 /* DENALI_PHY_512_DATA */ + 0x00800000 /* DENALI_PHY_513_DATA */ + 0x00000000 /* DENALI_PHY_514_DATA */ + 0x00000000 /* DENALI_PHY_515_DATA */ + 0x00000000 /* DENALI_PHY_516_DATA */ + 0x00000000 /* DENALI_PHY_517_DATA */ + 0x00000000 /* DENALI_PHY_518_DATA */ + 0x00000001 /* DENALI_PHY_519_DATA */ + 0x00000000 /* DENALI_PHY_520_DATA */ + 0x00000000 /* DENALI_PHY_521_DATA */ + 0x00000000 /* DENALI_PHY_522_DATA */ + 0x00400320 /* DENALI_PHY_523_DATA */ + 0x00000040 /* DENALI_PHY_524_DATA */ + 0x00806420 /* DENALI_PHY_525_DATA */ + 0x00917531 /* DENALI_PHY_526_DATA */ + 0x00806420 /* DENALI_PHY_527_DATA */ + 0x01917531 /* DENALI_PHY_528_DATA */ + 0x02020003 /* DENALI_PHY_529_DATA */ + 0x00000000 /* DENALI_PHY_530_DATA */ + 0x00000000 /* DENALI_PHY_531_DATA */ + 0x00000000 /* DENALI_PHY_532_DATA */ + 0x000fffff /* DENALI_PHY_533_DATA */ + 0x00000000 /* DENALI_PHY_534_DATA */ + 0x000556aa /* DENALI_PHY_535_DATA */ + 0x000aaaaa /* DENALI_PHY_536_DATA */ + 0x000b3133 /* DENALI_PHY_537_DATA */ + 0x0004cd33 /* DENALI_PHY_538_DATA */ + 0x0004cecc /* DENALI_PHY_539_DATA */ + 0x000b32cc /* DENALI_PHY_540_DATA */ + 0x0a418820 /* DENALI_PHY_541_DATA */ + 0x103f0000 /* DENALI_PHY_542_DATA */ + 0x0000003f /* DENALI_PHY_543_DATA */ + 0x00038055 /* DENALI_PHY_544_DATA */ + 0x03800380 /* DENALI_PHY_545_DATA */ + 0x03800380 /* DENALI_PHY_546_DATA */ + 0x00000380 /* DENALI_PHY_547_DATA */ + 0x42080010 /* DENALI_PHY_548_DATA */ + 0x00000003 /* DENALI_PHY_549_DATA */ + 0x00000000 /* DENALI_PHY_550_DATA */ + 0x00000000 /* DENALI_PHY_551_DATA */ + 0x00000000 /* DENALI_PHY_552_DATA */ + 0x00000000 /* DENALI_PHY_553_DATA */ + 0x00000000 /* DENALI_PHY_554_DATA */ + 0x00000000 /* DENALI_PHY_555_DATA */ + 0x00000000 /* DENALI_PHY_556_DATA */ + 0x00000000 /* DENALI_PHY_557_DATA */ + 0x00000000 /* DENALI_PHY_558_DATA */ + 0x00000000 /* DENALI_PHY_559_DATA */ + 0x00000000 /* DENALI_PHY_560_DATA */ + 0x00000000 /* DENALI_PHY_561_DATA */ + 0x00000000 /* DENALI_PHY_562_DATA */ + 0x00000000 /* DENALI_PHY_563_DATA */ + 0x00000000 /* DENALI_PHY_564_DATA */ + 0x00000000 /* DENALI_PHY_565_DATA */ + 0x00000000 /* DENALI_PHY_566_DATA */ + 0x00000000 /* DENALI_PHY_567_DATA */ + 0x00000000 /* DENALI_PHY_568_DATA */ + 0x00000000 /* DENALI_PHY_569_DATA */ + 0x00000000 /* DENALI_PHY_570_DATA */ + 0x00000000 /* DENALI_PHY_571_DATA */ + 0x00000000 /* DENALI_PHY_572_DATA */ + 0x00000000 /* DENALI_PHY_573_DATA */ + 0x00000000 /* DENALI_PHY_574_DATA */ + 0x00000000 /* DENALI_PHY_575_DATA */ + 0x00000000 /* DENALI_PHY_576_DATA */ + 0x00000000 /* DENALI_PHY_577_DATA */ + 0x00000000 /* DENALI_PHY_578_DATA */ + 0x00000000 /* DENALI_PHY_579_DATA */ + 0x00000000 /* DENALI_PHY_580_DATA */ + 0x00000000 /* DENALI_PHY_581_DATA */ + 0x00000000 /* DENALI_PHY_582_DATA */ + 0x00000000 /* DENALI_PHY_583_DATA */ + 0x00000000 /* DENALI_PHY_584_DATA */ + 0x00000000 /* DENALI_PHY_585_DATA */ + 0x00000000 /* DENALI_PHY_586_DATA */ + 0x00000000 /* DENALI_PHY_587_DATA */ + 0x00000000 /* DENALI_PHY_588_DATA */ + 0x00000000 /* DENALI_PHY_589_DATA */ + 0x00000000 /* DENALI_PHY_590_DATA */ + 0x00000000 /* DENALI_PHY_591_DATA */ + 0x00000000 /* DENALI_PHY_592_DATA */ + 0x00000000 /* DENALI_PHY_593_DATA */ + 0x00000000 /* DENALI_PHY_594_DATA */ + 0x00000000 /* DENALI_PHY_595_DATA */ + 0x00000000 /* DENALI_PHY_596_DATA */ + 0x00000000 /* DENALI_PHY_597_DATA */ + 0x00000000 /* DENALI_PHY_598_DATA */ + 0x00000000 /* DENALI_PHY_599_DATA */ + 0x00000000 /* DENALI_PHY_600_DATA */ + 0x00000000 /* DENALI_PHY_601_DATA */ + 0x00000000 /* DENALI_PHY_602_DATA */ + 0x00000000 /* DENALI_PHY_603_DATA */ + 0x00000000 /* DENALI_PHY_604_DATA */ + 0x00000000 /* DENALI_PHY_605_DATA */ + 0x00000000 /* DENALI_PHY_606_DATA */ + 0x00000000 /* DENALI_PHY_607_DATA */ + 0x00000000 /* DENALI_PHY_608_DATA */ + 0x00000000 /* DENALI_PHY_609_DATA */ + 0x00000000 /* DENALI_PHY_610_DATA */ + 0x00000000 /* DENALI_PHY_611_DATA */ + 0x00000000 /* DENALI_PHY_612_DATA */ + 0x00000000 /* DENALI_PHY_613_DATA */ + 0x00000000 /* DENALI_PHY_614_DATA */ + 0x00000000 /* DENALI_PHY_615_DATA */ + 0x00000000 /* DENALI_PHY_616_DATA */ + 0x00000000 /* DENALI_PHY_617_DATA */ + 0x00000000 /* DENALI_PHY_618_DATA */ + 0x00000000 /* DENALI_PHY_619_DATA */ + 0x00000000 /* DENALI_PHY_620_DATA */ + 0x00000000 /* DENALI_PHY_621_DATA */ + 0x00000000 /* DENALI_PHY_622_DATA */ + 0x00000000 /* DENALI_PHY_623_DATA */ + 0x00000000 /* DENALI_PHY_624_DATA */ + 0x00000000 /* DENALI_PHY_625_DATA */ + 0x00000000 /* DENALI_PHY_626_DATA */ + 0x00000000 /* DENALI_PHY_627_DATA */ + 0x00000000 /* DENALI_PHY_628_DATA */ + 0x00000000 /* DENALI_PHY_629_DATA */ + 0x00000000 /* DENALI_PHY_630_DATA */ + 0x00000000 /* DENALI_PHY_631_DATA */ + 0x00000000 /* DENALI_PHY_632_DATA */ + 0x00000000 /* DENALI_PHY_633_DATA */ + 0x00000000 /* DENALI_PHY_634_DATA */ + 0x00000000 /* DENALI_PHY_635_DATA */ + 0x00000000 /* DENALI_PHY_636_DATA */ + 0x00000000 /* DENALI_PHY_637_DATA */ + 0x00000000 /* DENALI_PHY_638_DATA */ + 0x00000000 /* DENALI_PHY_639_DATA */ + 0x00000000 /* DENALI_PHY_640_DATA */ + 0x00800000 /* DENALI_PHY_641_DATA */ + 0x00000000 /* DENALI_PHY_642_DATA */ + 0x00000000 /* DENALI_PHY_643_DATA */ + 0x00000000 /* DENALI_PHY_644_DATA */ + 0x00000000 /* DENALI_PHY_645_DATA */ + 0x00000000 /* DENALI_PHY_646_DATA */ + 0x00000001 /* DENALI_PHY_647_DATA */ + 0x00000000 /* DENALI_PHY_648_DATA */ + 0x00000000 /* DENALI_PHY_649_DATA */ + 0x00000000 /* DENALI_PHY_650_DATA */ + 0x00400320 /* DENALI_PHY_651_DATA */ + 0x00000040 /* DENALI_PHY_652_DATA */ + 0x00008eca /* DENALI_PHY_653_DATA */ + 0x00009fdb /* DENALI_PHY_654_DATA */ + 0x00008eca /* DENALI_PHY_655_DATA */ + 0x01009fdb /* DENALI_PHY_656_DATA */ + 0x02020003 /* DENALI_PHY_657_DATA */ + 0x00000000 /* DENALI_PHY_658_DATA */ + 0x00000000 /* DENALI_PHY_659_DATA */ + 0x00000000 /* DENALI_PHY_660_DATA */ + 0x000fffff /* DENALI_PHY_661_DATA */ + 0x00000000 /* DENALI_PHY_662_DATA */ + 0x000556aa /* DENALI_PHY_663_DATA */ + 0x000aaaaa /* DENALI_PHY_664_DATA */ + 0x000b3133 /* DENALI_PHY_665_DATA */ + 0x0004cd33 /* DENALI_PHY_666_DATA */ + 0x0004cecc /* DENALI_PHY_667_DATA */ + 0x000b32cc /* DENALI_PHY_668_DATA */ + 0x0004a0e6 /* DENALI_PHY_669_DATA */ + 0x080f0000 /* DENALI_PHY_670_DATA */ + 0x0000000f /* DENALI_PHY_671_DATA */ + 0x00038055 /* DENALI_PHY_672_DATA */ + 0x03800380 /* DENALI_PHY_673_DATA */ + 0x03800380 /* DENALI_PHY_674_DATA */ + 0x00000380 /* DENALI_PHY_675_DATA */ + 0x42080010 /* DENALI_PHY_676_DATA */ + 0x00000003 /* DENALI_PHY_677_DATA */ + 0x00000000 /* DENALI_PHY_678_DATA */ + 0x00000000 /* DENALI_PHY_679_DATA */ + 0x00000000 /* DENALI_PHY_680_DATA */ + 0x00000000 /* DENALI_PHY_681_DATA */ + 0x00000000 /* DENALI_PHY_682_DATA */ + 0x00000000 /* DENALI_PHY_683_DATA */ + 0x00000000 /* DENALI_PHY_684_DATA */ + 0x00000000 /* DENALI_PHY_685_DATA */ + 0x00000000 /* DENALI_PHY_686_DATA */ + 0x00000000 /* DENALI_PHY_687_DATA */ + 0x00000000 /* DENALI_PHY_688_DATA */ + 0x00000000 /* DENALI_PHY_689_DATA */ + 0x00000000 /* DENALI_PHY_690_DATA */ + 0x00000000 /* DENALI_PHY_691_DATA */ + 0x00000000 /* DENALI_PHY_692_DATA */ + 0x00000000 /* DENALI_PHY_693_DATA */ + 0x00000000 /* DENALI_PHY_694_DATA */ + 0x00000000 /* DENALI_PHY_695_DATA */ + 0x00000000 /* DENALI_PHY_696_DATA */ + 0x00000000 /* DENALI_PHY_697_DATA */ + 0x00000000 /* DENALI_PHY_698_DATA */ + 0x00000000 /* DENALI_PHY_699_DATA */ + 0x00000000 /* DENALI_PHY_700_DATA */ + 0x00000000 /* DENALI_PHY_701_DATA */ + 0x00000000 /* DENALI_PHY_702_DATA */ + 0x00000000 /* DENALI_PHY_703_DATA */ + 0x00000000 /* DENALI_PHY_704_DATA */ + 0x00000000 /* DENALI_PHY_705_DATA */ + 0x00000000 /* DENALI_PHY_706_DATA */ + 0x00000000 /* DENALI_PHY_707_DATA */ + 0x00000000 /* DENALI_PHY_708_DATA */ + 0x00000000 /* DENALI_PHY_709_DATA */ + 0x00000000 /* DENALI_PHY_710_DATA */ + 0x00000000 /* DENALI_PHY_711_DATA */ + 0x00000000 /* DENALI_PHY_712_DATA */ + 0x00000000 /* DENALI_PHY_713_DATA */ + 0x00000000 /* DENALI_PHY_714_DATA */ + 0x00000000 /* DENALI_PHY_715_DATA */ + 0x00000000 /* DENALI_PHY_716_DATA */ + 0x00000000 /* DENALI_PHY_717_DATA */ + 0x00000000 /* DENALI_PHY_718_DATA */ + 0x00000000 /* DENALI_PHY_719_DATA */ + 0x00000000 /* DENALI_PHY_720_DATA */ + 0x00000000 /* DENALI_PHY_721_DATA */ + 0x00000000 /* DENALI_PHY_722_DATA */ + 0x00000000 /* DENALI_PHY_723_DATA */ + 0x00000000 /* DENALI_PHY_724_DATA */ + 0x00000000 /* DENALI_PHY_725_DATA */ + 0x00000000 /* DENALI_PHY_726_DATA */ + 0x00000000 /* DENALI_PHY_727_DATA */ + 0x00000000 /* DENALI_PHY_728_DATA */ + 0x00000000 /* DENALI_PHY_729_DATA */ + 0x00000000 /* DENALI_PHY_730_DATA */ + 0x00000000 /* DENALI_PHY_731_DATA */ + 0x00000000 /* DENALI_PHY_732_DATA */ + 0x00000000 /* DENALI_PHY_733_DATA */ + 0x00000000 /* DENALI_PHY_734_DATA */ + 0x00000000 /* DENALI_PHY_735_DATA */ + 0x00000000 /* DENALI_PHY_736_DATA */ + 0x00000000 /* DENALI_PHY_737_DATA */ + 0x00000000 /* DENALI_PHY_738_DATA */ + 0x00000000 /* DENALI_PHY_739_DATA */ + 0x00000000 /* DENALI_PHY_740_DATA */ + 0x00000000 /* DENALI_PHY_741_DATA */ + 0x00000000 /* DENALI_PHY_742_DATA */ + 0x00000000 /* DENALI_PHY_743_DATA */ + 0x00000000 /* DENALI_PHY_744_DATA */ + 0x00000000 /* DENALI_PHY_745_DATA */ + 0x00000000 /* DENALI_PHY_746_DATA */ + 0x00000000 /* DENALI_PHY_747_DATA */ + 0x00000000 /* DENALI_PHY_748_DATA */ + 0x00000000 /* DENALI_PHY_749_DATA */ + 0x00000000 /* DENALI_PHY_750_DATA */ + 0x00000000 /* DENALI_PHY_751_DATA */ + 0x00000000 /* DENALI_PHY_752_DATA */ + 0x00000000 /* DENALI_PHY_753_DATA */ + 0x00000000 /* DENALI_PHY_754_DATA */ + 0x00000000 /* DENALI_PHY_755_DATA */ + 0x00000000 /* DENALI_PHY_756_DATA */ + 0x00000000 /* DENALI_PHY_757_DATA */ + 0x00000000 /* DENALI_PHY_758_DATA */ + 0x00000000 /* DENALI_PHY_759_DATA */ + 0x00000000 /* DENALI_PHY_760_DATA */ + 0x00000000 /* DENALI_PHY_761_DATA */ + 0x00000000 /* DENALI_PHY_762_DATA */ + 0x00000000 /* DENALI_PHY_763_DATA */ + 0x00000000 /* DENALI_PHY_764_DATA */ + 0x00000000 /* DENALI_PHY_765_DATA */ + 0x00000000 /* DENALI_PHY_766_DATA */ + 0x00000000 /* DENALI_PHY_767_DATA */ + 0x00000000 /* DENALI_PHY_768_DATA */ + 0x00800000 /* DENALI_PHY_769_DATA */ + 0x00000000 /* DENALI_PHY_770_DATA */ + 0x00000000 /* DENALI_PHY_771_DATA */ + 0x00000000 /* DENALI_PHY_772_DATA */ + 0x00000000 /* DENALI_PHY_773_DATA */ + 0x00000000 /* DENALI_PHY_774_DATA */ + 0x00000001 /* DENALI_PHY_775_DATA */ + 0x00000000 /* DENALI_PHY_776_DATA */ + 0x00000000 /* DENALI_PHY_777_DATA */ + 0x00000000 /* DENALI_PHY_778_DATA */ + 0x00400320 /* DENALI_PHY_779_DATA */ + 0x00000040 /* DENALI_PHY_780_DATA */ + 0x00008eca /* DENALI_PHY_781_DATA */ + 0x00009fdb /* DENALI_PHY_782_DATA */ + 0x00008eca /* DENALI_PHY_783_DATA */ + 0x01009fdb /* DENALI_PHY_784_DATA */ + 0x02020003 /* DENALI_PHY_785_DATA */ + 0x00000000 /* DENALI_PHY_786_DATA */ + 0x00000000 /* DENALI_PHY_787_DATA */ + 0x00000000 /* DENALI_PHY_788_DATA */ + 0x000fffff /* DENALI_PHY_789_DATA */ + 0x00000000 /* DENALI_PHY_790_DATA */ + 0x000556aa /* DENALI_PHY_791_DATA */ + 0x000aaaaa /* DENALI_PHY_792_DATA */ + 0x000b3133 /* DENALI_PHY_793_DATA */ + 0x0004cd33 /* DENALI_PHY_794_DATA */ + 0x0004cecc /* DENALI_PHY_795_DATA */ + 0x000b32cc /* DENALI_PHY_796_DATA */ + 0x1ee6b16a /* DENALI_PHY_797_DATA */ + 0x10000000 /* DENALI_PHY_798_DATA */ + 0x00000000 /* DENALI_PHY_799_DATA */ + 0x00038055 /* DENALI_PHY_800_DATA */ + 0x03800380 /* DENALI_PHY_801_DATA */ + 0x03800380 /* DENALI_PHY_802_DATA */ + 0x00000380 /* DENALI_PHY_803_DATA */ + 0x42080010 /* DENALI_PHY_804_DATA */ + 0x00000003 /* DENALI_PHY_805_DATA */ + 0x00000000 /* DENALI_PHY_806_DATA */ + 0x00000000 /* DENALI_PHY_807_DATA */ + 0x00000000 /* DENALI_PHY_808_DATA */ + 0x00000000 /* DENALI_PHY_809_DATA */ + 0x00000000 /* DENALI_PHY_810_DATA */ + 0x00000000 /* DENALI_PHY_811_DATA */ + 0x00000000 /* DENALI_PHY_812_DATA */ + 0x00000000 /* DENALI_PHY_813_DATA */ + 0x00000000 /* DENALI_PHY_814_DATA */ + 0x00000000 /* DENALI_PHY_815_DATA */ + 0x00000000 /* DENALI_PHY_816_DATA */ + 0x00000000 /* DENALI_PHY_817_DATA */ + 0x00000000 /* DENALI_PHY_818_DATA */ + 0x00000000 /* DENALI_PHY_819_DATA */ + 0x00000000 /* DENALI_PHY_820_DATA */ + 0x00000000 /* DENALI_PHY_821_DATA */ + 0x00000000 /* DENALI_PHY_822_DATA */ + 0x00000000 /* DENALI_PHY_823_DATA */ + 0x00000000 /* DENALI_PHY_824_DATA */ + 0x00000000 /* DENALI_PHY_825_DATA */ + 0x00000000 /* DENALI_PHY_826_DATA */ + 0x00000000 /* DENALI_PHY_827_DATA */ + 0x00000000 /* DENALI_PHY_828_DATA */ + 0x00000000 /* DENALI_PHY_829_DATA */ + 0x00000000 /* DENALI_PHY_830_DATA */ + 0x00000000 /* DENALI_PHY_831_DATA */ + 0x00000000 /* DENALI_PHY_832_DATA */ + 0x00000000 /* DENALI_PHY_833_DATA */ + 0x00000000 /* DENALI_PHY_834_DATA */ + 0x00000000 /* DENALI_PHY_835_DATA */ + 0x00000000 /* DENALI_PHY_836_DATA */ + 0x00000000 /* DENALI_PHY_837_DATA */ + 0x00000000 /* DENALI_PHY_838_DATA */ + 0x00000000 /* DENALI_PHY_839_DATA */ + 0x00000000 /* DENALI_PHY_840_DATA */ + 0x00000000 /* DENALI_PHY_841_DATA */ + 0x00000000 /* DENALI_PHY_842_DATA */ + 0x00000000 /* DENALI_PHY_843_DATA */ + 0x00000000 /* DENALI_PHY_844_DATA */ + 0x00000000 /* DENALI_PHY_845_DATA */ + 0x00000000 /* DENALI_PHY_846_DATA */ + 0x00000000 /* DENALI_PHY_847_DATA */ + 0x00000000 /* DENALI_PHY_848_DATA */ + 0x00000000 /* DENALI_PHY_849_DATA */ + 0x00000000 /* DENALI_PHY_850_DATA */ + 0x00000000 /* DENALI_PHY_851_DATA */ + 0x00000000 /* DENALI_PHY_852_DATA */ + 0x00000000 /* DENALI_PHY_853_DATA */ + 0x00000000 /* DENALI_PHY_854_DATA */ + 0x00000000 /* DENALI_PHY_855_DATA */ + 0x00000000 /* DENALI_PHY_856_DATA */ + 0x00000000 /* DENALI_PHY_857_DATA */ + 0x00000000 /* DENALI_PHY_858_DATA */ + 0x00000000 /* DENALI_PHY_859_DATA */ + 0x00000000 /* DENALI_PHY_860_DATA */ + 0x00000000 /* DENALI_PHY_861_DATA */ + 0x00000000 /* DENALI_PHY_862_DATA */ + 0x00000000 /* DENALI_PHY_863_DATA */ + 0x00000000 /* DENALI_PHY_864_DATA */ + 0x00000000 /* DENALI_PHY_865_DATA */ + 0x00000000 /* DENALI_PHY_866_DATA */ + 0x00000000 /* DENALI_PHY_867_DATA */ + 0x00000000 /* DENALI_PHY_868_DATA */ + 0x00000000 /* DENALI_PHY_869_DATA */ + 0x00000000 /* DENALI_PHY_870_DATA */ + 0x00000000 /* DENALI_PHY_871_DATA */ + 0x00000000 /* DENALI_PHY_872_DATA */ + 0x00000000 /* DENALI_PHY_873_DATA */ + 0x00000000 /* DENALI_PHY_874_DATA */ + 0x00000000 /* DENALI_PHY_875_DATA */ + 0x00000000 /* DENALI_PHY_876_DATA */ + 0x00000000 /* DENALI_PHY_877_DATA */ + 0x00000000 /* DENALI_PHY_878_DATA */ + 0x00000000 /* DENALI_PHY_879_DATA */ + 0x00000000 /* DENALI_PHY_880_DATA */ + 0x00000000 /* DENALI_PHY_881_DATA */ + 0x00000000 /* DENALI_PHY_882_DATA */ + 0x00000000 /* DENALI_PHY_883_DATA */ + 0x00000000 /* DENALI_PHY_884_DATA */ + 0x00000000 /* DENALI_PHY_885_DATA */ + 0x00000000 /* DENALI_PHY_886_DATA */ + 0x00000000 /* DENALI_PHY_887_DATA */ + 0x00000000 /* DENALI_PHY_888_DATA */ + 0x00000000 /* DENALI_PHY_889_DATA */ + 0x00000000 /* DENALI_PHY_890_DATA */ + 0x00000000 /* DENALI_PHY_891_DATA */ + 0x00000000 /* DENALI_PHY_892_DATA */ + 0x00000000 /* DENALI_PHY_893_DATA */ + 0x00000000 /* DENALI_PHY_894_DATA */ + 0x00000000 /* DENALI_PHY_895_DATA */ + 0x00000001 /* DENALI_PHY_896_DATA */ + 0x00000000 /* DENALI_PHY_897_DATA */ + 0x01000005 /* DENALI_PHY_898_DATA */ + 0x04000f00 /* DENALI_PHY_899_DATA */ + 0x00020040 /* DENALI_PHY_900_DATA */ + 0x00020055 /* DENALI_PHY_901_DATA */ + 0x00000000 /* DENALI_PHY_902_DATA */ + 0x00000000 /* DENALI_PHY_903_DATA */ + 0x00000000 /* DENALI_PHY_904_DATA */ + 0x00000050 /* DENALI_PHY_905_DATA */ + 0x00000000 /* DENALI_PHY_906_DATA */ + 0x00010100 /* DENALI_PHY_907_DATA */ + 0x00000601 /* DENALI_PHY_908_DATA */ + 0x00000000 /* DENALI_PHY_909_DATA */ + 0x00006400 /* DENALI_PHY_910_DATA */ + 0x01221102 /* DENALI_PHY_911_DATA */ + 0x00000000 /* DENALI_PHY_912_DATA */ + 0x00051f00 /* DENALI_PHY_913_DATA */ + 0x051f051f /* DENALI_PHY_914_DATA */ + 0x051f051f /* DENALI_PHY_915_DATA */ + 0x00030003 /* DENALI_PHY_916_DATA */ + 0x03000300 /* DENALI_PHY_917_DATA */ + 0x00000300 /* DENALI_PHY_918_DATA */ + 0x01221102 /* DENALI_PHY_919_DATA */ + 0x00000000 /* DENALI_PHY_920_DATA */ + 0x00000000 /* DENALI_PHY_921_DATA */ + 0x04020000 /* DENALI_PHY_922_DATA */ + 0x00000001 /* DENALI_PHY_923_DATA */ + 0x00000011 /* DENALI_PHY_924_DATA */ + 0x00000011 /* DENALI_PHY_925_DATA */ + 0x00000400 /* DENALI_PHY_926_DATA */ + 0x00000000 /* DENALI_PHY_927_DATA */ + 0x00000011 /* DENALI_PHY_928_DATA */ + 0x00000011 /* DENALI_PHY_929_DATA */ + 0x00004410 /* DENALI_PHY_930_DATA */ + 0x00004410 /* DENALI_PHY_931_DATA */ + 0x00004410 /* DENALI_PHY_932_DATA */ + 0x00004410 /* DENALI_PHY_933_DATA */ + 0x00004410 /* DENALI_PHY_934_DATA */ + 0x00000011 /* DENALI_PHY_935_DATA */ + 0x00004410 /* DENALI_PHY_936_DATA */ + 0x00000011 /* DENALI_PHY_937_DATA */ + 0x00004410 /* DENALI_PHY_938_DATA */ + 0x00000011 /* DENALI_PHY_939_DATA */ + 0x00004410 /* DENALI_PHY_940_DATA */ + 0x00000000 /* DENALI_PHY_941_DATA */ + 0x00000000 /* DENALI_PHY_942_DATA */ + 0x00000000 /* DENALI_PHY_943_DATA */ + 0x04000000 /* DENALI_PHY_944_DATA */ + 0x00000000 /* DENALI_PHY_945_DATA */ + 0x00000000 /* DENALI_PHY_946_DATA */ + 0x00000508 /* DENALI_PHY_947_DATA */ + 0x00000000 /* DENALI_PHY_948_DATA */ + 0x00000000 /* DENALI_PHY_949_DATA */ + 0x00000000 /* DENALI_PHY_950_DATA */ + 0x00000000 /* DENALI_PHY_951_DATA */ + 0x00000000 /* DENALI_PHY_952_DATA */ + 0x00000000 /* DENALI_PHY_953_DATA */ + 0xe4000000 /* DENALI_PHY_954_DATA */ + 0x00000000 /* DENALI_PHY_955_DATA */ + 0x00000000 /* DENALI_PHY_956_DATA */ + 0x01010000 /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + >; +};

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 13/18] rockchip: clk: Add mention of four new clocks

These clocks are needed to get MMC running. We don't actually support setting them yet.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 198914b067..98de4bc69c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -925,7 +925,13 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_SARADC: rate = rk3399_saradc_get_clk(priv->cru); break; + case ACLK_VIO: + case ACLK_HDCP: + case ACLK_GIC_PRE: + case PCLK_DDR: + break; default: + log_debug("Unknown clock %d\n", clk->id); return -ENOENT; }

@@ -993,7 +999,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: ret = rk3399_saradc_set_clk(priv->cru, rate); break; + case ACLK_VIO: + case ACLK_HDCP: + case ACLK_GIC_PRE: + case PCLK_DDR: + return 0; default: + log_debug("Unknown clock %d\n", clk->id); return -ENOENT; }

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 14/18] rockchip: Tidy up board include-file ordering

These board files have inconsistent #include ordering. Fix them.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/mach-rockchip/rk3036-board.c | 2 +- arch/arm/mach-rockchip/rk3188-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3188-board.c | 2 +- arch/arm/mach-rockchip/rk322x-board.c | 2 +- arch/arm/mach-rockchip/rk3368-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3368-board-tpl.c | 4 ++-- arch/arm/mach-rockchip/rk3399-board-spl.c | 12 ++++++------ 7 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 95871cdd2e..872bed9606 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -7,13 +7,13 @@ #include <clk.h> #include <dm.h> #include <ram.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/periph.h> #include <asm/arch/grf_rk3036.h> #include <asm/arch/boot_mode.h> #include <asm/arch/sdram_rk3036.h> -#include <asm/gpio.h> #include <dm/pinctrl.h>

DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index a5e4d39cb7..5c09b0e4ae 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -12,6 +12,7 @@ #include <malloc.h> #include <ram.h> #include <spl.h> +#include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/bootrom.h> @@ -27,7 +28,6 @@ #include <dm/test.h> #include <dm/util.h> #include <power/regulator.h> -#include <syscon.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 8853e4a58e..3802395bc0 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -8,13 +8,13 @@ #include <dm.h> #include <ram.h> #include <syscon.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/grf_rk3188.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3288.h> #include <asm/arch/boot_mode.h> -#include <asm/gpio.h> #include <dm/pinctrl.h>

__weak int rk_board_late_init(void) diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index 7366d45ab6..5659248178 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -8,10 +8,10 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> +#include <asm/arch/boot_mode.h> #include <asm/arch/clock.h> #include <asm/arch/periph.h> #include <asm/arch/grf_rk322x.h> -#include <asm/arch/boot_mode.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index eae8ef15f3..230850ad6c 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -6,7 +6,6 @@ #include <common.h> #include <debug_uart.h> #include <dm.h> -#include <dm/pinctrl.h> #include <ram.h> #include <spl.h> #include <asm/io.h> @@ -15,6 +14,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/timer.h> +#include <dm/pinctrl.h>

void board_debug_uart_init(void) { diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index 3b33ce468a..f90a1fdca7 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -4,18 +4,18 @@ */

#include <common.h> -#include <asm/arch/clock.h> #include <debug_uart.h> #include <dm.h> #include <ram.h> #include <spl.h> +#include <syscon.h> #include <asm/io.h> #include <asm/arch/bootrom.h> +#include <asm/arch/clock.h> #include <asm/arch/cru_rk3368.h> #include <asm/arch/grf_rk3368.h> #include <asm/arch/hardware.h> #include <asm/arch/timer.h> -#include <syscon.h>

/* * The SPL (and also the full U-Boot stage on the RK3368) will run in diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 0198c6c65f..5453b2a61e 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -5,18 +5,18 @@ */

#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <syscon.h> +#include <asm/io.h> #include <asm/arch/bootrom.h> #include <asm/arch/clock.h> #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> -#include <asm/io.h> -#include <debug_uart.h> -#include <dm.h> #include <dm/pinctrl.h> -#include <ram.h> -#include <spl.h> -#include <syscon.h>

void board_return_to_bootrom(void) {

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 15/18] rockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set env

Some boards use different stdio environment variables from the default. Provide a #define for this which can be set before including the header file.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/configs/rk3399_common.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index eeda070752..3231de6668 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -50,11 +50,16 @@ "kernel_addr_r=0x02080000\0" \ "ramdisk_addr_r=0x04000000\0"

+#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + #include <config_distro_bootcmd.h> #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ BOOTENV

#endif

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 16/18] rockchip: Implement spl_gpio in the GPIO driver

Allow rockchip boards to use GPIOs before driver model is ready. This is really only useful for setting GPIOs to enable the early debug console, if needed on some platforms.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/include/asm/arch-rockchip/gpio.h | 29 ++++++++++++++ drivers/gpio/rk_gpio.c | 46 +++++++++++++++++++++++ 2 files changed, 75 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h index e204dcfd1d..3b337c4d41 100644 --- a/arch/arm/include/asm/arch-rockchip/gpio.h +++ b/arch/arm/include/asm/arch-rockchip/gpio.h @@ -24,4 +24,33 @@ struct rockchip_gpio_regs { }; check_member(rockchip_gpio_regs, ls_sync, 0x60);

+/* These defines are only used by spl_gpio.h */ +enum { + /* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */ + GPIO_BANK_SHIFT = 3, + GPIO_BANK_MASK = 3 << GPIO_BANK_SHIFT, + + GPIO_OFFSET_MASK = 0x1f, +}; + +#define GPIO(bank, offset) ((bank) << GPIO_BANK_SHIFT | (offset)) + +enum gpio_bank_t { + BANK_A = 0, + BANK_B, + BANK_C, + BANK_D, +}; + +enum gpio_dir_t { + GPIO_INPUT = 0, + GPIO_OUTPUT, +}; + +enum gpio_pull_t { + GPIO_PULL_NONE = 0, + GPIO_PULL_DOWN, + GPIO_PULL_UP, +}; + #endif diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index a8f311bbd6..c4d0c4ff23 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -91,6 +91,52 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) #endif }

+/* Simple SPL interface to GPIOs */ +#ifdef CONFIG_SPL_BUILD + +enum { + PULL_NONE_1V8 = 0, + PULL_DOWN_1V8 = 1, + PULL_UP_1V8 = 3, +}; + +int spl_gpio_set_pull(void *vregs, uint gpio, int pull) +{ + u32 *regs = vregs; + uint val; + + regs += gpio >> GPIO_BANK_SHIFT; + gpio &= GPIO_OFFSET_MASK; + switch (pull) { + case GPIO_PULL_UP: + val = PULL_UP_1V8; + break; + case GPIO_PULL_DOWN: + val = PULL_DOWN_1V8; + break; + case GPIO_PULL_NONE: + default: + val = PULL_NONE_1V8; + break; + } + clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2)); + + return 0; +} + +int spl_gpio_output(void *vregs, uint gpio, int value) +{ + struct rockchip_gpio_regs * const regs = vregs; + + clrsetbits_le32(&regs->swport_dr, 1 << gpio, value << gpio); + + /* Set direction */ + clrsetbits_le32(&regs->swport_ddr, 1 << gpio, 1 << gpio); + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ + static int rockchip_gpio_probe(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 17/18] rockchip: gru: Add extra device-tree settings

Add some U-Boot-specific settings. These should really go in the *u-boot.dtsi file, but it seems that rk3399 does not use that yet.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/arm/dts/rk3399-gru-bob.dts | 1 + arch/arm/dts/rk3399-gru-chromebook.dtsi | 1 + arch/arm/dts/rk3399-gru.dtsi | 21 +++++++++++++++++---- 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts index 1ee0dc0d9f..0e3d91fc28 100644 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -7,6 +7,7 @@

/dts-v1/; #include "rk3399-gru-chromebook.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"

/ { model = "Google Bob"; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi index ff81dfda3b..c6495adcca 100644 --- a/arch/arm/dts/rk3399-gru-chromebook.dtsi +++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi @@ -232,6 +232,7 @@ &edp { status = "okay";

+ rockchip,panel = <&edp_panel>; ports { edp_out: port@1 { reg = <1>; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index 7cc9b2642b..df19263acc 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -11,7 +11,13 @@

/ { chosen { + u-boot,dm-pre-reloc; stdout-path = "serial2:115200n8"; + u-boot,spl-boot-order = &spi_flash; + }; + + config { + u-boot,spl-payload-offset = <0x40000>; };

/* @@ -539,12 +545,14 @@ ap_i2c_audio: &i2c8 {

&spi1 { status = "okay"; + u-boot,dm-pre-reloc;

pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>;

- spiflash@0 { - compatible = "jedec,spi-nor"; + spi_flash: spiflash@0 { + u-boot,dm-pre-reloc; + compatible = "jedec,spi-nor", "spi-flash"; reg = <0>;

/* May run faster once verified. */ @@ -558,12 +566,16 @@ ap_i2c_audio: &i2c8 {

&spi5 { status = "okay"; + spi-activate-delay = <100>; + spi-max-frequency = <3000000>; + spi-deactivate-delay = <200>;

cros_ec: ec@0 { compatible = "google,cros-ec-spi"; reg = <0>; interrupt-parent = <&gpio0>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; @@ -618,6 +630,7 @@ ap_i2c_audio: &i2c8 {

&uart2 { status = "okay"; + u-boot,dm-pre-reloc; };

&usb_host0_ohci { @@ -650,8 +663,8 @@ ap_i2c_audio: &i2c8 { status = "okay"; };

-#include <arm/cros-ec-keyboard.dtsi> -#include <arm/cros-ec-sbs.dtsi> +#include <cros-ec-keyboard.dtsi> +#include <cros-ec-sbs.dtsi>

&pinctrl { /*

-- 2.20.1.97.g81188d93c3-goog

Simon Glass

5:24 a.m.

New subject: [U-Boot] [PATCH 18/18] rockchip: Add support for chromebook_bob

Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports for both power and external display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions.

Support so far includes only: - UART - SDRAM - MMC, SD card - Cros EC (but not keyboard)

Not included: - Keyboard - Display - Sound - USB - TPM

Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support for this is not provided in this series.

Signed-off-by: Simon Glass sjg@chromium.org ---

.../arm/include/asm/arch-rockchip/sys_proto.h | 3 + arch/arm/mach-rockchip/rk3399-board-spl.c | 37 ++++++- arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++ board/google/gru/Kconfig | 15 +++ board/google/gru/MAINTAINERS | 6 ++ board/google/gru/Makefile | 5 + board/google/gru/gru.c | 16 +++ configs/chromebook_bob_defconfig | 100 ++++++++++++++++++ doc/README.rockchip | 6 +- include/configs/gru.h | 18 ++++ 10 files changed, 213 insertions(+), 3 deletions(-) create mode 100644 board/google/gru/Kconfig create mode 100644 board/google/gru/MAINTAINERS create mode 100644 board/google/gru/Makefile create mode 100644 board/google/gru/gru.c create mode 100644 configs/chromebook_bob_defconfig create mode 100644 include/configs/gru.h

diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 925fcc888c..928e4f258b 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -29,4 +29,7 @@ static void configure_l2ctlr(void) } #endif /* CONFIG_ROCKCHIP_RK3288 */

+/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 5453b2a61e..2be485ec5e 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -9,6 +9,7 @@ #include <dm.h> #include <ram.h> #include <spl.h> +#include <spl_gpio.h> #include <syscon.h> #include <asm/io.h> #include <asm/arch/bootrom.h> @@ -16,6 +17,7 @@ #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> +#include <asm/arch/sys_proto.h> #include <dm/pinctrl.h>

void board_return_to_bootrom(void) @@ -128,7 +130,11 @@ void secure_timer_init(void) void board_debug_uart_init(void) { #define GRF_BASE 0xff770000 +#define GPIO0_BASE 0xff720000 +#define PMUGRF_BASE 0xff320000 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;

#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) /* Enable early UART0 on the RK3399 */ @@ -139,6 +145,20 @@ void board_debug_uart_init(void) GRF_GPIO2C1_SEL_MASK, GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); #else +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running the SPI + * Flash based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NONE); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NONE); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, @@ -163,6 +183,22 @@ void board_init_f(ulong dummy)

#define EARLY_UART #ifdef EARLY_UART +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + int sum, i; + + debug_uart_init(); + + /* + * Add a delay and ensure that the compiler does not optimise this out. + * This is needed since the power rails tail a while to turn on, and + * we get garbage serial output otherwise. + */ + sum = 0; + for (i = 0; i < 150000; i++) + sum += i; + gru_dummy_function(sum); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + /* * Debug UART can be used from here if required: * @@ -171,7 +207,6 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - debug_uart_init(); printascii("U-Boot SPL board init\n"); #endif

diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 8f18e33c76..2408adb420 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -53,6 +53,15 @@ config TARGET_ROCK960_RK3399 * 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only), 1x USB 3.0 type C OTG

+config TARGET_CHROMEBOOK_BOB + bool "Asus Flip C101PA Chromebook (RK3399)" + help + Bob is a small RK3299-based device similar in apperance to Minnie. + It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 10.1", + 1280x800 display. It uses its USB ports for both power and external + display. It includes a Chrome OS EC (Cortex-M3) to provide access to + the keyboard and battery functions. + endchoice

config SYS_SOC @@ -64,5 +73,6 @@ config SYS_MALLOC_F_LEN source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" +source "board/google/gru/Kconfig"

endif diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig new file mode 100644 index 0000000000..61f7bbca98 --- /dev/null +++ b/board/google/gru/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_BOB + +config SYS_BOARD + default "gru" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "gru" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/gru/MAINTAINERS b/board/google/gru/MAINTAINERS new file mode 100644 index 0000000000..e1cda756b8 --- /dev/null +++ b/board/google/gru/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK BOB BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/google/gru/ +F: include/configs/gru.h +F: configs/chromebook_bob_defconfig diff --git a/board/google/gru/Makefile b/board/google/gru/Makefile new file mode 100644 index 0000000000..9117534a49 --- /dev/null +++ b/board/google/gru/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += gru.o diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c new file mode 100644 index 0000000000..b116b1a549 --- /dev/null +++ b/board/google/gru/gru.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google + */ + +#include <common.h> + +int board_init(void) +{ + return 0; +} + +/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i) +{ +} diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig new file mode 100644 index 0000000000..56b52bc160 --- /dev/null +++ b/configs/chromebook_bob_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_BOOT_MODE_REG=0 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_TARGET_CHROMEBOOK_BOB=y +CONFIG_DEBUG_UART_BASE=0xff1a0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_LOG_DEFAULT_LEVEL=7 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 9b7e4bac11..b1aed93a40 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -52,13 +52,14 @@ One RK3328 board is supported:

- EVB RK3328

-Five RK3399 boards are supported (aarch64): +Size RK3399 boards are supported (aarch64):

- EBV RK3399 - use evb_rk3399 configuration - Firefly RK3399 - use the same evb_rk3399 configuration - Puma - use puma_rk3399 configuration - Ficus - use ficus-rk3399 configuration - Rock960 (Vamrs) - use rock960-rk3399 configuration + - Bob - use chromebook_bob configuration

Four RK3368 boards are supported:

@@ -252,7 +253,8 @@ You should see something like: Booting from SPI ================

-To write an image that boots from SPI flash (e.g. for the Haier Chromebook): +To write an image that boots from SPI flash (e.g. for the Haier Chromebook or +Bob):

./chromebook_jerry/tools/mkimage -n rk3288 -T rkspi \ -d chromebook_jerry/spl/u-boot-spl-dtb.bin spl.bin && \ diff --git a/include/configs/gru.h b/include/configs/gru.h new file mode 100644 index 0000000000..a0d27b6d51 --- /dev/null +++ b/include/configs/gru.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif

-- 2.20.1.97.g81188d93c3-goog

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Andy Yan
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Simon Glass