A64 and H6 support automatic delay calibration and Linux driver uses it instead of hardcoded delays. Add support for it to u-boot driver.

Fixes eMMC instability on Pinebook

Signed-off-by: Vasily Khoruzhick anarsoul@gmail.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com Tested-by: Maxime Ripard maxime.ripard@bootlin.com Cc: Vagrant Cascadian vagrant@debian.org --- arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++- drivers/mmc/sunxi_mmc.c | 21 ++++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index d98c53faaa..f2deafddd2 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -46,7 +46,9 @@ struct sunxi_mmc { u32 cbda; /* 0x94 */ u32 res2[26]; #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) - u32 res3[64]; + u32 res3[17]; + u32 samp_dl; + u32 res4[46]; #endif u32 fifo; /* 0x100 / 0x200 FIFO access address */ }; @@ -130,5 +132,7 @@ struct sunxi_mmc { #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) #define SUNXI_MMC_COMMON_RESET (1 << 18)

+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) + struct mmc *sunxi_mmc_init(int sdc_no); #endif /* _SUNXI_MMC_H */ diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 39f15eb423..147eb9b4d5 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) { unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; bool new_mode = false; + bool calibrate = false; u32 val = 0;

if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) new_mode = true;

+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6) + calibrate = true; +#endif + /* * The MMC clock has an extra /2 post-divider when operating in the new * mode. @@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) val = CCM_MMC_CTRL_MODE_SEL_NEW; setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif - } else { + } else if (!calibrate) { + /* + * Use hardcoded delay values if controller doesn't support + * calibration + */ val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | CCM_MMC_CTRL_SCLK_DLY(sclk_dly); } @@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr);

+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6) + /* A64 supports calibration of delays on MMC controller and we + * have to set delay of zero before starting calibration. + * Allwinner BSP driver sets a delay only in the case of + * using HS400 which is not supported by mainline U-Boot or + * Linux at the moment + */ + writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl); +#endif + /* Re-enable Clock */ rval |= SUNXI_MMC_CLK_ENABLE; writel(rval, &priv->reg->clkcr);

Both GPIOs are optional, so we shouldn't fail if any is missing. Without this fix reset is not deasserted if sleep GPIO is missing.

Signed-off-by: Vasily Khoruzhick anarsoul@gmail.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com Tested-by: Maxime Ripard maxime.ripard@bootlin.com Cc: Vagrant Cascadian vagrant@debian.org --- drivers/video/bridge/video-bridge-uclass.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c index cd4959cc71..5fecb4cfd5 100644 --- a/drivers/video/bridge/video-bridge-uclass.c +++ b/drivers/video/bridge/video-bridge-uclass.c @@ -106,13 +106,19 @@ static int video_bridge_pre_probe(struct udevice *dev) int video_bridge_set_active(struct udevice *dev, bool active) { struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); - int ret; + int ret = 0;

debug("%s: %d\n", __func__, active); - ret = dm_gpio_set_value(&uc_priv->sleep, !active); - if (ret) - return ret; - if (active) { + if (uc_priv->sleep.dev) { + ret = dm_gpio_set_value(&uc_priv->sleep, !active); + if (ret) + return ret; + } + + if (!active) + return 0; + + if (uc_priv->reset.dev) { ret = dm_gpio_set_value(&uc_priv->reset, true); if (ret) return ret;

Updates the device tree file from the the Linux tree as of v4.19-rc4, exactly Linux commit:

commit 7876320f8880 (tag: v4.19-rc4) Author: Linus Torvalds torvalds@linux-foundation.org Date: Sun Sep 16 11:52:37 2018 -0700

Linux 4.19-rc4

Signed-off-by: Vasily Khoruzhick anarsoul@gmail.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com Tested-by: Maxime Ripard maxime.ripard@bootlin.com Cc: Vagrant Cascadian vagrant@debian.org --- arch/arm/dts/sun50i-a64.dtsi | 122 +++++++++++++++++++++++++++++------ 1 file changed, 103 insertions(+), 19 deletions(-)

diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 7a083637c4..d3daf90a87 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -43,9 +43,12 @@ */

#include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/sun50i-a64-ccu.h> +#include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/reset/sun8i-r-ccu.h>

/ { interrupt-parent = <&gic>; @@ -57,17 +60,21 @@ #size-cells = <1>; ranges;

-/* - * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. - * However there is no support for this clock on A64 yet, so we depend - * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. - */ simplefb_lcd: framebuffer-lcd { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "mixer0-lcd0"; clocks = <&ccu CLK_TCON0>, - <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; + <&display_clocks CLK_MIXER0>; + status = "disabled"; + }; + + simplefb_hdmi: framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-hdmi"; + clocks = <&display_clocks CLK_MIXER1>, + <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; status = "disabled"; }; }; @@ -168,10 +175,46 @@ #size-cells = <1>; ranges;

+ de2@1000000 { + compatible = "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&de2_sram 1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000000 0x400000>; + + display_clocks: clock@0 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + syscon: syscon@1c00000 { - compatible = "allwinner,sun50i-a64-system-controller", - "syscon"; + compatible = "allwinner,sun50i-a64-system-control"; reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@18000 { + compatible = "mmio-sram"; + reg = <0x00018000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00018000 0x28000>; + + de2_sram: sram-section@0 { + compatible = "allwinner,sun50i-a64-sram-c"; + reg = <0x0000 0x28000>; + }; + }; };

dma: dma-controller@1c02000 { @@ -364,6 +407,11 @@ bias-pull-up; };

+ pwm_pin: pwm_pin { + pins = "PD22"; + function = "pwm"; + }; + rmii_pins: rmii_pins { pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; @@ -474,15 +522,6 @@ status = "disabled"; };

- pwm: pwm@1c21400 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; - reg = <0x01c21400 0x8>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -617,8 +656,6 @@ clocks = <&ccu CLK_BUS_EMAC>; clock-names = "stmmaceth"; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>;

mdio: mdio { compatible = "snps,dwmac-mdio"; @@ -638,11 +675,25 @@ #interrupt-cells = <3>; };

+ pwm: pwm@1c21400 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; + clocks = <&osc32k>; + #clock-cells = <1>; };

r_intc: interrupt-controller@1f00c00 { @@ -664,6 +715,29 @@ #reset-cells = <1>; };

+ r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_APB0_I2C>; + resets = <&r_ccu RST_APB0_I2C>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; + reg = <0x01f03800 0x400>; + clocks = <&osc24M>; + pinctrl-names = "default"; + pinctrl-0 = <&r_pwm_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun50i-a64-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -675,6 +749,16 @@ interrupt-controller; #interrupt-cells = <3>;

+ r_i2c_pins_a: i2c-a { + pins = "PL8", "PL9"; + function = "s_i2c"; + }; + + r_pwm_pin: pwm { + pins = "PL10"; + function = "s_pwm"; + }; + r_rsb_pins: rsb { pins = "PL0", "PL1"; function = "s_rsb";

Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has two groups of pinmuxes on PL bank, so it's called R_I2C.

Add support for this I2C controller and the pinmux which doesn't conflict with RSB.

Signed-off-by: Vasily Khoruzhick anarsoul@gmail.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com Tested-by: Maxime Ripard maxime.ripard@bootlin.com Cc: Vagrant Cascadian vagrant@debian.org --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/Kconfig | 1 + board/sunxi/board.c | 6 ++++++ 3 files changed, 8 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 6a5eafc3d3..2daf23f6f5 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -211,6 +211,7 @@ enum sunxi_gpio_number { #define SUN8I_H3_GPL_R_TWI 2 #define SUN8I_A23_GPL_R_TWI 3 #define SUN8I_GPL_R_UART 2 +#define SUN50I_GPL_R_TWI 2

#define SUN9I_GPN_R_RSB 3

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 686f38fec4..7ba429c744 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -272,6 +272,7 @@ config MACH_SUN50I select ARM64 select DM_I2C select PHY_SUN4I_USB + select SUN6I_PRCM select SUNXI_DE2 select SUNXI_GEN_SUN6I select SUPPORT_SPL diff --git a/board/sunxi/board.c b/board/sunxi/board.c index d1d7f9f400..90f8bc0a6e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -168,10 +168,16 @@ void i2c_init_board(void) #endif

#ifdef CONFIG_R_I2C_ENABLE +#ifdef CONFIG_MACH_SUN50I + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); +#else clock_twi_onoff(5, 1); sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); #endif +#endif }

#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)