GPR register definition is already available at imx-regs.h, so remove the duplication.

Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- arch/arm/cpu/arm1136/mx31/generic.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 4f27e25..1621e9e 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -27,8 +27,6 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h>

-#define IOMUXGPR (IOMUXC_BASE + 0x008) - static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = GET_PLL_MFI(reg); @@ -147,13 +145,13 @@ void mx31_set_gpr(enum iomux_gp_func gp, char en) { u32 l;

- l = readl(IOMUXGPR); + l = readl(IOMUXC_GPR); if (en) l |= gp; else l &= ~gp;

- writel(l, IOMUXGPR); + writel(l, IOMUXC_GPR); }

void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)

Use proper IO accessor for GPR register.

Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- arch/arm/cpu/arm1136/mx31/generic.c | 5 +++-- arch/arm/include/asm/arch-mx31/imx-regs.h | 7 ++++++- 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 1621e9e..167e97a 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -144,14 +144,15 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) void mx31_set_gpr(enum iomux_gp_func gp, char en) { u32 l; + struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;

- l = readl(IOMUXC_GPR); + l = readl(&iomuxc->gpr); if (en) l |= gp; else l &= ~gp;

- writel(l, IOMUXC_GPR); + writel(l, &iomuxc->gpr); }

void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index afdaa1c..0147920 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -98,6 +98,12 @@ struct iim_regs { u32 iim_scs3; };

+struct iomuxc_regs { + u32 unused1; + u32 unused2; + u32 gpr; +}; + struct mx3_cpu_type { u8 srev; u32 v; @@ -636,7 +642,6 @@ struct esdc_regs { #define WEIM_BASE 0xb8002000

#define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_GPR (IOMUXC_BASE + 0x8) #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)

Fix checkpatch warnings in generic.c.

Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- arch/arm/cpu/arm1136/mx31/generic.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 167e97a..f458281 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -87,7 +87,7 @@ static u32 mx31_get_hsp_clk(void) void mx31_dump_clocks(void) { u32 cpufreq = mx31_get_mcu_main_clk(); - printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); + printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000); printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); printf("hsp clock : %dHz\n", mx31_get_hsp_clk()); } @@ -215,7 +215,7 @@ static char *get_reset_cause(void) }

#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) +int print_cpuinfo(void) { u32 srev = get_cpu_rev();

On 11/09/2011 03:15 PM, Fabio Estevam wrote:

Use generic function for configuring GPR register.

Signed-off-by: Fabio Estevam fabio.estevam@freescale.com

board/davedenx/qong/qong.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 665aedf..c41f11d 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -231,7 +231,7 @@ static void board_nand_setup(void)

mxc_setup_weimcs(3, &cs3);

• __REG(IOMUXC_GPR) |= 1 << 13;

• mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);

  mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));

Acked-by: Stefano Babic sbabic@denx.de

Best regards, Stefano Babic