[PATCH 1/2] mmc: fsl_esdhc_imx: initialize data for imx7ulp
From: Jorge Ramirez-Ortiz jorge@foundries.io
Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel. Set supported by u-boot flags only.
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io Signed-off-by: Ricardo Salveti ricardo@foundries.io Co-developed-by: Oleksandr Suvorov oleksandr.suvorov@foundries.io Signed-off-by: Oleksandr Suvorov oleksandr.suvorov@foundries.io ---
drivers/mmc/fsl_esdhc_imx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index aabf39535f..6c8f77f9ee 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1706,6 +1706,11 @@ static struct esdhc_soc_data usdhc_imx7d_data = { | ESDHC_FLAG_HS400, };
+static struct esdhc_soc_data usdhc_imx7ulp_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, +}; + static struct esdhc_soc_data usdhc_imx8qm_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | @@ -1720,7 +1725,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6sl-usdhc", }, { .compatible = "fsl,imx6q-usdhc", }, { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, - { .compatible = "fsl,imx7ulp-usdhc", }, + { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,}, { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Import HS400 support for iMX7ULP B0 from the Linux kernel:
2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel value. If this register bits value is 0, it needs 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave sel value. This will short the lock time of slave.
i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add 5us delay.
Signed-off-by: Oleksandr Suvorov oleksandr.suvorov@foundries.io Series-notes fsl_esdhc_imx improvements
Import individual settings for soc imx7ulp and add support of HS400 for this soc. END
---
drivers/mmc/fsl_esdhc_imx.c | 11 ++++++++--- include/fsl_esdhc_imx.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 6c8f77f9ee..569f099d9b 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -727,17 +727,21 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); + /* clear the reset bit on strobe dll before any setting */ + esdhc_write32(®s->strobe_dllctrl, 0); +
/* * enable strobe dll ctrl and adjust the delay target * for the uSDHC loopback read clock */ val = ESDHC_STROBE_DLL_CTRL_ENABLE | + ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | (priv->strobe_dll_delay_target << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); esdhc_write32(®s->strobe_dllctrl, val); - /* wait 1us to make sure strobe dll status register stable */ - mdelay(1); + /* wait 5us to make sure strobe dll status register stable */ + mdelay(5); val = esdhc_read32(®s->strobe_dllstat); if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) pr_warn("HS400 strobe DLL status REF not lock!\n"); @@ -1708,7 +1712,8 @@ static struct esdhc_soc_data usdhc_imx7d_data = {
static struct esdhc_soc_data usdhc_imx7ulp_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING - | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_HS400, };
static struct esdhc_soc_data usdhc_imx8qm_data = { diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 45ed635a77..12e9163382 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -194,6 +194,7 @@ #define ESDHC_STROBE_DLL_CTRL_RESET BIT(1) #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 +#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
#define ESDHC_STROBE_DLL_STATUS 0x74 #define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
Hi Oleksandr,
On Tue, Aug 31, 2021 at 1:42 PM Oleksandr Suvorov oleksandr.suvorov@foundries.io wrote:
Import HS400 support for iMX7ULP B0 from the Linux kernel:
2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel value. If this register bits value is 0, it needs 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave sel value. This will short the lock time of slave.
i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add 5us delay.
Signed-off-by: Oleksandr Suvorov oleksandr.suvorov@foundries.io Series-notes fsl_esdhc_imx improvements
Import individual settings for soc imx7ulp and add support of HS400 for this soc. END
The text below the Signed-off-by should be removed.
Other than that, the patch looks good:
Reviewed-by: Fabio Estevam festevam@gmail.com
On Tue, Aug 31, 2021 at 8:34 PM Fabio Estevam festevam@gmail.com wrote:
Hi Oleksandr,
On Tue, Aug 31, 2021 at 1:42 PM Oleksandr Suvorov oleksandr.suvorov@foundries.io wrote:
Import HS400 support for iMX7ULP B0 from the Linux kernel:
2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel value. If this register bits value is 0, it needs 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave sel value. This will short the lock time of slave.
i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add 5us delay.
Signed-off-by: Oleksandr Suvorov oleksandr.suvorov@foundries.io Series-notes fsl_esdhc_imx improvements
Import individual settings for soc imx7ulp and add support of HS400 for this soc. END
The text below the Signed-off-by should be removed.
Oops, missed ":" :) The fix is coming.
Other than that, the patch looks good:
Reviewed-by: Fabio Estevam festevam@gmail.com
Thanks, Fabio!
On Tue, Aug 31, 2021 at 1:42 PM Oleksandr Suvorov oleksandr.suvorov@foundries.io wrote:
From: Jorge Ramirez-Ortiz jorge@foundries.io
Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel. Set supported by u-boot flags only.
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io Signed-off-by: Ricardo Salveti ricardo@foundries.io Co-developed-by: Oleksandr Suvorov oleksandr.suvorov@foundries.io Signed-off-by: Oleksandr Suvorov oleksandr.suvorov@foundries.io
Reviewed-by: Fabio Estevam festevam@gmail.com
participants (3)
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Fabio Estevam -
Oleksandr Suvorov -
Oleksandr Suvorov