[PATCH v2 0/9] phyCORE-i.MX8MP Update
Hello,
this is the second version of the phyCORE-i.MX8MP updates. This includes also an update of imx8mp.dtsi from kernel and the introduction of a common imx8mp-u-boot.dtsi.
Changes in v2: [5/9] - removed hardcoded serverip in environment - removed not needed fec eth defines in board config include
Teresa
Teresa Remmet (9): arm: dts: imx8mp: Resync imx8mp device tree include arm: dts: imx8mp: Add common u-boot dtsi arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel board: phytec: phycore_imx8mp: Change debug UART board: phytec: phycore_imx8mp: Add fec support board: phytec: phycore_imx8mp: Set VDD_ARM to 0,95V board: phytec: phycore-imx8mp: Enable DVS1 control arm: dts: imx8mp-phyboard-pollux-rdk-u-boot: Add wdog pinctrl entry board: phytec: imx8mp-phycore: Switch to binman
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 39 +---- .../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 152 +++++++++++++----- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 58 ++++++- arch/arm/dts/imx8mp-phycore-som.dtsi | 2 +- arch/arm/dts/imx8mp-u-boot.dtsi | 42 +++++ arch/arm/dts/imx8mp.dtsi | 146 ++++++++++++++++- arch/arm/mach-imx/imx8m/Kconfig | 1 + .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++ board/phytec/phycore_imx8mp/phycore-imx8mp.c | 14 ++ board/phytec/phycore_imx8mp/spl.c | 23 ++- configs/phycore-imx8mp_defconfig | 12 +- include/configs/phycore_imx8mp.h | 21 ++- 12 files changed, 422 insertions(+), 98 deletions(-) create mode 100644 arch/arm/dts/imx8mp-u-boot.dtsi create mode 100644 board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
Sync imx8mp include with kernel commit: d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps, dwc3"")
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/imx8mp.dtsi | 146 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 141 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index ecccfbb4f5ad..c2d51a46cb3c 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -18,6 +18,7 @@
aliases { ethernet0 = &fec; + ethernet1 = &eqos; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -218,10 +219,12 @@ };
soc@0 { - compatible = "simple-bus"; + compatible = "fsl,imx8mp-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mp_uid>; + nvmem-cell-names = "soc_unique_id";
aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -266,7 +269,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>; + gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; };
gpio4: gpio@30230000 { @@ -310,6 +313,22 @@ status = "disabled"; };
+ wdog2: watchdog@30290000 { + compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; + status = "disabled"; + }; + + wdog3: watchdog@302a0000 { + compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; + status = "disabled"; + }; + iomuxc: pinctrl@30330000 { compatible = "fsl,imx8mp-iomuxc"; reg = <0x30330000 0x10000>; @@ -328,9 +347,17 @@ #address-cells = <1>; #size-cells = <1>;
+ imx8mp_uid: unique-id@420 { + reg = <0x8 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + eth_mac1: mac-address@90 { + reg = <0x90 6>; + }; };
anatop: anatop@30360000 { @@ -762,13 +789,40 @@ assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, <&clk IMX8MP_CLK_ENET_TIMER>, <&clk IMX8MP_CLK_ENET_REF>, - <&clk IMX8MP_CLK_ENET_TIMER>; + <&clk IMX8MP_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, <&clk IMX8MP_SYS_PLL2_100M>, - <&clk IMX8MP_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + <&clk IMX8MP_SYS_PLL2_125M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + fsl,stop-mode = <&gpr 0x10 3>; + nvmem_macaddr_swap; + status = "disabled"; + }; + + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + intf_mode = <&gpr 0x4>; status = "disabled"; }; }; @@ -788,5 +842,87 @@ reg = <0x3d800000 0x400000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; + + usb3_phy0: usb-phy@381f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0x381f0040 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_0: usb@32f10100 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0x32f10100 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x40000000 0x40000000 0xc0000000>; + ranges; + status = "disabled"; + + usb_dwc3_0: usb@38100000 { + compatible = "snps,dwc3"; + reg = <0x38100000 0x10000>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_USB_CORE_REF>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u2-freeclk-exists-quirk; + }; + + }; + + usb3_phy1: usb-phy@382f0040 { + compatible = "fsl,imx8mp-usb-phy"; + reg = <0x382f0040 0x40>; + clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + }; + + usb3_1: usb@32f10108 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0x32f10108 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "suspend"; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x40000000 0x40000000 0xc0000000>; + ranges; + status = "disabled"; + + usb_dwc3_1: usb@38200000 { + compatible = "snps,dwc3"; + reg = <0x38200000 0x10000>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_USB_CORE_REF>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus_early", "ref", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u2-freeclk-exists-quirk; + }; + }; }; };
Hello Teresa,
On 02.07.21 13:19, Teresa Remmet wrote:
Sync imx8mp include with kernel commit: d1689cd3c0f4 ("arm64: dts: imx8mp: Use the correct name for child node "snps, dwc3"")
Signed-off-by: Teresa Remmet t.remmet@phytec.de
arch/arm/dts/imx8mp.dtsi | 146 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 141 insertions(+), 5 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Factor out the common node settings for dm-spl and dm-pre-reloc and move them to imx8mp-u-boot.dtsi
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/imx8mp-evk-u-boot.dtsi | 39 +---------------- .../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 39 +---------------- arch/arm/dts/imx8mp-u-boot.dtsi | 42 +++++++++++++++++++ 3 files changed, 46 insertions(+), 74 deletions(-) create mode 100644 arch/arm/dts/imx8mp-u-boot.dtsi
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 4162f41cffb6..cf10194fe4ab 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2019 NXP */
+#include "imx8mp-u-boot.dtsi" + / { binman: binman { multiple-images; @@ -21,43 +23,6 @@ }; };
-&{/soc@0} { - u-boot,dm-pre-reloc; - u-boot,dm-spl; -}; - -&clk { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&osc_32k { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&osc_24m { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&aips1 { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&aips2 { - u-boot,dm-spl; -}; - -&aips3 { - u-boot,dm-spl; -}; - -&iomuxc { - u-boot,dm-spl; -}; - ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 20e7f63ff91f..6c1528934a98 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -4,6 +4,8 @@ * Author: Teresa Remmet t.remmet@phytec.de */
+#include "imx8mp-u-boot.dtsi" + / { wdt-reboot { compatible = "wdt-reboot"; @@ -12,43 +14,6 @@ }; };
-&{/soc@0} { - u-boot,dm-pre-reloc; - u-boot,dm-spl; -}; - -&clk { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&osc_32k { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&osc_24m { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&aips1 { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&aips2 { - u-boot,dm-spl; -}; - -&aips3 { - u-boot,dm-spl; -}; - -&iomuxc { - u-boot,dm-spl; -}; - ®_usdhc2_vmmc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi new file mode 100644 index 000000000000..92f586f6dfed --- /dev/null +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet t.remmet@phytec.de + */ + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_32k { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +};
Hello Teresa,
On 02.07.21 13:19, Teresa Remmet wrote:
Factor out the common node settings for dm-spl and dm-pre-reloc and move them to imx8mp-u-boot.dtsi
Signed-off-by: Teresa Remmet t.remmet@phytec.de
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 39 +---------------- .../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 39 +---------------- arch/arm/dts/imx8mp-u-boot.dtsi | 42 +++++++++++++++++++ 3 files changed, 46 insertions(+), 74 deletions(-) create mode 100644 arch/arm/dts/imx8mp-u-boot.dtsi
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
This update includes eqos support and debug uart changes.
Synced with kernel commit 846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 58 ++++++++++++++++++--- arch/arm/dts/imx8mp-phycore-som.dtsi | 2 +- 2 files changed, 52 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts index 0e1a6d953389..984a6b9ded8d 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts @@ -16,7 +16,7 @@ "phytec,imx8mp-phycore-som", "fsl,imx8mp";
chosen { - stdout-path = &uart2; + stdout-path = &uart1; };
reg_usdhc2_vmmc: regulator-usdhc2 { @@ -33,9 +33,33 @@ }; };
+&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + enet-phy-lane-no-swap; + }; + }; +}; + &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -71,9 +95,9 @@ };
/* debug console */ -&uart2 { +&uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; + pinctrl-0 = <&pinctrl_uart1>; status = "okay"; };
@@ -90,6 +114,26 @@ };
&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 @@ -110,10 +154,10 @@ >; };
- pinctrl_uart2: uart2grp { + pinctrl_uart1: uart1grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 >; };
diff --git a/arch/arm/dts/imx8mp-phycore-som.dtsi b/arch/arm/dts/imx8mp-phycore-som.dtsi index 44a8c2337cee..f3965ec5b31d 100644 --- a/arch/arm/dts/imx8mp-phycore-som.dtsi +++ b/arch/arm/dts/imx8mp-phycore-som.dtsi @@ -67,7 +67,7 @@
&i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Hello Teresa,
On 02.07.21 13:19, Teresa Remmet wrote:
This update includes eqos support and debug uart changes.
Synced with kernel commit 846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
Signed-off-by: Teresa Remmet t.remmet@phytec.de
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 58 ++++++++++++++++++--- arch/arm/dts/imx8mp-phycore-som.dtsi | 2 +- 2 files changed, 52 insertions(+), 8 deletions(-)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
With the first redesign the debug UART had changed from UART2 to UART1. As the first hardware revision is considered as alpha and will not be supported in future. The old setup will not be preserved.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 ++-- board/phytec/phycore_imx8mp/spl.c | 6 +++--- include/configs/phycore_imx8mp.h | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 6c1528934a98..32ed037e3721 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -18,7 +18,7 @@ u-boot,dm-spl; };
-&pinctrl_uart2 { +&pinctrl_uart1 { u-boot,dm-spl; };
@@ -54,7 +54,7 @@ u-boot,dm-spl; };
-&uart2 { +&uart1 { u-boot,dm-spl; };
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index f9fa8d1e1281..0bc4c7693b06 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -80,8 +80,8 @@ int board_fit_config_name_match(const char *name) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = { - MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), };
static iomux_v3_cfg_t const wdog_pads[] = { @@ -107,7 +107,7 @@ void board_init_f(ulong dummy)
arch_cpu_init();
- init_uart_clk(1); + init_uart_clk(0);
board_early_init_f();
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 04900498507a..e24f223c21d3 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -39,7 +39,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ - "console=ttymxc1,115200\0" \ + "console=ttymxc0,115200\0" \ "fdt_addr=0x48000000\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ @@ -87,7 +87,7 @@ #define PHYS_SDRAM_SIZE 0x80000000
/* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K
Hello Teresa,
On 02.07.21 13:19, Teresa Remmet wrote:
With the first redesign the debug UART had changed from UART2 to UART1. As the first hardware revision is considered as alpha and will not be supported in future. The old setup will not be preserved.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 ++-- board/phytec/phycore_imx8mp/spl.c | 6 +++--- include/configs/phycore_imx8mp.h | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-)
Your patch "[PATCH v2 3/9] arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel"
changed uart2 to uart1 in arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
May this part should be done also in this patch?
Beside of this:
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Hello Heiko,
Am Montag, den 05.07.2021, 06:58 +0200 schrieb Heiko Schocher:
Hello Teresa,
On 02.07.21 13:19, Teresa Remmet wrote:
With the first redesign the debug UART had changed from UART2 to UART1. As the first hardware revision is considered as alpha and will not be supported in future. The old setup will not be preserved.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 ++-- board/phytec/phycore_imx8mp/spl.c | 6 +++--- include/configs/phycore_imx8mp.h | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-)
Your patch "[PATCH v2 3/9] arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel"
changed uart2 to uart1 in arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
May this part should be done also in this patch?
yes, this would make the uart change more atomic and not separated over 2 patches. I will update this in v3.
Thanks, Teresa
Beside of this:
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Enable support for the fec ethernet on phyCORE-i.MX8MP.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mp/phycore-imx8mp.c | 14 ++++++++++++++ configs/phycore-imx8mp_defconfig | 7 +++++++ include/configs/phycore_imx8mp.h | 17 +++++++++++++++++ 3 files changed, 38 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index 67649078c201..a8f082143762 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -10,11 +10,25 @@ #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> +#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
+static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + + return 0; +} + int board_init(void) { + setup_fec(); + return 0; }
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 7f21e8888e0e..a22f5e089d97 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -58,6 +58,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y @@ -79,7 +80,13 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI_DP83867=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index e24f223c21d3..75f84e60f5da 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -42,6 +42,7 @@ "console=ttymxc0,115200\0" \ "fdt_addr=0x48000000\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=2\0" \ @@ -57,6 +58,22 @@ "else " \ "echo WARN: Cannot load the DT; " \ "fi;\0 " \ + "nfsroot=/nfs\0" \ + "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi;\0" \
#define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \
Hello Teresa,
On 02.07.21 13:19, Teresa Remmet wrote:
Enable support for the fec ethernet on phyCORE-i.MX8MP.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/phycore_imx8mp/phycore-imx8mp.c | 14 ++++++++++++++ configs/phycore-imx8mp_defconfig | 7 +++++++ include/configs/phycore_imx8mp.h | 17 +++++++++++++++++ 3 files changed, 38 insertions(+)
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
Increase VDD_ARM to prevent timing issues as VDD_SOC is used in OD mode. Also increase GIC clock.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mp/spl.c | 11 ++++++++++- configs/phycore-imx8mp_defconfig | 1 + 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 0bc4c7693b06..815ca9badcba 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -62,7 +62,8 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
- /* increase VDD_SOC to typical value 0.95V */ + /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */ @@ -71,6 +72,14 @@ int power_init_board(void) return 0; }
+void spl_board_init(void) +{ + /* Set GIC clock to 500Mhz for OD VDD_SOC. */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +} + int board_fit_config_name_match(const char *name) { return 0; diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index a22f5e089d97..89c2ac977f47 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -25,6 +25,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y
Enable DVS1 control through PMIC_STBY_REQ.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mp/spl.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 815ca9badcba..19c486e55174 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -66,7 +66,11 @@ int power_init_board(void) pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
- /* set WDOG_B_CFG to cold reset */ + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set WDOG_B_CFG to cold reset */ pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
return 0;
Add missing pinctrl entry in spl.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 32ed037e3721..dbc48dfb4841 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -34,6 +34,10 @@ u-boot,dm-spl; };
+&pinctrl_wdog { + u-boot,dm-spl; +}; + &gpio1 { u-boot,dm-spl; };
Use now binman for image creation.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- .../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 105 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++ configs/phycore-imx8mp_defconfig | 4 +- 4 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index dbc48dfb4841..2b8e77cb27c5 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -7,6 +7,10 @@ #include "imx8mp-u-boot.dtsi"
/ { + binman: binman { + multiple-images; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -81,3 +85,104 @@ &wdog1 { u-boot,dm-spl; }; + +&binman { + u-boot-spl-ddr { + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + align-size = <4>; + align = <4>; + + u-boot-spl { + align-end = <4>; + }; + + blob_1: blob-ext@1 { + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; + size = <0x8000>; + }; + + blob_2: blob-ext@2 { + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; + size = <0x4000>; + }; + + blob_3: blob-ext@3 { + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; + size = <0x8000>; + }; + + blob_4: blob-ext@4 { + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; + size = <0x4000>; + }; + }; + + flash { + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <CONFIG_SYS_TEXT_BASE>; + + uboot_blob: blob-ext { + filename = "u-boot-nodtb.bin"; + }; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x970000>; + entry = <0x970000>; + + atf_blob: blob-ext { + filename = "bl31.bin"; + }; + }; + + fdt { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt"; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 0669363c0f51..ccaf106be5d8 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -127,6 +127,7 @@ config TARGET_PHYCORE_IMX8MM
config TARGET_PHYCORE_IMX8MP bool "PHYTEC PHYCORE i.MX8MP" + select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg new file mode 100644 index 000000000000..b2920b4908ed --- /dev/null +++ b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#define __ASSEMBLY__ + +ROM_VERSION v2 +BOOT_FROM sd +LOADER mkimage.flash.mkimage 0x920000 diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 89c2ac977f47..32d538c8bbbb 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -20,9 +20,9 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" CONFIG_DEFAULT_FDT_FILE="oftree" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y
Hello Teresa,
On 02.07.21 13:19, Teresa Remmet wrote:
Use now binman for image creation.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 105 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++ configs/phycore-imx8mp_defconfig | 4 +- 4 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
Reviewed-by: Heiko Schocher hs@denx.de
bye, Heiko
On Fri, Jul 2, 2021 at 4:49 PM Teresa Remmet t.remmet@phytec.de wrote:
Use now binman for image creation.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 105 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++ configs/phycore-imx8mp_defconfig | 4 +- 4 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index dbc48dfb4841..2b8e77cb27c5 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -7,6 +7,10 @@ #include "imx8mp-u-boot.dtsi"
/ {
binman: binman {multiple-images;};wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>;@@ -81,3 +85,104 @@ &wdog1 { u-boot,dm-spl; };
+&binman {
u-boot-spl-ddr {filename = "u-boot-spl-ddr.bin";pad-byte = <0xff>;align-size = <4>;align = <4>;u-boot-spl {align-end = <4>;};blob_1: blob-ext@1 {filename = "lpddr4_pmu_train_1d_imem_202006.bin";size = <0x8000>;};blob_2: blob-ext@2 {filename = "lpddr4_pmu_train_1d_dmem_202006.bin";size = <0x4000>;};blob_3: blob-ext@3 {filename = "lpddr4_pmu_train_2d_imem_202006.bin";size = <0x8000>;};blob_4: blob-ext@4 {filename = "lpddr4_pmu_train_2d_dmem_202006.bin";size = <0x4000>;};};flash {mkimage {args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";blob {filename = "u-boot-spl-ddr.bin";};};};itb {filename = "u-boot.itb";fit {description = "Configuration to load ATF before U-Boot";#address-cells = <1>;fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;images {uboot {description = "U-Boot (64-bit)";type = "standalone";arch = "arm64";compression = "none";load = <CONFIG_SYS_TEXT_BASE>;uboot_blob: blob-ext {filename = "u-boot-nodtb.bin";};};atf {description = "ARM Trusted Firmware";type = "firmware";arch = "arm64";compression = "none";load = <0x970000>;entry = <0x970000>;atf_blob: blob-ext {filename = "bl31.bin";};};fdt {description = "NAME";type = "flat_dt";compression = "none";uboot_fdt_blob: blob-ext {filename = "u-boot.dtb";};};};configurations {default = "conf";conf {description = "NAME";firmware = "uboot";loadables = "atf";fdt = "fdt";};};};};+};
I think this will increase the same copy of its in respective boards with changes in ddr names. Better to have common script to update the final its by taking ddr files via env, like it was done in Rockchip, Allwinner.
Jagan.
Hello Jagan,
Am Montag, den 05.07.2021, 11:01 +0530 schrieb Jagan Teki:
On Fri, Jul 2, 2021 at 4:49 PM Teresa Remmet t.remmet@phytec.de wrote:
Use now binman for image creation.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 105 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++ configs/phycore-imx8mp_defconfig | 4 +- 4 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index dbc48dfb4841..2b8e77cb27c5 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -7,6 +7,10 @@ #include "imx8mp-u-boot.dtsi"
/ {
binman: binman {multiple-images;};wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>;@@ -81,3 +85,104 @@ &wdog1 { u-boot,dm-spl; };
+&binman {
u-boot-spl-ddr {filename = "u-boot-spl-ddr.bin";pad-byte = <0xff>;align-size = <4>;align = <4>;u-boot-spl {align-end = <4>;};blob_1: blob-ext@1 {filename ="lpddr4_pmu_train_1d_imem_202006.bin";
size = <0x8000>;};blob_2: blob-ext@2 {filename ="lpddr4_pmu_train_1d_dmem_202006.bin";
size = <0x4000>;};blob_3: blob-ext@3 {filename ="lpddr4_pmu_train_2d_imem_202006.bin";
size = <0x8000>;};blob_4: blob-ext@4 {filename ="lpddr4_pmu_train_2d_dmem_202006.bin";
size = <0x4000>;};};flash {mkimage {args = "-n spl/u-boot-spl.cfgout -Timx8mimage -e 0x920000";
blob {filename = "u-boot-spl-ddr.bin";};};};itb {filename = "u-boot.itb";fit {description = "Configuration to load ATFbefore U-Boot";
#address-cells = <1>;fit,external-offset =<CONFIG_FIT_EXTERNAL_OFFSET>;
images {uboot {description = "U-Boot (64-bit)";
type = "standalone";arch = "arm64";compression = "none";load =<CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {filename = "u-boot-nodtb.bin";
};};atf {description = "ARM TrustedFirmware";
type = "firmware";arch = "arm64";compression = "none";load = <0x970000>;entry = <0x970000>;atf_blob: blob-ext {filename ="bl31.bin";
};};fdt {description = "NAME";type = "flat_dt";compression = "none";uboot_fdt_blob: blob-ext {filename = "u-boot.dtb";
};};};configurations {default = "conf";conf {description = "NAME";firmware = "uboot";loadables = "atf";fdt = "fdt";};};};};+};
I think this will increase the same copy of its in respective boards with changes in ddr names. Better to have common script to update the final its by taking ddr files via env, like it was done in Rockchip, Allwinner.
I could move the binman nodes also to "imx8mp-u-boot.dtsi". If it is only the ddr firmware names that might differ, they could be overwritten in the board specific u-boot.dtsi files using the blob_* labels.
What do you think?
Teresa
Jagan.
On Tue, Jul 6, 2021 at 5:54 PM Teresa Remmet T.Remmet@phytec.de wrote:
Hello Jagan,
Am Montag, den 05.07.2021, 11:01 +0530 schrieb Jagan Teki:
On Fri, Jul 2, 2021 at 4:49 PM Teresa Remmet t.remmet@phytec.de wrote:
Use now binman for image creation.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
.../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 105 ++++++++++++++++++ arch/arm/mach-imx/imx8m/Kconfig | 1 + .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++ configs/phycore-imx8mp_defconfig | 4 +- 4 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index dbc48dfb4841..2b8e77cb27c5 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -7,6 +7,10 @@ #include "imx8mp-u-boot.dtsi"
/ {
binman: binman {multiple-images;};wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>;@@ -81,3 +85,104 @@ &wdog1 { u-boot,dm-spl; };
+&binman {
u-boot-spl-ddr {filename = "u-boot-spl-ddr.bin";pad-byte = <0xff>;align-size = <4>;align = <4>;u-boot-spl {align-end = <4>;};blob_1: blob-ext@1 {filename ="lpddr4_pmu_train_1d_imem_202006.bin";
size = <0x8000>;};blob_2: blob-ext@2 {filename ="lpddr4_pmu_train_1d_dmem_202006.bin";
size = <0x4000>;};blob_3: blob-ext@3 {filename ="lpddr4_pmu_train_2d_imem_202006.bin";
size = <0x8000>;};blob_4: blob-ext@4 {filename ="lpddr4_pmu_train_2d_dmem_202006.bin";
size = <0x4000>;};};flash {mkimage {args = "-n spl/u-boot-spl.cfgout -Timx8mimage -e 0x920000";
blob {filename = "u-boot-spl-ddr.bin";};};};itb {filename = "u-boot.itb";fit {description = "Configuration to load ATFbefore U-Boot";
#address-cells = <1>;fit,external-offset =<CONFIG_FIT_EXTERNAL_OFFSET>;
images {uboot {description = "U-Boot (64-bit)";
type = "standalone";arch = "arm64";compression = "none";load =<CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {filename = "u-boot-nodtb.bin";
};};atf {description = "ARM TrustedFirmware";
type = "firmware";arch = "arm64";compression = "none";load = <0x970000>;entry = <0x970000>;atf_blob: blob-ext {filename ="bl31.bin";
};};fdt {description = "NAME";type = "flat_dt";compression = "none";uboot_fdt_blob: blob-ext {filename = "u-boot.dtb";
};};};configurations {default = "conf";conf {description = "NAME";firmware = "uboot";loadables = "atf";fdt = "fdt";};};};};+};
I think this will increase the same copy of its in respective boards with changes in ddr names. Better to have common script to update the final its by taking ddr files via env, like it was done in Rockchip, Allwinner.
I could move the binman nodes also to "imx8mp-u-boot.dtsi". If it is only the ddr firmware names that might differ, they could be overwritten in the board specific u-boot.dtsi files using the blob_* labels.
What do you think?
Agreed.
Jagan.
Hi Teresa,
On Fri, Jul 2, 2021 at 8:19 AM Teresa Remmet t.remmet@phytec.de wrote:
Hello,
this is the second version of the phyCORE-i.MX8MP updates. This includes also an update of imx8mp.dtsi from kernel and the introduction of a common imx8mp-u-boot.dtsi.
Changes in v2: [5/9] - removed hardcoded serverip in environment - removed not needed fec eth defines in board config include
Teresa
Teresa Remmet (9): arm: dts: imx8mp: Resync imx8mp device tree include arm: dts: imx8mp: Add common u-boot dtsi arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel board: phytec: phycore_imx8mp: Change debug UART board: phytec: phycore_imx8mp: Add fec support board: phytec: phycore_imx8mp: Set VDD_ARM to 0,95V board: phytec: phycore-imx8mp: Enable DVS1 control arm: dts: imx8mp-phyboard-pollux-rdk-u-boot: Add wdog pinctrl entry board: phytec: imx8mp-phycore: Switch to binman
For the series:
Reviewed-by: Fabio Estevam festevam@gmail.com
participants (5)
-
Fabio Estevam -
Heiko Schocher -
Jagan Teki -
Teresa Remmet -
Teresa Remmet