[PATCH 00/31] rockchip: rk3399: Sync DT with linux v6.8 and update defconfigs
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
I have runtime tested this series on following devices: - 96boards Rock960 - Khadas Edge Captain - Pine64 PineBook Pro - Pine64 RockPro64 - Radxa ROCK 4C+ - Radxa ROCK 4SE - Radxa ROCK Pi 4A - Radxa ROCK Pi 4B+
This series depends on the following series: - Enable booting from SPI flash on ROCK Pi 4 [1] - rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
Chromebook bob and kevin only use SPL and not TPL+SPL like other RK3399 boards, this mean that SPL is loaded to and run from SRAM instead of DRAM. The SPL and U-Boot payload is loaded from SPI flash.
The U-Boot payload is located at 0x40000 (256 KiB) offset in SPI flash and because the BROM only read first 2 KiB for each 4 KiB page, the size of SPL (idbloader.img) is limited to max 128 KiB.
The chosen bss start address further limits the size of SPL to 120 KiB.
0xff8e0000 (SPL_BSS_START_ADDR) - 0xff8c2000 (SPL_TEXT_BASE) = 0x1e000
Update SPL_MAX_SIZE to reflect the 120 KiB max size limitation.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- configs/chromebook_bob_defconfig | 2 +- configs/chromebook_kevin_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index d0321948697b..58e76f11472c 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -30,7 +30,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000 diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 120c11c04972..5adc276a746a 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -31,7 +31,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000
On 2024/4/1 04:28, Jonas Karlman wrote:
Chromebook bob and kevin only use SPL and not TPL+SPL like other RK3399 boards, this mean that SPL is loaded to and run from SRAM instead of DRAM. The SPL and U-Boot payload is loaded from SPI flash.
The U-Boot payload is located at 0x40000 (256 KiB) offset in SPI flash and because the BROM only read first 2 KiB for each 4 KiB page, the size of SPL (idbloader.img) is limited to max 128 KiB.
The chosen bss start address further limits the size of SPL to 120 KiB.
0xff8e0000 (SPL_BSS_START_ADDR) - 0xff8c2000 (SPL_TEXT_BASE) = 0x1e000
Update SPL_MAX_SIZE to reflect the 120 KiB max size limitation.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/chromebook_bob_defconfig | 2 +- configs/chromebook_kevin_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index d0321948697b..58e76f11472c 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -30,7 +30,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000 diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 120c11c04972..5adc276a746a 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -31,7 +31,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000
The rk3399-ficus board is only using SPL and not TPL+SPL like all other RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any technical reason why this board was left using only SPL.
Switch to use TPL+SPL and use common bss and stack addresses to allow for more options to be enabled in a future patch. Also add the missing DEFAULT_FDT_FILE option.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- configs/ficus-rk3399_defconfig | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 4859042d6b56..3bcd0fd66b91 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -2,32 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0xff8effff CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
The rk3399-ficus board is only using SPL and not TPL+SPL like all other RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any technical reason why this board was left using only SPL.
Switch to use TPL+SPL and use common bss and stack addresses to allow for more options to be enabled in a future patch. Also add the missing DEFAULT_FDT_FILE option.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
configs/ficus-rk3399_defconfig | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 4859042d6b56..3bcd0fd66b91 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -2,32 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0xff8effff CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y
I think we want to move CONFIG_SPL_STACK to match other RK3399 devices as well?
Indeed, it is currently set to 0xff8effff which matches the default value for when TPL was NOT enabled. 0x400000 is used for devices with TPL support. c.f. https://source.denx.de/u-boot/u-boot/-/commit/f113d7d3034672de7d074506a05a70...
Cheers, Quentin
Hi Quentin,
On 2024-04-02 15:10, Quentin Schulz wrote:
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
The rk3399-ficus board is only using SPL and not TPL+SPL like all other RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any technical reason why this board was left using only SPL.
Switch to use TPL+SPL and use common bss and stack addresses to allow for more options to be enabled in a future patch. Also add the missing DEFAULT_FDT_FILE option.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
configs/ficus-rk3399_defconfig | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 4859042d6b56..3bcd0fd66b91 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -2,32 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0xff8effff CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y
I think we want to move CONFIG_SPL_STACK to match other RK3399 devices as well?
This patch also drops SPL_SHARES_INIT_SP_ADDR and other bss + stack related options, so new safe default bss and stack addresses from [1] is used after this patch.
[1] https://source.denx.de/u-boot/u-boot/-/commit/008ba0d56d002f550570faa76c4752...
Regards, Jonas
Indeed, it is currently set to 0xff8effff which matches the default value for when TPL was NOT enabled. 0x400000 is used for devices with TPL support. c.f. https://source.denx.de/u-boot/u-boot/-/commit/f113d7d3034672de7d074506a05a70...
Cheers, Quentin
On Sun, 31 Mar 2024 at 21:30, Jonas Karlman jonas@kwiboo.se wrote:
The rk3399-ficus board is only using SPL and not TPL+SPL like all other RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any technical reason why this board was left using only SPL.
Switch to use TPL+SPL and use common bss and stack addresses to allow for more options to be enabled in a future patch. Also add the missing DEFAULT_FDT_FILE option.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Peter Robinson pbrobinson@gmail.com
I believe I have one of these if you need anything tested.
P
configs/ficus-rk3399_defconfig | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 4859042d6b56..3bcd0fd66b91 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -2,32 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0xff8effff CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -- 2.43.2
On 2024/4/1 04:28, Jonas Karlman wrote:
The rk3399-ficus board is only using SPL and not TPL+SPL like all other RK3399 boards, chromebook bob/kevin excluded. It does not seem to be any technical reason why this board was left using only SPL.
Switch to use TPL+SPL and use common bss and stack addresses to allow for more options to be enabled in a future patch. Also add the missing DEFAULT_FDT_FILE option.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
configs/ficus-rk3399_defconfig | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 4859042d6b56..3bcd0fd66b91 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -2,32 +2,22 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_TARGET_ROCK960_RK3399=y -CONFIG_SPL_STACK=0xff8effff CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y
Sort imply statements under ROCKCHIP_RK3399 alphabetically.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/Kconfig | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 22eccaaf5cb1..c0010fbb6887 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -260,30 +260,30 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT + imply BOOTSTD_FULL + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT + imply MISC + imply MISC_INIT_R imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply TPL_CLK + imply TPL_DM + imply TPL_DRIVERS_MISC imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT + imply TPL_OF_CONTROL + imply TPL_RAM + imply TPL_REGMAP + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL imply TPL_SYS_MALLOC_SIMPLE - imply TPL_DRIVERS_MISC - imply TPL_OF_CONTROL - imply TPL_DM - imply TPL_REGMAP imply TPL_SYSCON - imply TPL_RAM - imply TPL_CLK imply TPL_TINY_MEMSET - imply TPL_ROCKCHIP_COMMON_BOARD - imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT - imply BOOTSTD_FULL - imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT - imply MISC - imply ROCKCHIP_EFUSE - imply MISC_INIT_R help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53.
On 2024/4/1 04:28, Jonas Karlman wrote:
Sort imply statements under ROCKCHIP_RK3399 alphabetically.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 22eccaaf5cb1..c0010fbb6887 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -260,30 +260,30 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT
- imply BOOTSTD_FULL
- imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
- imply MISC
- imply MISC_INIT_R imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD
- imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD
- imply TPL_SERIAL
- imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
- imply TPL_CLK
- imply TPL_DM
- imply TPL_DRIVERS_MISC imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT
- imply TPL_OF_CONTROL
- imply TPL_RAM
- imply TPL_REGMAP
- imply TPL_ROCKCHIP_COMMON_BOARD
- imply TPL_SERIAL imply TPL_SYS_MALLOC_SIMPLE
- imply TPL_DRIVERS_MISC
- imply TPL_OF_CONTROL
- imply TPL_DM
- imply TPL_REGMAP imply TPL_SYSCON
- imply TPL_RAM
- imply TPL_CLK imply TPL_TINY_MEMSET
- imply TPL_ROCKCHIP_COMMON_BOARD
- imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
- imply BOOTSTD_FULL
- imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
- imply MISC
- imply ROCKCHIP_EFUSE
- imply MISC_INIT_R help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53.
The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8 crypto can speed up FIT checksum validation in SPL.
Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images.
Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation to almost all RK3399 boards.
The following boards have been excluded: - chromebook_bob: SPL max size limitation of 120 KiB - chromebook_kevin: SPL max size limitation of 120 KiB - puma-rk3399: SPL stack in SRAM and TPL+SPL combined max size limitation of 224 KiB
Also imply OF_LIVE to help speed up init of U-Boot proper and disable CONFIG_SPL_RAW_IMAGE_SUPPORT on leez-rk3399 to ensure SPL does not try to jump to code that failed checksum validation.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/Kconfig | 5 +++++ configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/puma-rk3399_defconfig | 2 +- configs/rock-4se-rk3399_defconfig | 2 -- configs/rock-pi-4-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 2 -- 8 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c0010fbb6887..eb74cd850409 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -260,15 +260,20 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT + imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R + imply OF_LIVE imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON + imply SPL_FIT_SIGNATURE imply SPL_ROCKCHIP_COMMON_BOARD imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply TPL_CLK diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 58e76f11472c..5d8037d31422 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 5adc276a746a..54ba2fdd136f 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index e5088341389a..2831cfb36689 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2759e1a9520..fe7aac791271 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 @@ -52,7 +53,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 712502517eb2..04622df3c0a0 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -15,8 +15,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 315b8b853fc3..9036c51de421 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -19,7 +19,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_SPL_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index d66b4a9d8900..062477286708 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -17,8 +17,6 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_USE_PREBOOT=y
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8 crypto can speed up FIT checksum validation in SPL.
Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images.
Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation to almost all RK3399 boards.
The following boards have been excluded:
- chromebook_bob: SPL max size limitation of 120 KiB
- chromebook_kevin: SPL max size limitation of 120 KiB
- puma-rk3399: SPL stack in SRAM and TPL+SPL combined max size limitation of 224 KiB
I think we should move the SPL stack out of SRAM, thanks for hinting at this. This is clearly something I missed when migrating Puma to TPL+SPL as all other devices were migrated way earlier than this board, c.f. https://source.denx.de/u-boot/u-boot/-/commit/f113d7d3034672de7d074506a05a70... for the default address.
Considering that SPL_MAX_SIZE is set to 0x2e000 (184K) right now, we should fail if we reach that size. But I couldn't with applying the same changes as in this patch, is there something I'm missing that prevents this from happening on Puma? Just trying to figure out what we need to do to not stay too far from most RK3399 devices :)
""" diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2aa02ec74b..f3d23fa3f11 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -21,8 +21,12 @@ CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_ARMV8_SET_SMPEN=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y @@ -115,4 +119,5 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +# CONFIG_RSA is not set CONFIG_ERRNO_STR=y """
(not booted).
Additionally, I think I should be able to bump SPL_MAX_SIZE to 0x30000 (224K offset for U-Boot proper on MMC - 32K offset for TPL+SPL on MMC), don't you think?
Backward compatibility is a PITA :)
Cheers, Quentin
Hi Quentin,
On 2024-04-02 15:22, Quentin Schulz wrote:
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8 crypto can speed up FIT checksum validation in SPL.
Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images.
Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation to almost all RK3399 boards.
The following boards have been excluded:
- chromebook_bob: SPL max size limitation of 120 KiB
- chromebook_kevin: SPL max size limitation of 120 KiB
- puma-rk3399: SPL stack in SRAM and TPL+SPL combined max size limitation of 224 KiB
I think we should move the SPL stack out of SRAM, thanks for hinting at this. This is clearly something I missed when migrating Puma to TPL+SPL as all other devices were migrated way earlier than this board, c.f. https://source.denx.de/u-boot/u-boot/-/commit/f113d7d3034672de7d074506a05a70... for the default address.
Great, I included a patch in v2 to use same bss and stack addresses as most other rk3399 boards.
Considering that SPL_MAX_SIZE is set to 0x2e000 (184K) right now, we should fail if we reach that size. But I couldn't with applying the same changes as in this patch, is there something I'm missing that prevents this from happening on Puma? Just trying to figure out what we need to do to not stay too far from most RK3399 devices :)
Sure, I have changed to not exclude puma in v2.
""" diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2aa02ec74b..f3d23fa3f11 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -21,8 +21,12 @@ CONFIG_DEBUG_UART_BASE=0xFF180000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_ARMV8_SET_SMPEN=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y @@ -115,4 +119,5 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +# CONFIG_RSA is not set CONFIG_ERRNO_STR=y """
(not booted).
Additionally, I think I should be able to bump SPL_MAX_SIZE to 0x30000 (224K offset for U-Boot proper on MMC - 32K offset for TPL+SPL on MMC), don't you think?
Not sure what the best value would be, if I am not mistaken the 224 KiB limit is for the combined header+TPL+SPL (idbloader.img). A quick test build show TPL to be around 52 KiB, that leaves around 172 KiB for SPL, the SPL binary currently only take up around 132 KiB. With CONFIG_LTO=y build output shrink a little bit to 50 KiB + 117 KiB.
I did not include any change to SPL_MAX_SIZE in v2.
Regards, Jonas
Backward compatibility is a PITA :)
Cheers, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
The RK3399 SoC support the ARMv8 Cryptography Extensions, use of ARMv8 crypto can speed up FIT checksum validation in SPL.
Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images.
Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation to almost all RK3399 boards.
The following boards have been excluded:
- chromebook_bob: SPL max size limitation of 120 KiB
- chromebook_kevin: SPL max size limitation of 120 KiB
- puma-rk3399: SPL stack in SRAM and TPL+SPL combined max size limitation of 224 KiB
Also imply OF_LIVE to help speed up init of U-Boot proper and disable CONFIG_SPL_RAW_IMAGE_SUPPORT on leez-rk3399 to ensure SPL does not try to jump to code that failed checksum validation.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 5 +++++ configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/puma-rk3399_defconfig | 2 +- configs/rock-4se-rk3399_defconfig | 2 -- configs/rock-pi-4-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 2 -- 8 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c0010fbb6887..eb74cd850409 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -260,15 +260,20 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT
- imply ARMV8_CRYPTO
- imply ARMV8_SET_SMPEN imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
- imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R
- imply OF_LIVE imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFER imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON
- imply SPL_FIT_SIGNATURE imply SPL_ROCKCHIP_COMMON_BOARD imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply TPL_CLK
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 58e76f11472c..5d8037d31422 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 5adc276a746a..54ba2fdd136f 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index e5088341389a..2831cfb36689 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -15,6 +15,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2759e1a9520..fe7aac791271 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y +# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 @@ -52,7 +53,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 712502517eb2..04622df3c0a0 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -15,8 +15,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 315b8b853fc3..9036c51de421 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -19,7 +19,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_SPL_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index d66b4a9d8900..062477286708 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -17,8 +17,6 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_USE_PREBOOT=y
The RK3399 SoC contain a crypto engine block that can generate random numbers.
Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the random generator on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/Kconfig | 2 ++ configs/chromebook_bob_defconfig | 2 -- configs/chromebook_kevin_defconfig | 2 -- configs/evb-rk3399_defconfig | 2 -- configs/firefly-rk3399_defconfig | 2 -- configs/pinebook-pro-rk3399_defconfig | 2 -- configs/pinephone-pro-rk3399_defconfig | 2 -- configs/roc-pc-rk3399_defconfig | 2 -- configs/rock960-rk3399_defconfig | 2 -- configs/rockpro64-rk3399_defconfig | 2 -- 10 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index eb74cd850409..e18d7f373f77 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -264,12 +264,14 @@ config ROCKCHIP_RK3399 imply ARMV8_SET_SMPEN imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT + imply DM_RNG imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R imply OF_LIVE imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFER + imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 5d8037d31422..6e203a6cf0e1 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -89,8 +89,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 54ba2fdd136f..e3d16f44d62a 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -90,8 +90,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index d81c7f9604e1..c4936768ffb6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -47,8 +47,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 545c047c6df8..8f68ffbd3a49 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -45,8 +45,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 23ac24a0bffe..e4aad1b710cb 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -75,8 +75,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 8c6323f6c516..285c47d76b6e 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -65,8 +65,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index a41f71d9e167..5d6e6b17091f 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -60,8 +60,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 13575c580054..7a4a3df85b1b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -52,8 +52,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 062477286708..368ef7c4b5db 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -68,8 +68,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
The RK3399 SoC contain a crypto engine block that can generate random numbers.
Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the random generator on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Thanks, Quentin
On Sun, 31 Mar 2024 at 21:29, Jonas Karlman jonas@kwiboo.se wrote:
The RK3399 SoC contain a crypto engine block that can generate random numbers.
Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the random generator on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Peter Robinson pbrobinson@gmail.com
Looks good, I meant to do this ages ago.
arch/arm/mach-rockchip/Kconfig | 2 ++ configs/chromebook_bob_defconfig | 2 -- configs/chromebook_kevin_defconfig | 2 -- configs/evb-rk3399_defconfig | 2 -- configs/firefly-rk3399_defconfig | 2 -- configs/pinebook-pro-rk3399_defconfig | 2 -- configs/pinephone-pro-rk3399_defconfig | 2 -- configs/roc-pc-rk3399_defconfig | 2 -- configs/rock960-rk3399_defconfig | 2 -- configs/rockpro64-rk3399_defconfig | 2 -- 10 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index eb74cd850409..e18d7f373f77 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -264,12 +264,14 @@ config ROCKCHIP_RK3399 imply ARMV8_SET_SMPEN imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
imply DM_RNG imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R imply OF_LIVE imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFERimply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMONdiff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 5d8037d31422..6e203a6cf0e1 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -89,8 +89,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 54ba2fdd136f..e3d16f44d62a 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -90,8 +90,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index d81c7f9604e1..c4936768ffb6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -47,8 +47,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 545c047c6df8..8f68ffbd3a49 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -45,8 +45,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 23ac24a0bffe..e4aad1b710cb 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -75,8 +75,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 8c6323f6c516..285c47d76b6e 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -65,8 +65,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index a41f71d9e167..5d6e6b17091f 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -60,8 +60,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 13575c580054..7a4a3df85b1b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -52,8 +52,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 062477286708..368ef7c4b5db 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -68,8 +68,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 -- 2.43.2
On 2024/4/1 04:28, Jonas Karlman wrote:
The RK3399 SoC contain a crypto engine block that can generate random numbers.
Imply DM_RNG and RNG_ROCKCHIP Kconfig options to take advantage of the random generator on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 2 ++ configs/chromebook_bob_defconfig | 2 -- configs/chromebook_kevin_defconfig | 2 -- configs/evb-rk3399_defconfig | 2 -- configs/firefly-rk3399_defconfig | 2 -- configs/pinebook-pro-rk3399_defconfig | 2 -- configs/pinephone-pro-rk3399_defconfig | 2 -- configs/roc-pc-rk3399_defconfig | 2 -- configs/rock960-rk3399_defconfig | 2 -- configs/rockpro64-rk3399_defconfig | 2 -- 10 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index eb74cd850409..e18d7f373f77 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -264,12 +264,14 @@ config ROCKCHIP_RK3399 imply ARMV8_SET_SMPEN imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
- imply DM_RNG imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R imply OF_LIVE imply PARTITION_TYPE_GUID imply PRE_CONSOLE_BUFFER
- imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 5d8037d31422..6e203a6cf0e1 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -89,8 +89,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 54ba2fdd136f..e3d16f44d62a 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -90,8 +90,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index d81c7f9604e1..c4936768ffb6 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -47,8 +47,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 545c047c6df8..8f68ffbd3a49 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -45,8 +45,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 23ac24a0bffe..e4aad1b710cb 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -75,8 +75,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 8c6323f6c516..285c47d76b6e 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -65,8 +65,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index a41f71d9e167..5d6e6b17091f 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -60,8 +60,6 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 13575c580054..7a4a3df85b1b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -52,8 +52,6 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 062477286708..368ef7c4b5db 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -68,8 +68,6 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2
Imply support for GbE PHY status parsing and configuration when support for onboard ethernet is enabled.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index e18d7f373f77..a07ad38f2efc 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -270,6 +270,7 @@ config ROCKCHIP_RK3399 imply MISC_INIT_R imply OF_LIVE imply PARTITION_TYPE_GUID + imply PHY_GIGE if GMAC_ROCKCHIP imply PRE_CONSOLE_BUFFER imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
Imply support for GbE PHY status parsing and configuration when support for onboard ethernet is enabled.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Thanks, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
Imply support for GbE PHY status parsing and configuration when support for onboard ethernet is enabled.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index e18d7f373f77..a07ad38f2efc 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -270,6 +270,7 @@ config ROCKCHIP_RK3399 imply MISC_INIT_R imply OF_LIVE imply PARTITION_TYPE_GUID
- imply PHY_GIGE if GMAC_ROCKCHIP imply PRE_CONSOLE_BUFFER imply RNG_ROCKCHIP imply ROCKCHIP_COMMON_BOARD
Imply OF_LIBFDT_OVERLAY Kconfig options to add device tree overlay support on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/Kconfig | 1 + configs/rock-4c-plus-rk3399_defconfig | 1 - configs/rock-4se-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock-pi-4c-rk3399_defconfig | 1 - 5 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index a07ad38f2efc..8dca9d2853b4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -268,6 +268,7 @@ config ROCKCHIP_RK3399 imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R + imply OF_LIBFDT_OVERLAY imply OF_LIVE imply PARTITION_TYPE_GUID imply PHY_GIGE if GMAC_ROCKCHIP diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index bebea4fd0691..6c69e8bdcb92 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPI4_RK3399=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 04622df3c0a0..e5ed81022bd6 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPI4_RK3399=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 9036c51de421..2801becedb4b 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -6,7 +6,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index e1adec600174..72d37bff9e9a 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPI4_RK3399=y
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
Imply OF_LIBFDT_OVERLAY Kconfig options to add device tree overlay support on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Thanks, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
Imply OF_LIBFDT_OVERLAY Kconfig options to add device tree overlay support on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 1 + configs/rock-4c-plus-rk3399_defconfig | 1 - configs/rock-4se-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock-pi-4c-rk3399_defconfig | 1 - 5 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index a07ad38f2efc..8dca9d2853b4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -268,6 +268,7 @@ config ROCKCHIP_RK3399 imply LEGACY_IMAGE_FORMAT imply MISC imply MISC_INIT_R
- imply OF_LIBFDT_OVERLAY imply OF_LIVE imply PARTITION_TYPE_GUID imply PHY_GIGE if GMAC_ROCKCHIP
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index bebea4fd0691..6c69e8bdcb92 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPI4_RK3399=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 04622df3c0a0..e5ed81022bd6 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPI4_RK3399=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 9036c51de421..2801becedb4b 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -6,7 +6,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPI_IMAGE=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index e1adec600174..72d37bff9e9a 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCKPI4_RK3399=y
The TPL and/or SPL control FDT on RK3399 boards does not contain any node with a compatible that is supported by driver/misc/ drivers.
Remove use of xPL_MISC_DRIVERS options to stop including e.g an unused efuse driver in TPL and/or SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/mach-rockchip/Kconfig | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 8dca9d2853b4..bc03d69a7f5c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -250,7 +250,6 @@ config ROCKCHIP_RK3399 select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL - select SPL_DRIVERS_MISC select CLK select FIT select PINCTRL @@ -282,7 +281,6 @@ config ROCKCHIP_RK3399 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply TPL_CLK imply TPL_DM - imply TPL_DRIVERS_MISC imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_OF_CONTROL
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
The TPL and/or SPL control FDT on RK3399 boards does not contain any node with a compatible that is supported by driver/misc/ drivers.
Remove use of xPL_MISC_DRIVERS options to stop including e.g an unused efuse driver in TPL and/or SPL.
This also makes each board maintainer responsible for enabling CrOS EC (Embedded Controller on Chromebooks) and/or IO domain if they need it in TPL/SPL. But considering Gru Bob and Kevin don't seem to be enabling EC support in TPL/SPL and that IO domain isn't enabled for any board in TPL/SPL,
Reviewed-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Thanks, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
The TPL and/or SPL control FDT on RK3399 boards does not contain any node with a compatible that is supported by driver/misc/ drivers.
Remove use of xPL_MISC_DRIVERS options to stop including e.g an unused efuse driver in TPL and/or SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/Kconfig | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 8dca9d2853b4..bc03d69a7f5c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -250,7 +250,6 @@ config ROCKCHIP_RK3399 select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL
- select SPL_DRIVERS_MISC select CLK select FIT select PINCTRL
@@ -282,7 +281,6 @@ config ROCKCHIP_RK3399 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply TPL_CLK imply TPL_DM
- imply TPL_DRIVERS_MISC imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_OF_CONTROL
A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl", &sdhci and &sdmmc.
Move this to rk3399-u-boot.dtsi and make this default for boards currently missing a u-boot,spl-boot-order prop.
The &spi_flash reference has been dropped from spl-boot-order now that boot source id is cached and "same-as-spl" can be resolved into the SPI flash node.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 - arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 4 ---- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-rock960-u-boot.dtsi | 5 ----- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 +---- arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 ------ 15 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi index a3f27566e438..6c07de98fa01 100644 --- a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi +++ b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi @@ -9,7 +9,6 @@ / { chosen { stdout-path = "serial2:1500000n8"; - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; };
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index dfce63e4d428..796ac9642399 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -9,7 +9,6 @@ / { chosen { stdout-path = "serial2:1500000n8"; - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; }; };
diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi index 38e0897db91d..67b63a835238 100644 --- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -5,9 +5,3 @@
#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi index c58ad95d120a..1f5fda1d0f1d 100644 --- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi"
-/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi index a7039d74a016..4a3b23e48313 100644 --- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi index c638ce259731..03b596850635 100644 --- a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi +++ b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index a9d10592d573..a126bbaf086f 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -5,12 +5,6 @@
#include "rk3399-u-boot.dtsi"
-/{ - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &sdmmc { pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; }; diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index 88a77cad8d43..83b0c44e9ec5 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; - }; -}; - &edp { rockchip,panel = <&edp_panel>; }; diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index cabf0a9dae89..e29757590611 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &rng { status = "okay"; }; diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index c8f4418a7389..e390cf3abab5 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr4-100.dtsi"
/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc; - }; - vcc_hub_en: vcc_hub_en-regulator { compatible = "regulator-fixed"; enable-active-high; diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index 60122f3bcd6c..b3bfc77f7569 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -}; - &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi index c190089e2643..55716ba4df73 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; - vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; @@ -22,5 +18,4 @@ regulator-init-microvolt = <950000>; vin-supply = <&vcc5v0_sys>; }; - }; diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 089732524a76..b15e5392c3cf 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -5,11 +5,8 @@
#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" + / { - chosen { - u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci; - }; - smbios { compatible = "u-boot,sysinfo-smbios"; smbios { diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 87b173e59579..fe045ca81749 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -14,6 +14,10 @@ spi1 = &spi1; };
+ chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; + cic: syscon@ff620000 { bootph-all; compatible = "rockchip,rk3399-cic", "syscon"; diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi index 7c66e1145a50..946a0230dbb4 100644 --- a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi +++ b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi @@ -5,9 +5,3 @@
#include "rk3399pro-u-boot.dtsi" #include "rk3399-sdram-lpddr3-4GB-1600.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; - }; -};
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl", &sdhci and &sdmmc.
Move this to rk3399-u-boot.dtsi and make this default for boards currently missing a u-boot,spl-boot-order prop.
The &spi_flash reference has been dropped from spl-boot-order now that boot source id is cached and "same-as-spl" can be resolved into the SPI flash node.
This is not really the same thing.
This prevents from having U-Boot proper in SPI and TPL+SPL on eMMC/SD card. Is this a real usecase? I don't know, we do support it on Puma (though I know you haven't changed it in this commit). I guess we could still have the devices with SPI flashes have their own u-boot,spl-boot-order if they want.
So, in short, I would at the very least document this new limitation in the commit log but have nothing against the change (my board not being impacted by it :) ).
Cheers, Quentin
Hi Quentin,
On 2024-04-02 16:02, Quentin Schulz wrote:
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl", &sdhci and &sdmmc.
Move this to rk3399-u-boot.dtsi and make this default for boards currently missing a u-boot,spl-boot-order prop.
The &spi_flash reference has been dropped from spl-boot-order now that boot source id is cached and "same-as-spl" can be resolved into the SPI flash node.
This is not really the same thing.
This prevents from having U-Boot proper in SPI and TPL+SPL on eMMC/SD card. Is this a real usecase? I don't know, we do support it on Puma (though I know you haven't changed it in this commit). I guess we could still have the devices with SPI flashes have their own u-boot,spl-boot-order if they want.
Agree, I tweaked the commit message a little bit in v2.
I think before the SPI flash node had to be included in spl-boot-order to be able to load FIT from SPI flash, so the inclusion has probably mostly been an effect of that.
So, in short, I would at the very least document this new limitation in the commit log but have nothing against the change (my board not being impacted by it :) ).
Agree, I have been very restrictive and try not to change any behavior on gru based and puma targets :-
Regards, Jonas
Cheers, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
A lot of RK3399 boards use a u-boot,spl-boot-order of "same-as-spl", &sdhci and &sdmmc.
Move this to rk3399-u-boot.dtsi and make this default for boards currently missing a u-boot,spl-boot-order prop.
The &spi_flash reference has been dropped from spl-boot-order now that boot source id is cached and "same-as-spl" can be resolved into the SPI flash node.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 - arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 4 ---- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 ------ arch/arm/dts/rk3399-rock960-u-boot.dtsi | 5 ----- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 5 +---- arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 ------ 15 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi index a3f27566e438..6c07de98fa01 100644 --- a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi +++ b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi @@ -9,7 +9,6 @@ / { chosen { stdout-path = "serial2:1500000n8";
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index dfce63e4d428..796ac9642399 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -9,7 +9,6 @@ / { chosen { stdout-path = "serial2:1500000n8";
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi index 38e0897db91d..67b63a835238 100644 --- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -5,9 +5,3 @@
#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-}; diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi index c58ad95d120a..1f5fda1d0f1d 100644 --- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-};
- &vdd_log { regulator-init-microvolt = <950000>; };
diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi index a7039d74a016..4a3b23e48313 100644 --- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-};
- &vdd_log { regulator-init-microvolt = <950000>; };
diff --git a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi index c638ce259731..03b596850635 100644 --- a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi +++ b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-};
- &vdd_log { regulator-init-microvolt = <950000>; };
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index a9d10592d573..a126bbaf086f 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -5,12 +5,6 @@
#include "rk3399-u-boot.dtsi"
-/{
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-};
- &sdmmc { pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; };
diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index 88a77cad8d43..83b0c44e9ec5 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc;- };
-};
- &edp { rockchip,panel = <&edp_panel>; };
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index cabf0a9dae89..e29757590611 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-};
- &rng { status = "okay"; };
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index c8f4418a7389..e390cf3abab5 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr4-100.dtsi"
/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc;- };
- vcc_hub_en: vcc_hub_en-regulator { compatible = "regulator-fixed"; enable-active-high;
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index 60122f3bcd6c..b3bfc77f7569 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-};
- &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v;
diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi index c190089e2643..55716ba4df73 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
- vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>;
@@ -22,5 +18,4 @@ regulator-init-microvolt = <950000>; vin-supply = <&vcc5v0_sys>; };
- };
diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 089732524a76..b15e5392c3cf 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -5,11 +5,8 @@
#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
- / {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;- };
smbios { compatible = "u-boot,sysinfo-smbios"; smbios {diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 87b173e59579..fe045ca81749 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -14,6 +14,10 @@ spi1 = &spi1; };
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
- cic: syscon@ff620000 { bootph-all; compatible = "rockchip,rk3399-cic", "syscon";
diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi index 7c66e1145a50..946a0230dbb4 100644 --- a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi +++ b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi @@ -5,9 +5,3 @@
#include "rk3399pro-u-boot.dtsi" #include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
-/ {
- chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;- };
-};
When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due to it being missing or checksum validation fails there can be a fallback to read FIT from SD-card. However, without proper pinctrl configuration reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 17 2024 - 22:54:45 +0000) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 Card did not respond to voltage select! : -110 mmc_init: -95, time 12 spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices (err=-6) ### ERROR ### Please RESET the board ###
Fix this by tagging related sdhci and sdmmc pinctrl nodes with bootph props. Also sort and move common nodes shared by all boards to the SoC u-boot.dtsi. Finally imply the SPL_DM_SEQ_ALIAS Kconfig option to enable it on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 - arch/arm/dts/rk3399-ficus-u-boot.dtsi | 8 ++ arch/arm/dts/rk3399-gru-u-boot.dtsi | 24 ++++++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 12 +++ arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 +++ arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 17 ++++- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 2 - arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 19 ++--- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 41 ++++++---- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 8 ++ arch/arm/dts/rk3399-rock960-u-boot.dtsi | 8 ++ arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 17 ++++- arch/arm/dts/rk3399-u-boot.dtsi | 75 +++++++++++++++---- arch/arm/mach-rockchip/Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/chromebook_kevin_defconfig | 1 - configs/eaidk-610-rk3399_defconfig | 2 +- configs/evb-rk3399_defconfig | 2 +- configs/ficus-rk3399_defconfig | 2 +- configs/firefly-rk3399_defconfig | 2 +- configs/khadas-edge-captain-rk3399_defconfig | 2 +- configs/khadas-edge-rk3399_defconfig | 2 +- configs/khadas-edge-v-rk3399_defconfig | 2 +- configs/leez-rk3399_defconfig | 2 +- configs/nanopc-t4-rk3399_defconfig | 4 +- configs/nanopi-m4-2gb-rk3399_defconfig | 4 +- configs/nanopi-m4-rk3399_defconfig | 4 +- configs/nanopi-m4b-rk3399_defconfig | 4 +- configs/nanopi-neo4-rk3399_defconfig | 4 +- configs/nanopi-r4s-rk3399_defconfig | 4 +- configs/orangepi-rk3399_defconfig | 4 +- configs/pinebook-pro-rk3399_defconfig | 5 +- configs/pinephone-pro-rk3399_defconfig | 3 +- configs/puma-rk3399_defconfig | 1 - configs/roc-pc-mezzanine-rk3399_defconfig | 4 +- configs/roc-pc-rk3399_defconfig | 4 +- configs/rock-4c-plus-rk3399_defconfig | 2 +- configs/rock-4se-rk3399_defconfig | 2 +- configs/rock-pi-4-rk3399_defconfig | 3 +- configs/rock-pi-4c-rk3399_defconfig | 2 +- configs/rock-pi-n10-rk3399pro_defconfig | 2 +- configs/rock960-rk3399_defconfig | 2 +- configs/rockpro64-rk3399_defconfig | 5 +- 43 files changed, 243 insertions(+), 83 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index 796ac9642399..9df4a02c3e74 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -38,7 +38,6 @@ };
&sdmmc { - bootph-all; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi index 67b63a835238..d821cabfaa67 100644 --- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -5,3 +5,11 @@
#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" + +&pcfg_pull_none_18ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index b1604a6872c0..0cc40eb6d6f6 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -54,6 +54,30 @@ enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; };
+&sdhci { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_bus4 { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_cd { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_clk { + /delete-property/ bootph-pre-ram; +}; + +&sdmmc_cmd { + /delete-property/ bootph-pre-ram; +}; + &spi5 { spi-activate-delay = <100>; spi-max-frequency = <3000000>; diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index a126bbaf086f..e0d7a518dfc2 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -5,6 +5,18 @@
#include "rk3399-u-boot.dtsi"
+&gpio0 { + bootph-pre-ram; +}; + &sdmmc { pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; }; + +&sdmmc0_pwr_h { + bootph-pre-ram; +}; + +&vcc3v0_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi index d4327ea607c4..b7452eca2254 100644 --- a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi +++ b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi @@ -6,6 +6,18 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1333.dtsi"
+&gpio0 { + bootph-pre-ram; +}; + +&sdmmc0_pwr_h { + bootph-pre-ram; +}; + +&vcc3v0_sd { + bootph-pre-ram; +}; + &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index 83b0c44e9ec5..2341db444ef3 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -10,18 +10,29 @@ rockchip,panel = <&edp_panel>; };
+&gpio0 { + bootph-pre-ram; +}; + &sdhci { max-frequency = <25000000>; - bootph-all; };
&sdmmc { max-frequency = <20000000>; - bootph-all; +}; + +&sdmmc0_pwr_h_pin { + bootph-pre-ram; };
&spiflash { - bootph-all; + bootph-pre-ram; + bootph-some-ram; +}; + +&vcc3v0_sd { + bootph-pre-ram; };
&vdd_log { diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index e29757590611..b8f95b86d86b 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -12,10 +12,8 @@
&sdhci { max-frequency = <25000000>; - bootph-all; };
&sdmmc { max-frequency = <20000000>; - bootph-all; }; diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index 2b3ea6da88db..f48d395f972a 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -87,26 +87,27 @@ bootph-all; };
+&haikou_pin_hog { + bootph-all; +}; + &norflash { - bootph-all; -}; - -&pcfg_pull_none { - bootph-all; + bootph-pre-ram; + bootph-some-ram; };
-&pcfg_pull_up { +&uart0 { bootph-all; };
-&sdmmc_bus4 { +&uart0_cts { bootph-all; };
-&sdmmc_clk { +&uart0_rts { bootph-all; };
-&sdmmc_cmd { +&uart0_xfer { bootph-all; }; diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index e390cf3abab5..aecf7dbe383c 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -32,25 +32,38 @@ vin-supply = <&vcc_vbus_typec0>; };
+&gpio4 { + bootph-pre-ram; +}; + &spi1 { - spi_flash: flash@0 { - bootph-all; + flash@0 { + bootph-pre-ram; + bootph-some-ram; }; };
+&vcc3v0_sd { + bootph-pre-ram; +}; + +&vcc3v0_sd_en { + bootph-pre-ram; +}; + +&vcc5v0_host { + regulator-always-on; +}; + +&vcc_sdio { + regulator-always-on; +}; + +&vcc_sys { + regulator-always-on; +}; + &vdd_log { regulator-min-microvolt = <430000>; regulator-init-microvolt = <950000>; }; - -&vcc5v0_host { - regulator-always-on; -}; - -&vcc_sys { - regulator-always-on; -}; - -&vcc_sdio { - regulator-always-on; -}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 5c1c451b8f85..9785b97b9eea 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -3,3 +3,11 @@ * Copyright (c) 2023 Radxa Limited */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +&pcfg_pull_none_18ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi index 55716ba4df73..b1db07a107ec 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -19,3 +19,11 @@ vin-supply = <&vcc5v0_sys>; }; }; + +&pcfg_pull_none_18ma { + bootph-pre-ram; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index b15e5392c3cf..43b67991fe5a 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -26,8 +26,10 @@ }; }; }; +};
- +&gpio0 { + bootph-pre-ram; };
&sdhci { @@ -35,12 +37,21 @@ mmc-ddr-1_8v; };
+&sdmmc0_pwr_h { + bootph-pre-ram; +}; + &spi1 { - spi_flash: flash@0 { - bootph-all; + flash@0 { + bootph-pre-ram; + bootph-some-ram; }; };
+&vcc3v0_sd { + bootph-pre-ram; +}; + &vdd_center { regulator-min-microvolt = <950000>; regulator-max-microvolt = <950000>; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index fe045ca81749..69e6b808a69b 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -94,13 +94,22 @@ };
&emmc_phy { - bootph-all; + bootph-pre-ram; + bootph-some-ram; };
&grf { bootph-all; };
+&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_up { + bootph-all; +}; + &pinctrl { bootph-all; }; @@ -109,47 +118,81 @@ bootph-all; };
-&pmugrf { - bootph-all; -}; - -&pmu { - bootph-all; -}; - &pmucru { bootph-all; };
+&pmugrf { + bootph-all; +}; + &sdhci { + bootph-pre-ram; + bootph-some-ram; max-frequency = <200000000>; - bootph-all; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; };
&sdmmc { - bootph-all; + bootph-pre-ram; + bootph-some-ram;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; };
+&sdmmc_bus4 { + bootph-pre-ram; +}; + +&sdmmc_cd { + bootph-pre-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; +}; + &spi1 { - bootph-all; + bootph-pre-ram; + bootph-some-ram; };
-&uart0 { - bootph-all; +&spi1_clk { + bootph-pre-ram; +}; + +&spi1_cs0 { + bootph-pre-ram; +}; + +&spi1_rx { + bootph-pre-ram; +}; + +&spi1_tx { + bootph-pre-ram; };
&uart2 { bootph-all; + clock-frequency = <24000000>; +}; + +&uart2c_xfer { + bootph-all; };
&vopb { - bootph-all; + bootph-some-ram; };
&vopl { - bootph-all; + bootph-some-ram; }; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index bc03d69a7f5c..1b9bfa313fc0 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -276,6 +276,7 @@ config ROCKCHIP_RK3399 imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON + imply SPL_DM_SEQ_ALIAS imply SPL_FIT_SIGNATURE imply SPL_ROCKCHIP_COMMON_BOARD imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 6e203a6cf0e1..7022ee51e6c7 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -61,7 +61,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index e3d16f44d62a..57d43677eb00 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -62,7 +62,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 4d8b495ccfec..eba6f90c605b 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index c4936768ffb6..afb79987464f 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 3bcd0fd66b91..f4e3ebba8f46 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 8f68ffbd3a49..db98926b627a 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 310250ed4a52..230b9d796442 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 3fe5542d1256..9f13cbf58398 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 4b41454d710d..abc4f2054cfd 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 2831cfb36689..13453e523444 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index cdfacb66e678..89c36e273a9b 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" @@ -28,7 +29,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -42,6 +43,7 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 51596f57ae35..eb1d2c1f51fc 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 2af84fb6ff17..bc0b90b3d861 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 1b76f98e0df7..678f4d9d823f 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index c176c5a12111..d9b7a90e8402 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index ea01d323541b..1fcccf2bae6e 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index c6a92b2decf3..703732ad15f0 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index e4aad1b710cb..dd8bc2b72cc3 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x8000 @@ -41,10 +42,9 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y @@ -72,6 +72,7 @@ CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 285c47d76b6e..c36898364b5d 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -40,10 +40,9 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index fe7aac791271..cc3d2cf3755d 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -61,7 +61,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 1ff4e15c8c10..e13356faabbc 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -38,10 +38,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -57,6 +56,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 5d6e6b17091f..dee342898d1f 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -38,10 +38,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -56,6 +55,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 6c69e8bdcb92..2024defb2bf0 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index e5ed81022bd6..9b2303fdf792 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 2801becedb4b..e5a2bba8e7ff 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -40,10 +40,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 72d37bff9e9a..4a9d1c531c10 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 6889cdcbf7d8..234d0c9ab0f5 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 7a4a3df85b1b..3b5ab7dc5781 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 368ef7c4b5db..173f8f75020d 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 @@ -38,10 +39,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_CMD_BOOTSTAGE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SATA=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y @@ -65,6 +65,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due to it being missing or checksum validation fails there can be a fallback to read FIT from SD-card. However, without proper pinctrl configuration reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 17 2024 - 22:54:45 +0000) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 Card did not respond to voltage select! : -110 mmc_init: -95, time 12 spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices (err=-6) ### ERROR ### Please RESET the board ###
Fix this by tagging related sdhci and sdmmc pinctrl nodes with bootph props. Also sort and move common nodes shared by all boards to the SoC u-boot.dtsi. Finally imply the SPL_DM_SEQ_ALIAS Kconfig option to enable it on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Review may be easier if we added all missing nodes in one commit, and then another commit to move the common nodes into rk3399-u-boot.dtsi.
For Puma,
Reviewed-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Thanks, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
When RK3399 boards run SPL from eMMC and fail to load FIT from eMMC due to it being missing or checksum validation fails there can be a fallback to read FIT from SD-card. However, without proper pinctrl configuration reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 17 2024 - 22:54:45 +0000) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 Card did not respond to voltage select! : -110 mmc_init: -95, time 12 spl: mmc init failed with error: -95 SPL: failed to boot from all boot devices (err=-6) ### ERROR ### Please RESET the board ###
Fix this by tagging related sdhci and sdmmc pinctrl nodes with bootph props. Also sort and move common nodes shared by all boards to the SoC u-boot.dtsi. Finally imply the SPL_DM_SEQ_ALIAS Kconfig option to enable it on all RK3399 boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 - arch/arm/dts/rk3399-ficus-u-boot.dtsi | 8 ++ arch/arm/dts/rk3399-gru-u-boot.dtsi | 24 ++++++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 12 +++ arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 +++ arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 17 ++++- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 2 - arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 19 ++--- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 41 ++++++---- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 8 ++ arch/arm/dts/rk3399-rock960-u-boot.dtsi | 8 ++ arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 17 ++++- arch/arm/dts/rk3399-u-boot.dtsi | 75 +++++++++++++++---- arch/arm/mach-rockchip/Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/chromebook_kevin_defconfig | 1 - configs/eaidk-610-rk3399_defconfig | 2 +- configs/evb-rk3399_defconfig | 2 +- configs/ficus-rk3399_defconfig | 2 +- configs/firefly-rk3399_defconfig | 2 +- configs/khadas-edge-captain-rk3399_defconfig | 2 +- configs/khadas-edge-rk3399_defconfig | 2 +- configs/khadas-edge-v-rk3399_defconfig | 2 +- configs/leez-rk3399_defconfig | 2 +- configs/nanopc-t4-rk3399_defconfig | 4 +- configs/nanopi-m4-2gb-rk3399_defconfig | 4 +- configs/nanopi-m4-rk3399_defconfig | 4 +- configs/nanopi-m4b-rk3399_defconfig | 4 +- configs/nanopi-neo4-rk3399_defconfig | 4 +- configs/nanopi-r4s-rk3399_defconfig | 4 +- configs/orangepi-rk3399_defconfig | 4 +- configs/pinebook-pro-rk3399_defconfig | 5 +- configs/pinephone-pro-rk3399_defconfig | 3 +- configs/puma-rk3399_defconfig | 1 - configs/roc-pc-mezzanine-rk3399_defconfig | 4 +- configs/roc-pc-rk3399_defconfig | 4 +- configs/rock-4c-plus-rk3399_defconfig | 2 +- configs/rock-4se-rk3399_defconfig | 2 +- configs/rock-pi-4-rk3399_defconfig | 3 +- configs/rock-pi-4c-rk3399_defconfig | 2 +- configs/rock-pi-n10-rk3399pro_defconfig | 2 +- configs/rock960-rk3399_defconfig | 2 +- configs/rockpro64-rk3399_defconfig | 5 +- 43 files changed, 243 insertions(+), 83 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index 796ac9642399..9df4a02c3e74 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -38,7 +38,6 @@ };
&sdmmc {
- bootph-all; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed;
diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi index 67b63a835238..d821cabfaa67 100644 --- a/arch/arm/dts/rk3399-ficus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -5,3 +5,11 @@
#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi"
+&pcfg_pull_none_18ma {
- bootph-pre-ram;
+};
+&pcfg_pull_up_8ma {
- bootph-pre-ram;
+}; diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index b1604a6872c0..0cc40eb6d6f6 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -54,6 +54,30 @@ enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; };
+&sdhci {
- /delete-property/ bootph-pre-ram;
+};
+&sdmmc {
- /delete-property/ bootph-pre-ram;
+};
+&sdmmc_bus4 {
- /delete-property/ bootph-pre-ram;
+};
+&sdmmc_cd {
- /delete-property/ bootph-pre-ram;
+};
+&sdmmc_clk {
- /delete-property/ bootph-pre-ram;
+};
+&sdmmc_cmd {
- /delete-property/ bootph-pre-ram;
+};
- &spi5 { spi-activate-delay = <100>; spi-max-frequency = <3000000>;
diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index a126bbaf086f..e0d7a518dfc2 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -5,6 +5,18 @@
#include "rk3399-u-boot.dtsi"
+&gpio0 {
- bootph-pre-ram;
+};
- &sdmmc { pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; };
+&sdmmc0_pwr_h {
- bootph-pre-ram;
+};
+&vcc3v0_sd {
- bootph-pre-ram;
+}; diff --git a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi index d4327ea607c4..b7452eca2254 100644 --- a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi +++ b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi @@ -6,6 +6,18 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1333.dtsi"
+&gpio0 {
- bootph-pre-ram;
+};
+&sdmmc0_pwr_h {
- bootph-pre-ram;
+};
+&vcc3v0_sd {
- bootph-pre-ram;
+};
- &vdd_log { regulator-init-microvolt = <950000>; };
diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index 83b0c44e9ec5..2341db444ef3 100644 --- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -10,18 +10,29 @@ rockchip,panel = <&edp_panel>; };
+&gpio0 {
- bootph-pre-ram;
+};
- &sdhci { max-frequency = <25000000>;
bootph-all; };
&sdmmc { max-frequency = <20000000>;
bootph-all;
+};
+&sdmmc0_pwr_h_pin {
bootph-pre-ram; };
&spiflash {
- bootph-all;
- bootph-pre-ram;
- bootph-some-ram;
+};
+&vcc3v0_sd {
bootph-pre-ram; };
&vdd_log {
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index e29757590611..b8f95b86d86b 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -12,10 +12,8 @@
&sdhci { max-frequency = <25000000>;
bootph-all; };
&sdmmc { max-frequency = <20000000>;
bootph-all; };
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index 2b3ea6da88db..f48d395f972a 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -87,26 +87,27 @@ bootph-all; };
+&haikou_pin_hog {
- bootph-all;
+};
- &norflash {
- bootph-all;
-};
-&pcfg_pull_none {
- bootph-all;
- bootph-pre-ram;
- bootph-some-ram; };
-&pcfg_pull_up { +&uart0 { bootph-all; };
-&sdmmc_bus4 { +&uart0_cts { bootph-all; };
-&sdmmc_clk { +&uart0_rts { bootph-all; };
-&sdmmc_cmd { +&uart0_xfer { bootph-all; }; diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index e390cf3abab5..aecf7dbe383c 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -32,25 +32,38 @@ vin-supply = <&vcc_vbus_typec0>; };
+&gpio4 {
- bootph-pre-ram;
+};
- &spi1 {
- spi_flash: flash@0 {
bootph-all;
- flash@0 {
bootph-pre-ram;bootph-some-ram;+&vcc3v0_sd {
- bootph-pre-ram;
+};
+&vcc3v0_sd_en {
- bootph-pre-ram;
+};
+&vcc5v0_host {
- regulator-always-on;
+};
+&vcc_sdio {
- regulator-always-on;
+};
+&vcc_sys {
- regulator-always-on;
+};
- &vdd_log { regulator-min-microvolt = <430000>; regulator-init-microvolt = <950000>; };
-&vcc5v0_host {
- regulator-always-on;
-};
-&vcc_sys {
- regulator-always-on;
-};
-&vcc_sdio {
- regulator-always-on;
-}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 5c1c451b8f85..9785b97b9eea 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -3,3 +3,11 @@
- Copyright (c) 2023 Radxa Limited
*/ #include "rk3399-rock-pi-4-u-boot.dtsi"
+&pcfg_pull_none_18ma {
- bootph-pre-ram;
+};
+&pcfg_pull_up_8ma {
- bootph-pre-ram;
+}; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi index 55716ba4df73..b1db07a107ec 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -19,3 +19,11 @@ vin-supply = <&vcc5v0_sys>; }; };
+&pcfg_pull_none_18ma {
- bootph-pre-ram;
+};
+&pcfg_pull_up_8ma {
- bootph-pre-ram;
+}; diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index b15e5392c3cf..43b67991fe5a 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -26,8 +26,10 @@ }; }; }; +};
+&gpio0 {
bootph-pre-ram; };
&sdhci {
@@ -35,12 +37,21 @@ mmc-ddr-1_8v; };
+&sdmmc0_pwr_h {
- bootph-pre-ram;
+};
- &spi1 {
- spi_flash: flash@0 {
bootph-all;
- flash@0 {
bootph-pre-ram;bootph-some-ram;+&vcc3v0_sd {
- bootph-pre-ram;
+};
- &vdd_center { regulator-min-microvolt = <950000>; regulator-max-microvolt = <950000>;
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index fe045ca81749..69e6b808a69b 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -94,13 +94,22 @@ };
&emmc_phy {
- bootph-all;
bootph-pre-ram;
bootph-some-ram; };
&grf { bootph-all; };
+&pcfg_pull_none {
- bootph-all;
+};
+&pcfg_pull_up {
- bootph-all;
+};
- &pinctrl { bootph-all; };
@@ -109,47 +118,81 @@ bootph-all; };
-&pmugrf {
- bootph-all;
-};
-&pmu {
- bootph-all;
-};
- &pmucru { bootph-all; };
+&pmugrf {
- bootph-all;
+};
- &sdhci {
- bootph-pre-ram;
- bootph-some-ram; max-frequency = <200000000>;
- bootph-all;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; };
&sdmmc {
- bootph-all;
bootph-pre-ram;
bootph-some-ram;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ u-boot,spl-fifo-mode; };
+&sdmmc_bus4 {
- bootph-pre-ram;
+};
+&sdmmc_cd {
- bootph-pre-ram;
+};
+&sdmmc_clk {
- bootph-pre-ram;
+};
+&sdmmc_cmd {
- bootph-pre-ram;
+};
- &spi1 {
- bootph-all;
- bootph-pre-ram;
- bootph-some-ram; };
-&uart0 {
- bootph-all;
+&spi1_clk {
- bootph-pre-ram;
+};
+&spi1_cs0 {
- bootph-pre-ram;
+};
+&spi1_rx {
- bootph-pre-ram;
+};
+&spi1_tx {
bootph-pre-ram; };
&uart2 { bootph-all;
clock-frequency = <24000000>;
+};
+&uart2c_xfer {
bootph-all; };
&vopb {
- bootph-all;
bootph-some-ram; };
&vopl {
- bootph-all;
- bootph-some-ram; };
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index bc03d69a7f5c..1b9bfa313fc0 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -276,6 +276,7 @@ config ROCKCHIP_RK3399 imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_EFUSE imply ROCKCHIP_SDRAM_COMMON
- imply SPL_DM_SEQ_ALIAS imply SPL_FIT_SIGNATURE imply SPL_ROCKCHIP_COMMON_BOARD imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 6e203a6cf0e1..7022ee51e6c7 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -61,7 +61,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index e3d16f44d62a..57d43677eb00 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -62,7 +62,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 4d8b495ccfec..eba6f90c605b 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index c4936768ffb6..afb79987464f 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 3bcd0fd66b91..f4e3ebba8f46 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 8f68ffbd3a49..db98926b627a 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 310250ed4a52..230b9d796442 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 3fe5542d1256..9f13cbf58398 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index 4b41454d710d..abc4f2054cfd 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 2831cfb36689..13453e523444 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -25,7 +25,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index cdfacb66e678..89c36e273a9b 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" @@ -28,7 +29,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -42,6 +43,7 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 51596f57ae35..eb1d2c1f51fc 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 2af84fb6ff17..bc0b90b3d861 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 1b76f98e0df7..678f4d9d823f 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index c176c5a12111..d9b7a90e8402 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index ea01d323541b..1fcccf2bae6e 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index c6a92b2decf3..703732ad15f0 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" @@ -25,7 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -38,6 +39,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index e4aad1b710cb..dd8bc2b72cc3 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x8000 @@ -41,10 +42,9 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y @@ -72,6 +72,7 @@ CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index 285c47d76b6e..c36898364b5d 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -40,10 +40,9 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index fe7aac791271..cc3d2cf3755d 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -61,7 +61,6 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 1ff4e15c8c10..e13356faabbc 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -38,10 +38,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -57,6 +56,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 5d6e6b17091f..dee342898d1f 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -38,10 +38,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -56,6 +55,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 6c69e8bdcb92..2024defb2bf0 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index e5ed81022bd6..9b2303fdf792 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 2801becedb4b..e5a2bba8e7ff 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -40,10 +40,9 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 72d37bff9e9a..4a9d1c531c10 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 6889cdcbf7d8..234d0c9ab0f5 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 7a4a3df85b1b..3b5ab7dc5781 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 368ef7c4b5db..173f8f75020d 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 @@ -38,10 +39,9 @@ CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_CMD_BOOTSTAGE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SATA=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y @@ -65,6 +65,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y
Sync rk3399-cru.h with one from linux v6.2+ and fix use of the SCLK_DDRCLK name that was only used by U-Boot.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-u-boot.dtsi | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- include/dt-bindings/clock/rk3399-cru.h | 30 ++++++++++++++------------ 3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 69e6b808a69b..adb64d17e040 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -44,7 +44,7 @@ compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_DDRCLK>; + clocks = <&cru SCLK_DDRC>; clock-names = "dmc_clk"; reg = <0x0 0xffa80000 0x0 0x0800 0x0 0xffa80800 0x0 0x1800 diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 80f65a237e8e..f0ce54067f8c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * return 0 to satisfy clk_set_defaults during device probe. */ return 0; - case SCLK_DDRCLK: + case SCLK_DDRC: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS: diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 211faf8fa891..39169d94a44e 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng zhengxing@rock-chips.com */
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H @@ -121,16 +122,17 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 -#define SCLK_USBPHY0_480M_SRC 168 -#define SCLK_USBPHY1_480M_SRC 169 -#define SCLK_DDRCLK 170 -#define SCLK_TESTOUT2 171 +#define SCLK_DDRC 168 +#define SCLK_TESTCLKOUT1 169 +#define SCLK_TESTCLKOUT2 170
#define DCLK_VOP0 180 #define DCLK_VOP1 181 #define DCLK_VOP0_DIV 182 #define DCLK_VOP1_DIV 183 #define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186
#define FCLK_CM0S 190
@@ -545,8 +547,8 @@ #define SRST_H_PERILP0 171 #define SRST_H_PERILP0_NOC 172 #define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 +#define SRST_CRYPTO0_S 174 +#define SRST_CRYPTO0_M 175
/* cru_softrst_con11 */ #define SRST_P_DCF 176 @@ -554,7 +556,7 @@ #define SRST_CM0S 178 #define SRST_CM0S_DBG 179 #define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 +#define SRST_CRYPTO0 181 #define SRST_P_PERILP1_SGRF 182 #define SRST_P_PERILP1_GRF 183 #define SRST_CRYPTO1_S 184 @@ -592,13 +594,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI4 217 -#define SRST_P_SPI5 218 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI4 222 -#define SRST_SPI5 223 +#define SRST_SPI3 222 +#define SRST_SPI4 223
/* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -720,8 +722,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI3 6 -#define SRST_SPI3 7 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9 #define SRST_P_TIMER_1 10
On Mon, 1 Apr 2024 at 02:01, Jonas Karlman jonas@kwiboo.se wrote:
Sync rk3399-cru.h with one from linux v6.2+ and fix use of the SCLK_DDRCLK name that was only used by U-Boot.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
arch/arm/dts/rk3399-u-boot.dtsi | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- include/dt-bindings/clock/rk3399-cru.h | 30 ++++++++++++++------------
You shouldn't need to sync this header but rather just drop it which will lead to ./dts/upstream/include/dt-bindings/clock/rk3399-cru.h being included automatically. Similarly you should be able to drop all other duplicate headers as demonstrated by this [1] patch-set.
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=399954
-Sumit
3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 69e6b808a69b..adb64d17e040 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -44,7 +44,7 @@ compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DDRCLK>;
clocks = <&cru SCLK_DDRC>; clock-names = "dmc_clk"; reg = <0x0 0xffa80000 0x0 0x0800 0x0 0xffa80800 0x0 0x1800diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 80f65a237e8e..f0ce54067f8c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * return 0 to satisfy clk_set_defaults during device probe. */ return 0;
case SCLK_DDRCLK:
case SCLK_DDRC: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS:diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 211faf8fa891..39169d94a44e 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /*
- Copyright (c) 2016 Rockchip Electronics Co. Ltd.
*/
- Author: Xing Zheng zhengxing@rock-chips.com
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H @@ -121,16 +122,17 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 -#define SCLK_USBPHY0_480M_SRC 168 -#define SCLK_USBPHY1_480M_SRC 169 -#define SCLK_DDRCLK 170 -#define SCLK_TESTOUT2 171 +#define SCLK_DDRC 168 +#define SCLK_TESTCLKOUT1 169 +#define SCLK_TESTCLKOUT2 170
#define DCLK_VOP0 180 #define DCLK_VOP1 181 #define DCLK_VOP0_DIV 182 #define DCLK_VOP1_DIV 183 #define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186
#define FCLK_CM0S 190
@@ -545,8 +547,8 @@ #define SRST_H_PERILP0 171 #define SRST_H_PERILP0_NOC 172 #define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 +#define SRST_CRYPTO0_S 174 +#define SRST_CRYPTO0_M 175
/* cru_softrst_con11 */ #define SRST_P_DCF 176 @@ -554,7 +556,7 @@ #define SRST_CM0S 178 #define SRST_CM0S_DBG 179 #define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 +#define SRST_CRYPTO0 181 #define SRST_P_PERILP1_SGRF 182 #define SRST_P_PERILP1_GRF 183 #define SRST_CRYPTO1_S 184 @@ -592,13 +594,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI4 217 -#define SRST_P_SPI5 218 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI4 222 -#define SRST_SPI5 223 +#define SRST_SPI3 222 +#define SRST_SPI4 223
/* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -720,8 +722,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI3 6 -#define SRST_SPI3 7 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9
#define SRST_P_TIMER_1 10
2.43.2
Hi Sumit,
On 2024-04-01 10:56, Sumit Garg wrote:
On Mon, 1 Apr 2024 at 02:01, Jonas Karlman jonas@kwiboo.se wrote:
Sync rk3399-cru.h with one from linux v6.2+ and fix use of the SCLK_DDRCLK name that was only used by U-Boot.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
arch/arm/dts/rk3399-u-boot.dtsi | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- include/dt-bindings/clock/rk3399-cru.h | 30 ++++++++++++++------------
You shouldn't need to sync this header but rather just drop it which will lead to ./dts/upstream/include/dt-bindings/clock/rk3399-cru.h being included automatically. Similarly you should be able to drop all other duplicate headers as demonstrated by this [1] patch-set.
Because of reviewability and being able to cherry-pick this series I would opt for first moving existing files to a newer state and then in a separate future series fully move to OF_UPSTREAM.
Regards, Jonas
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=399954
-Sumit
3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 69e6b808a69b..adb64d17e040 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -44,7 +44,7 @@ compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DDRCLK>;
clocks = <&cru SCLK_DDRC>; clock-names = "dmc_clk"; reg = <0x0 0xffa80000 0x0 0x0800 0x0 0xffa80800 0x0 0x1800diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 80f65a237e8e..f0ce54067f8c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * return 0 to satisfy clk_set_defaults during device probe. */ return 0;
case SCLK_DDRCLK:
case SCLK_DDRC: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS:diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 211faf8fa891..39169d94a44e 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /*
- Copyright (c) 2016 Rockchip Electronics Co. Ltd.
*/
- Author: Xing Zheng zhengxing@rock-chips.com
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H @@ -121,16 +122,17 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 -#define SCLK_USBPHY0_480M_SRC 168 -#define SCLK_USBPHY1_480M_SRC 169 -#define SCLK_DDRCLK 170 -#define SCLK_TESTOUT2 171 +#define SCLK_DDRC 168 +#define SCLK_TESTCLKOUT1 169 +#define SCLK_TESTCLKOUT2 170
#define DCLK_VOP0 180 #define DCLK_VOP1 181 #define DCLK_VOP0_DIV 182 #define DCLK_VOP1_DIV 183 #define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186
#define FCLK_CM0S 190
@@ -545,8 +547,8 @@ #define SRST_H_PERILP0 171 #define SRST_H_PERILP0_NOC 172 #define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 +#define SRST_CRYPTO0_S 174 +#define SRST_CRYPTO0_M 175
/* cru_softrst_con11 */ #define SRST_P_DCF 176 @@ -554,7 +556,7 @@ #define SRST_CM0S 178 #define SRST_CM0S_DBG 179 #define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 +#define SRST_CRYPTO0 181 #define SRST_P_PERILP1_SGRF 182 #define SRST_P_PERILP1_GRF 183 #define SRST_CRYPTO1_S 184 @@ -592,13 +594,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI4 217 -#define SRST_P_SPI5 218 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI4 222 -#define SRST_SPI5 223 +#define SRST_SPI3 222 +#define SRST_SPI4 223
/* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -720,8 +722,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI3 6 -#define SRST_SPI3 7 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9
#define SRST_P_TIMER_1 10
2.43.2
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-cru.h with one from linux v6.2+ and fix use of the SCLK_DDRCLK name that was only used by U-Boot.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-u-boot.dtsi | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- include/dt-bindings/clock/rk3399-cru.h | 30 ++++++++++++++------------ 3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 69e6b808a69b..adb64d17e040 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -44,7 +44,7 @@ compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_DDRCLK>;
clocks = <&cru SCLK_DDRC>;diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 80f65a237e8e..f0ce54067f8c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1049,7 +1049,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) * return 0 to satisfy clk_set_defaults during device probe. */ return 0;
- case SCLK_DDRCLK:
- case SCLK_DDRC: ret = rk3399_ddr_set_clk(priv->cru, rate); break; case PCLK_EFUSE1024NS:
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 211faf8fa891..39169d94a44e 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /*
- Copyright (c) 2016 Rockchip Electronics Co. Ltd.
- Author: Xing Zheng zhengxing@rock-chips.com
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
@@ -121,16 +122,17 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 -#define SCLK_USBPHY0_480M_SRC 168 -#define SCLK_USBPHY1_480M_SRC 169 -#define SCLK_DDRCLK 170 -#define SCLK_TESTOUT2 171 +#define SCLK_DDRC 168 +#define SCLK_TESTCLKOUT1 169 +#define SCLK_TESTCLKOUT2 170
#define DCLK_VOP0 180 #define DCLK_VOP1 181 #define DCLK_VOP0_DIV 182 #define DCLK_VOP1_DIV 183 #define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186
#define FCLK_CM0S 190
@@ -545,8 +547,8 @@ #define SRST_H_PERILP0 171 #define SRST_H_PERILP0_NOC 172 #define SRST_ROM 173 -#define SRST_CRYPTO_S 174 -#define SRST_CRYPTO_M 175 +#define SRST_CRYPTO0_S 174 +#define SRST_CRYPTO0_M 175
/* cru_softrst_con11 */ #define SRST_P_DCF 176 @@ -554,7 +556,7 @@ #define SRST_CM0S 178 #define SRST_CM0S_DBG 179 #define SRST_CM0S_PO 180 -#define SRST_CRYPTO 181 +#define SRST_CRYPTO0 181 #define SRST_P_PERILP1_SGRF 182 #define SRST_P_PERILP1_GRF 183 #define SRST_CRYPTO1_S 184 @@ -592,13 +594,13 @@ #define SRST_P_SPI0 214 #define SRST_P_SPI1 215 #define SRST_P_SPI2 216 -#define SRST_P_SPI4 217 -#define SRST_P_SPI5 218 +#define SRST_P_SPI3 217 +#define SRST_P_SPI4 218 #define SRST_SPI0 219 #define SRST_SPI1 220 #define SRST_SPI2 221 -#define SRST_SPI4 222 -#define SRST_SPI5 223 +#define SRST_SPI3 222 +#define SRST_SPI4 223
/* cru_softrst_con14 */ #define SRST_I2S0_8CH 224 @@ -720,8 +722,8 @@ #define SRST_H_CM0S_NOC 3 #define SRST_DBG_CM0S 4 #define SRST_PO_CM0S 5 -#define SRST_P_SPI3 6 -#define SRST_SPI3 7 +#define SRST_P_SPI6 6 +#define SRST_SPI6 7 #define SRST_P_TIMER_0_1 8 #define SRST_P_TIMER_0 9 #define SRST_P_TIMER_1 10
rk3399.dtsi from linux v5.19 and newer try to set VDU clock rate to 400 MHz using an assigned-clock-rates prop of the CRU node.
U-Boot does not use or need this clock so add dummy support for getting and setting ACLK_VDU clock rate to allow CRU driver to be loaded with an updated rk3399.dtsi.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- drivers/clk/rockchip/clk_rk3399.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index f0ce54067f8c..5934771b4096 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -971,6 +971,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR: + case ACLK_VDU: break; case PCLK_ALIVE: case PCLK_WDT: @@ -1061,6 +1062,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR: + case ACLK_VDU: return 0; default: log_debug("Unknown clock %lu\n", clk->id);
On 2024/4/1 04:28, Jonas Karlman wrote:
rk3399.dtsi from linux v5.19 and newer try to set VDU clock rate to 400 MHz using an assigned-clock-rates prop of the CRU node.
U-Boot does not use or need this clock so add dummy support for getting and setting ACLK_VDU clock rate to allow CRU driver to be loaded with an updated rk3399.dtsi.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/clk/rockchip/clk_rk3399.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index f0ce54067f8c..5934771b4096 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -971,6 +971,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR:
- case ACLK_VDU: break; case PCLK_ALIVE: case PCLK_WDT:
@@ -1061,6 +1062,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case ACLK_HDCP: case ACLK_GIC_PRE: case PCLK_DDR:
- case ACLK_VDU: return 0; default: log_debug("Unknown clock %lu\n", clk->id);
rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock.
The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default rate used for this clock.
Add dummy support for setting parent, getting and setting clock rate of the SCLK_PCIEPHY_REF clock to allow use of PCIe on affected boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- drivers/clk/rockchip/clk_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 5934771b4096..29b01abeca06 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -972,6 +972,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_GIC_PRE: case PCLK_DDR: case ACLK_VDU: + case SCLK_PCIEPHY_REF: break; case PCLK_ALIVE: case PCLK_WDT: @@ -1063,6 +1064,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case ACLK_GIC_PRE: case PCLK_DDR: case ACLK_VDU: + case SCLK_PCIEPHY_REF: return 0; default: log_debug("Unknown clock %lu\n", clk->id); @@ -1114,6 +1116,8 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, switch (clk->id) { case SCLK_RMII_SRC: return rk3399_gmac_set_parent(clk, parent); + case SCLK_PCIEPHY_REF: + return 0; }
debug("%s: unsupported clk %ld\n", __func__, clk->id);
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock.
The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default rate used for this clock.
I'm not sure that's true?
If I read the TRM correctly, clk_pciephy_ref_sel can come either from clk_pcie_ref24m (the default) or clk_pcie_ref100m.
enable/disable is actually only ever writing 0 to that bit (bit 10 in CRU_CLKSEL_CON18) and not even enabling the clock.
Assuming clk_pcie_ref24m is the 24MHz base clock (which seems to be the case according to the Linux kernel CRU driver), there shouldn't be a way to disable that clock. However, if clk_pcie_ref100m is selected, one needs to enable/disable it via CRU_CLKGATE_CON12 bit 6 (enabled by default).
set_parent should be properly implemented to handle this parenting and enable/disable fixed to use the proper register.
Cheers, Quentin
Hi Quentin,
On 2024-04-02 16:44, Quentin Schulz wrote:
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock.
The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default rate used for this clock.
I'm not sure that's true?
If I read the TRM correctly, clk_pciephy_ref_sel can come either from clk_pcie_ref24m (the default) or clk_pcie_ref100m.
enable/disable is actually only ever writing 0 to that bit (bit 10 in CRU_CLKSEL_CON18) and not even enabling the clock.
You are correct, I should have looked closer at the code :-)
Assuming clk_pcie_ref24m is the 24MHz base clock (which seems to be the case according to the Linux kernel CRU driver), there shouldn't be a way to disable that clock. However, if clk_pcie_ref100m is selected, one needs to enable/disable it via CRU_CLKGATE_CON12 bit 6 (enabled by default).
set_parent should be properly implemented to handle this parenting and enable/disable fixed to use the proper register.
For v2 I have added improved support for enable/disable, setting parent and rate of the pciephy refclk, it is not a full implementation but should support the state of updated device tree files.
I have not been able to runtime test on a nanopi-4 based board yet, but will include the updated version in v2, it does not seem to affect any of my other boards not setting parent/rate.
Regards, Jonas
Cheers, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock.
The existing enable/disable ops for SCLK_PCIEPHY_REF already handles setting correct parent once the clock gets enabled. And 100 MHz is the default rate used for this clock.
Add dummy support for setting parent, getting and setting clock rate of the SCLK_PCIEPHY_REF clock to allow use of PCIe on affected boards.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/clk/rockchip/clk_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 5934771b4096..29b01abeca06 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -972,6 +972,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case ACLK_GIC_PRE: case PCLK_DDR: case ACLK_VDU:
- case SCLK_PCIEPHY_REF: break; case PCLK_ALIVE: case PCLK_WDT:
@@ -1063,6 +1064,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case ACLK_GIC_PRE: case PCLK_DDR: case ACLK_VDU:
- case SCLK_PCIEPHY_REF: return 0; default: log_debug("Unknown clock %lu\n", clk->id);
@@ -1114,6 +1116,8 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, switch (clk->id) { case SCLK_RMII_SRC: return rk3399_gmac_set_parent(clk, parent);
case SCLK_PCIEPHY_REF:
return 0;}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix reference clock period configuration.
Also replace use of 24000000 with the OSC_HZ constant.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- drivers/clk/rockchip/clk_rk3399.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 29b01abeca06..6408c5d0aa6a 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -956,7 +956,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART1: case SCLK_UART2: case SCLK_UART3: - return 24000000; + case SCLK_USB3OTG0_REF: + case SCLK_USB3OTG1_REF: + return OSC_HZ; case PCLK_HDMI_CTRL: break; case DCLK_VOP0:
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix reference clock period configuration.
Also replace use of 24000000 with the OSC_HZ constant.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Thanks, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
The SCLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of SCLK_USB3OTGx_REF clocks to fix reference clock period configuration.
Also replace use of 24000000 with the OSC_HZ constant.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
drivers/clk/rockchip/clk_rk3399.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 29b01abeca06..6408c5d0aa6a 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -956,7 +956,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) case SCLK_UART1: case SCLK_UART2: case SCLK_UART3:
return 24000000;
- case SCLK_USB3OTG0_REF:
- case SCLK_USB3OTG1_REF:
return OSC_HZ;
Sync RK3399 SoC common .dtsi-files from linux v6.8.
The ethernet0 alias is removed from rk3399.dtsi in this patch, it will be restored in board specific .dts-files. There is no other intended change with this patch.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 - arch/arm/dts/rk3399-u-boot.dtsi | 52 ++-- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- 5 files changed, 308 insertions(+), 74 deletions(-)
diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi index 69cc9b05baa5..783120e9cebe 100644 --- a/arch/arm/dts/rk3399-op1-opp.dtsi +++ b/arch/arm/dts/rk3399-op1-opp.dtsi @@ -4,7 +4,7 @@ */
/ { - cluster0_opp: opp-table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -39,7 +39,7 @@ }; };
- cluster1_opp: opp-table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -82,7 +82,7 @@ }; };
- gpu_opp_table: opp-table2 { + gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 { @@ -110,6 +110,27 @@ opp-microvolt = <1075000>; }; }; + + dmc_opp_table: opp-table-3 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <925000>; + }; + }; };
&cpu_l0 { @@ -136,6 +157,10 @@ operating-points-v2 = <&cluster1_opp>; };
+&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; + &gpu { operating-points-v2 = <&gpu_opp_table>; }; diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi index da41cd81ebb7..fee5e7111279 100644 --- a/arch/arm/dts/rk3399-opp.dtsi +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -4,7 +4,7 @@ */
/ { - cluster0_opp: opp-table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -35,7 +35,7 @@ }; };
- cluster1_opp: opp-table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -74,7 +74,7 @@ }; };
- gpu_opp_table: opp-table2 { + gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 { diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index b8f95b86d86b..dcfcec4f3072 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,10 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-&rng { - status = "okay"; -}; - &sdhci { max-frequency = <25000000>; }; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index adb64d17e040..d2648abd0a44 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -2,8 +2,6 @@ /* * Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com */ -#define USB_CLASS_HUB 9 - #include "rockchip-u-boot.dtsi"
/ { @@ -24,44 +22,11 @@ reg = <0x0 0xff620000 0x0 0x100>; };
- dfi: dfi@ff630000 { - bootph-all; - reg = <0x00 0xff630000 0x00 0x4000>; - compatible = "rockchip,rk3399-dfi"; - rockchip,pmu = <&pmugrf>; - clocks = <&cru PCLK_DDR_MON>; - clock-names = "pclk_ddr_mon"; - }; - - rng: rng@ff8b8000 { - compatible = "rockchip,rk3399-crypto"; - reg = <0x0 0xff8b8000 0x0 0x1000>; - status = "okay"; - }; - - dmc: dmc { - bootph-all; - compatible = "rockchip,rk3399-dmc"; - devfreq-events = <&dfi>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_DDRC>; - clock-names = "dmc_clk"; - reg = <0x0 0xffa80000 0x0 0x0800 - 0x0 0xffa80800 0x0 0x1800 - 0x0 0xffa82000 0x0 0x2000 - 0x0 0xffa84000 0x0 0x1000 - 0x0 0xffa88000 0x0 0x0800 - 0x0 0xffa88800 0x0 0x1800 - 0x0 0xffa8a000 0x0 0x2000 - 0x0 0xffa8c000 0x0 0x1000>; - }; - pmusgrf: syscon@ff330000 { bootph-all; compatible = "rockchip,rk3399-pmusgrf", "syscon"; reg = <0x0 0xff330000 0x0 0xe3d4>; }; - };
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) @@ -93,6 +58,19 @@ bootph-all; };
+&dmc { + bootph-all; + reg = <0x0 0xffa80000 0x0 0x0800 + 0x0 0xffa80800 0x0 0x1800 + 0x0 0xffa82000 0x0 0x2000 + 0x0 0xffa84000 0x0 0x1000 + 0x0 0xffa88000 0x0 0x0800 + 0x0 0xffa88800 0x0 0x1800 + 0x0 0xffa8a000 0x0 0x2000 + 0x0 0xffa8c000 0x0 0x1000>; + status = "okay"; +}; + &emmc_phy { bootph-pre-ram; bootph-some-ram; @@ -196,3 +174,7 @@ &vopl { bootph-some-ram; }; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 3871c7fd83b0..6e12c5a920ca 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -19,7 +19,11 @@ #size-cells = <2>;
aliases { - ethernet0 = &gmac; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -124,6 +128,12 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + + thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; };
cpu_b1: cpu@101 { @@ -136,6 +146,12 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + + thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; };
idle-states { @@ -166,6 +182,15 @@ ports = <&vopl_out>, <&vopb_out>; };
+ dmc: memory-controller { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + status = "disabled"; + }; + pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; @@ -244,6 +269,33 @@ }; };
+ pcie0_ep: pcie-ep@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + reg = <0x0 0xfd000000 0x0 0x1000000>, + <0x0 0xfa000000 0x0 0x2000000>; + reg-names = "apb-base", "mem-base"; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; + rockchip,max-outbound-regions = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + status = "disabled"; + }; + gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; @@ -361,6 +413,54 @@ status = "disabled"; };
+ debug@fe430000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe430000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l0>; + }; + + debug@fe432000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe432000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l1>; + }; + + debug@fe434000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe434000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l2>; + }; + + debug@fe436000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe436000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_L>; + clock-names = "apb_pclk"; + cpu = <&cpu_l3>; + }; + + debug@fe610000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe610000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_B>; + clock-names = "apb_pclk"; + cpu = <&cpu_b0>; + }; + + debug@fe710000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0 0xfe710000 0 0x1000>; + clocks = <&cru PCLK_COREDBG_B>; + clock-names = "apb_pclk"; + cpu = <&cpu_b1>; + }; + usbdrd3_0: usb@fe800000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; @@ -483,7 +583,7 @@ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; - its: interrupt-controller@fee20000 { + its: msi-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; @@ -513,6 +613,26 @@ status = "disabled"; };
+ crypto0: crypto@ff8b0000 { + compatible = "rockchip,rk3399-crypto"; + reg = <0x0 0xff8b0000 0x0 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; + reset-names = "master", "slave", "crypto-rst"; + }; + + crypto1: crypto@ff8b8000 { + compatible = "rockchip,rk3399-crypto"; + reg = <0x0 0xff8b8000 0x0 0x4000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; + reset-names = "master", "slave", "crypto-rst"; + }; + i2c1: i2c@ff110000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>; @@ -993,7 +1113,9 @@ power-domain@RK3399_PD_VDU { reg = <RK3399_PD_VDU>; clocks = <&cru ACLK_VDU>, - <&cru HCLK_VDU>; + <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, + <&cru SCLK_VDU_CORE>; pm_qos = <&qos_video_m1_r>, <&qos_video_m1_w>; #power-domain-cells = <0>; @@ -1235,6 +1357,15 @@ status = "disabled"; };
+ dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + }; + vpu: video-codec@ff650000 { compatible = "rockchip,rk3399-vpu"; reg = <0x0 0xff650000 0x0 0x800>; @@ -1251,7 +1382,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff650800 0x0 0x40>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "vpu_mmu"; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -1260,7 +1390,7 @@
vdec: video-codec@ff660000 { compatible = "rockchip,rk3399-vdec"; - reg = <0x0 0xff660000 0x0 0x400>; + reg = <0x0 0xff660000 0x0 0x480>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; @@ -1273,7 +1403,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "vdec_mmu"; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VDU>; @@ -1284,7 +1413,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff670800 0x0 0x40>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "iep_mmu"; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -1356,9 +1484,11 @@ clock-names = "apb_pclk"; };
- pmucru: pmu-clock-controller@ff750000 { + pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; @@ -1369,6 +1499,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -1382,7 +1514,8 @@ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, <&cru ACLK_VIO>, <&cru ACLK_HDCP>, <&cru ACLK_GIC_PRE>, - <&cru PCLK_DDR>; + <&cru PCLK_DDR>, + <&cru ACLK_VDU>; assigned-clock-rates = <594000000>, <800000000>, <1000000000>, @@ -1393,7 +1526,8 @@ <100000000>, <50000000>, <400000000>, <400000000>, <200000000>, - <200000000>; + <200000000>, + <400000000>; };
grf: syscon@ff770000 { @@ -1477,6 +1611,7 @@ reg = <0xf780 0x24>; clocks = <&sdhci>; clock-names = "emmcclk"; + drive-impedance-ohm = <50>; #phy-cells = <0>; status = "disabled"; }; @@ -1487,7 +1622,6 @@ clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; - drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; @@ -1582,8 +1716,9 @@ dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; - pinctrl-names = "default"; + pinctrl-names = "bclk_on", "bclk_off"; pinctrl-0 = <&i2s0_8ch_bus>; + pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; power-domains = <&power RK3399_PD_SDIOAUDIO>; #sound-dai-cells = <0>; status = "disabled"; @@ -1619,7 +1754,7 @@
vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit"; - reg = <0x0 0xff8f0000 0x0 0x3efc>; + reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; assigned-clock-rates = <400000000>, <100000000>; @@ -1666,7 +1801,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff8f3f00 0x0 0x100>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "vopl_mmu"; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VOPL>; @@ -1676,7 +1810,7 @@
vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big"; - reg = <0x0 0xff900000 0x0 0x3efc>; + reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; assigned-clock-rates = <400000000>, <100000000>; @@ -1723,7 +1857,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff903f00 0x0 0x100>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "vopb_mmu"; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk", "iface"; power-domains = <&power RK3399_PD_VOPB>; @@ -1761,7 +1894,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "isp0_mmu"; clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -1769,11 +1901,36 @@ rockchip,disable-mmu-reset; };
+ isp1: isp1@ff920000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff920000 0x0 0x4000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_ISP1>, + <&cru ACLK_ISP1_WRAPPER>, + <&cru HCLK_ISP1_WRAPPER>; + clock-names = "isp", "aclk", "hclk"; + iommus = <&isp1_mmu>; + phys = <&mipi_dsi1>; + phy-names = "dphy"; + power-domains = <&power RK3399_PD_ISP1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + isp1_mmu: iommu@ff924000 { compatible = "rockchip,iommu"; reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "isp1_mmu"; clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -1802,10 +1959,10 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, - <&cru PLL_VPLL>, + <&cru SCLK_HDMI_CEC>, <&cru PCLK_VIO_GRF>, - <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "vpll", "grf", "cec"; + <&cru PLL_VPLL>; + clock-names = "iahb", "isfr", "cec", "grf", "ref"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; @@ -1829,7 +1986,7 @@ }; };
- mipi_dsi: mipi@ff960000 { + mipi_dsi: dsi@ff960000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1857,15 +2014,20 @@ reg = <0>; remote-endpoint = <&vopb_out_mipi>; }; + mipi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_mipi>; }; }; + + mipi_out: port@1 { + reg = <1>; + }; }; };
- mipi_dsi1: mipi@ff968000 { + mipi_dsi1: dsi@ff968000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff968000 0x0 0x8000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1878,6 +2040,7 @@ rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; + #phy-cells = <0>; status = "disabled";
ports { @@ -1899,10 +2062,14 @@ remote-endpoint = <&vopl_out_mipi1>; }; }; + + mipi1_out: port@1 { + reg = <1>; + }; }; };
- edp: edp@ff970000 { + edp: dp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1919,6 +2086,7 @@ ports { #address-cells = <1>; #size-cells = <0>; + edp_in: port@0 { reg = <0>; #address-cells = <1>; @@ -1934,6 +2102,10 @@ remote-endpoint = <&vopl_out_edp>; }; }; + + edp_out: port@1 { + reg = <1>; + }; }; };
@@ -1946,6 +2118,7 @@ interrupt-names = "job", "mmu", "gpu"; clocks = <&cru ACLK_GPU>; #cooling-cells = <2>; + dynamic-power-coefficient = <2640>; power-domains = <&power RK3399_PD_GPU>; status = "disabled"; }; @@ -1958,7 +2131,7 @@ #size-cells = <2>; ranges;
- gpio0: gpio0@ff720000 { + gpio0: gpio@ff720000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; @@ -1971,7 +2144,7 @@ #interrupt-cells = <0x2>; };
- gpio1: gpio1@ff730000 { + gpio1: gpio@ff730000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; @@ -1984,7 +2157,7 @@ #interrupt-cells = <0x2>; };
- gpio2: gpio2@ff780000 { + gpio2: gpio@ff780000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; @@ -1997,7 +2170,7 @@ #interrupt-cells = <0x2>; };
- gpio3: gpio3@ff788000 { + gpio3: gpio@ff788000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; @@ -2010,7 +2183,7 @@ #interrupt-cells = <0x2>; };
- gpio4: gpio4@ff790000 { + gpio4: gpio@ff790000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; @@ -2108,12 +2281,38 @@ output-low; };
+ pcfg_input_enable: pcfg-input-enable { + input-enable; + }; + + pcfg_input_pull_up: pcfg-input-pull-up { + input-enable; + bias-pull-up; + }; + + pcfg_input_pull_down: pcfg-input-pull-down { + input-enable; + bias-pull-down; + }; + clock { clk_32k: clk-32k { rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; };
+ cif { + cif_clkin: cif-clkin { + rockchip,pins = + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + cif_clkouta: cif-clkouta { + rockchip,pins = + <2 RK_PB3 3 &pcfg_pull_none>; + }; + }; + edp { edp_hpd: edp-hpd { rockchip,pins = @@ -2264,6 +2463,16 @@ <4 RK_PA0 1 &pcfg_pull_none>; };
+ i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off { + rockchip,pins = + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; + i2s0_8ch_bus: i2s0-8ch-bus { rockchip,pins = <3 RK_PD0 1 &pcfg_pull_none>, @@ -2276,6 +2485,19 @@ <3 RK_PD7 1 &pcfg_pull_none>, <4 RK_PA0 1 &pcfg_pull_none>; }; + + i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { + rockchip,pins = + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; };
i2s1 { @@ -2287,6 +2509,15 @@ <4 RK_PA6 1 &pcfg_pull_none>, <4 RK_PA7 1 &pcfg_pull_none>; }; + + i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { + rockchip,pins = + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA4 1 &pcfg_pull_none>, + <4 RK_PA5 1 &pcfg_pull_none>, + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; + }; };
sdio0 {
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
Sync RK3399 SoC common .dtsi-files from linux v6.8.
The ethernet0 alias is removed from rk3399.dtsi in this patch, it will be restored in board specific .dts-files. There is no other intended
Please add ethernet0 alias to rk3399-u-boot.dtsi and remove it in the patch that moves it to board-specific dts files so that this is not a breaking change and we can bisect through this patch if we need to :)
change with this patch.
Could you please mention that rng node is named crypto1 in Linux DT? The diff here was a bit surprising since rng node is entirely removed.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 - arch/arm/dts/rk3399-u-boot.dtsi | 52 ++-- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- 5 files changed, 308 insertions(+), 74 deletions(-)
diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi index 69cc9b05baa5..783120e9cebe 100644 --- a/arch/arm/dts/rk3399-op1-opp.dtsi +++ b/arch/arm/dts/rk3399-op1-opp.dtsi @@ -4,7 +4,7 @@ */
/ {
- cluster0_opp: opp-table0 {
- cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -39,7 +39,7 @@ }; };
- cluster1_opp: opp-table1 {
- cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -82,7 +82,7 @@ }; };
- gpu_opp_table: opp-table2 {
gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 {
@@ -110,6 +110,27 @@ opp-microvolt = <1075000>; }; };
dmc_opp_table: opp-table-3 {
compatible = "operating-points-v2";opp00 {opp-hz = /bits/ 64 <400000000>;opp-microvolt = <900000>;};opp01 {opp-hz = /bits/ 64 <666000000>;opp-microvolt = <900000>;};opp02 {opp-hz = /bits/ 64 <800000000>;opp-microvolt = <900000>;};opp03 {opp-hz = /bits/ 64 <928000000>;opp-microvolt = <925000>;};}; };
&cpu_l0 {
@@ -136,6 +157,10 @@ operating-points-v2 = <&cluster1_opp>; };
+&dmc {
- operating-points-v2 = <&dmc_opp_table>;
+};
- &gpu { operating-points-v2 = <&gpu_opp_table>; };
diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi index da41cd81ebb7..fee5e7111279 100644 --- a/arch/arm/dts/rk3399-opp.dtsi +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -4,7 +4,7 @@ */
/ {
- cluster0_opp: opp-table0 {
- cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -35,7 +35,7 @@ }; };
- cluster1_opp: opp-table1 {
- cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -74,7 +74,7 @@ }; };
- gpu_opp_table: opp-table2 {
gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 {
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index b8f95b86d86b..dcfcec4f3072 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,10 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-&rng {
- status = "okay";
-};
- &sdhci { max-frequency = <25000000>; };
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index adb64d17e040..d2648abd0a44 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -2,8 +2,6 @@ /*
- Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com
*/ -#define USB_CLASS_HUB 9
#include "rockchip-u-boot.dtsi"
/ {
@@ -24,44 +22,11 @@ reg = <0x0 0xff620000 0x0 0x100>; };
- dfi: dfi@ff630000 {
bootph-all;reg = <0x00 0xff630000 0x00 0x4000>;compatible = "rockchip,rk3399-dfi";rockchip,pmu = <&pmugrf>;clocks = <&cru PCLK_DDR_MON>;clock-names = "pclk_ddr_mon";- };
- rng: rng@ff8b8000 {
compatible = "rockchip,rk3399-crypto";reg = <0x0 0xff8b8000 0x0 0x1000>;status = "okay";- };
- dmc: dmc {
bootph-all;compatible = "rockchip,rk3399-dmc";devfreq-events = <&dfi>;interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru SCLK_DDRC>;clock-names = "dmc_clk";reg = <0x0 0xffa80000 0x0 0x08000x0 0xffa80800 0x0 0x18000x0 0xffa82000 0x0 0x20000x0 0xffa84000 0x0 0x10000x0 0xffa88000 0x0 0x08000x0 0xffa88800 0x0 0x18000x0 0xffa8a000 0x0 0x20000x0 0xffa8c000 0x0 0x1000>;- };
- pmusgrf: syscon@ff330000 { bootph-all;
I have my doubts the PMU SGRF is accessible from U-Boot proper if TF-A loads it into normal world. Maybe this should rather be bootph-pre-sram+bootph-pre-ram?
Nothing to fix in this series though.
compatible = "rockchip,rk3399-pmusgrf", "syscon"; reg = <0x0 0xff330000 0x0 0xe3d4>;};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
@@ -93,6 +58,19 @@ bootph-all; };
+&dmc {
- bootph-all;
- reg = <0x0 0xffa80000 0x0 0x0800
0x0 0xffa80800 0x0 0x18000x0 0xffa82000 0x0 0x20000x0 0xffa84000 0x0 0x10000x0 0xffa88000 0x0 0x08000x0 0xffa88800 0x0 0x18000x0 0xffa8a000 0x0 0x20000x0 0xffa8c000 0x0 0x1000>;- status = "okay";
+};
Missing bootph-all for dfi?
[...]
Cheers, Quentin
Hi Quentin,
On 2024-04-02 17:02, Quentin Schulz wrote:
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
Sync RK3399 SoC common .dtsi-files from linux v6.8.
The ethernet0 alias is removed from rk3399.dtsi in this patch, it will be restored in board specific .dts-files. There is no other intended
Please add ethernet0 alias to rk3399-u-boot.dtsi and remove it in the patch that moves it to board-specific dts files so that this is not a breaking change and we can bisect through this patch if we need to :)
Agree, will add ethernet0 alias to rk3399-u-boot.dtsi in v2. And then drop it in a patch after all board files have been updated to v6.8.
change with this patch.
Could you please mention that rng node is named crypto1 in Linux DT? The diff here was a bit surprising since rng node is entirely removed.
Agree, will include a note about it in v2.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 - arch/arm/dts/rk3399-u-boot.dtsi | 52 ++-- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- 5 files changed, 308 insertions(+), 74 deletions(-)
diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi index 69cc9b05baa5..783120e9cebe 100644 --- a/arch/arm/dts/rk3399-op1-opp.dtsi +++ b/arch/arm/dts/rk3399-op1-opp.dtsi @@ -4,7 +4,7 @@ */
/ {
- cluster0_opp: opp-table0 {
- cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -39,7 +39,7 @@ }; };
- cluster1_opp: opp-table1 {
- cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -82,7 +82,7 @@ }; };
- gpu_opp_table: opp-table2 {
gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 {
@@ -110,6 +110,27 @@ opp-microvolt = <1075000>; }; };
dmc_opp_table: opp-table-3 {
compatible = "operating-points-v2";opp00 {opp-hz = /bits/ 64 <400000000>;opp-microvolt = <900000>;};opp01 {opp-hz = /bits/ 64 <666000000>;opp-microvolt = <900000>;};opp02 {opp-hz = /bits/ 64 <800000000>;opp-microvolt = <900000>;};opp03 {opp-hz = /bits/ 64 <928000000>;opp-microvolt = <925000>;};}; };
&cpu_l0 {
@@ -136,6 +157,10 @@ operating-points-v2 = <&cluster1_opp>; };
+&dmc {
- operating-points-v2 = <&dmc_opp_table>;
+};
- &gpu { operating-points-v2 = <&gpu_opp_table>; };
diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi index da41cd81ebb7..fee5e7111279 100644 --- a/arch/arm/dts/rk3399-opp.dtsi +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -4,7 +4,7 @@ */
/ {
- cluster0_opp: opp-table0 {
- cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -35,7 +35,7 @@ }; };
- cluster1_opp: opp-table1 {
- cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -74,7 +74,7 @@ }; };
- gpu_opp_table: opp-table2 {
gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 {
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index b8f95b86d86b..dcfcec4f3072 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,10 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-&rng {
- status = "okay";
-};
- &sdhci { max-frequency = <25000000>; };
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index adb64d17e040..d2648abd0a44 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -2,8 +2,6 @@ /*
- Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com
*/ -#define USB_CLASS_HUB 9
#include "rockchip-u-boot.dtsi"
/ {
@@ -24,44 +22,11 @@ reg = <0x0 0xff620000 0x0 0x100>; };
- dfi: dfi@ff630000 {
bootph-all;reg = <0x00 0xff630000 0x00 0x4000>;compatible = "rockchip,rk3399-dfi";rockchip,pmu = <&pmugrf>;clocks = <&cru PCLK_DDR_MON>;clock-names = "pclk_ddr_mon";- };
- rng: rng@ff8b8000 {
compatible = "rockchip,rk3399-crypto";reg = <0x0 0xff8b8000 0x0 0x1000>;status = "okay";- };
- dmc: dmc {
bootph-all;compatible = "rockchip,rk3399-dmc";devfreq-events = <&dfi>;interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru SCLK_DDRC>;clock-names = "dmc_clk";reg = <0x0 0xffa80000 0x0 0x08000x0 0xffa80800 0x0 0x18000x0 0xffa82000 0x0 0x20000x0 0xffa84000 0x0 0x10000x0 0xffa88000 0x0 0x08000x0 0xffa88800 0x0 0x18000x0 0xffa8a000 0x0 0x20000x0 0xffa8c000 0x0 0x1000>;- };
- pmusgrf: syscon@ff330000 { bootph-all;
I have my doubts the PMU SGRF is accessible from U-Boot proper if TF-A loads it into normal world. Maybe this should rather be bootph-pre-sram+bootph-pre-ram?
That is probably true, and as you mention below, nothing I will address in this series :-)
Nothing to fix in this series though.
compatible = "rockchip,rk3399-pmusgrf", "syscon"; reg = <0x0 0xff330000 0x0 0xe3d4>;};
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
@@ -93,6 +58,19 @@ bootph-all; };
+&dmc {
- bootph-all;
- reg = <0x0 0xffa80000 0x0 0x0800
0x0 0xffa80800 0x0 0x18000x0 0xffa82000 0x0 0x20000x0 0xffa84000 0x0 0x10000x0 0xffa88000 0x0 0x08000x0 0xffa88800 0x0 0x18000x0 0xffa8a000 0x0 0x20000x0 0xffa8c000 0x0 0x1000>;- status = "okay";
+};
Missing bootph-all for dfi?
Thanks, will restore/include in v2.
I do not think the dfi node is really required at TPL/SPL phase, but lets care about boot/size optimization in a future series :-)
Regards, Jonas
[...]
Cheers, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync RK3399 SoC common .dtsi-files from linux v6.8.
The ethernet0 alias is removed from rk3399.dtsi in this patch, it will be restored in board specific .dts-files. There is no other intended change with this patch.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 4 - arch/arm/dts/rk3399-u-boot.dtsi | 52 ++-- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- 5 files changed, 308 insertions(+), 74 deletions(-)
diff --git a/arch/arm/dts/rk3399-op1-opp.dtsi b/arch/arm/dts/rk3399-op1-opp.dtsi index 69cc9b05baa5..783120e9cebe 100644 --- a/arch/arm/dts/rk3399-op1-opp.dtsi +++ b/arch/arm/dts/rk3399-op1-opp.dtsi @@ -4,7 +4,7 @@ */
/ {
- cluster0_opp: opp-table0 {
- cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -39,7 +39,7 @@ }; };
- cluster1_opp: opp-table1 {
- cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -82,7 +82,7 @@ }; };
- gpu_opp_table: opp-table2 {
gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 {
@@ -110,6 +110,27 @@ opp-microvolt = <1075000>; }; };
dmc_opp_table: opp-table-3 {
compatible = "operating-points-v2";opp00 {opp-hz = /bits/ 64 <400000000>;opp-microvolt = <900000>;};opp01 {opp-hz = /bits/ 64 <666000000>;opp-microvolt = <900000>;};opp02 {opp-hz = /bits/ 64 <800000000>;opp-microvolt = <900000>;};opp03 {opp-hz = /bits/ 64 <928000000>;opp-microvolt = <925000>;};}; };
&cpu_l0 {
@@ -136,6 +157,10 @@ operating-points-v2 = <&cluster1_opp>; };
+&dmc {
- operating-points-v2 = <&dmc_opp_table>;
+};
- &gpu { operating-points-v2 = <&gpu_opp_table>; };
diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi index da41cd81ebb7..fee5e7111279 100644 --- a/arch/arm/dts/rk3399-opp.dtsi +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -4,7 +4,7 @@ */
/ {
- cluster0_opp: opp-table0 {
- cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared;
@@ -35,7 +35,7 @@ }; };
- cluster1_opp: opp-table1 {
- cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared;
@@ -74,7 +74,7 @@ }; };
- gpu_opp_table: opp-table2 {
gpu_opp_table: opp-table-2 { compatible = "operating-points-v2";
opp00 {
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index b8f95b86d86b..dcfcec4f3072 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -6,10 +6,6 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
-&rng {
- status = "okay";
-};
- &sdhci { max-frequency = <25000000>; };
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index adb64d17e040..d2648abd0a44 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -2,8 +2,6 @@ /*
- Copyright (C) 2019 Jagan Teki jagan@amarulasolutions.com
*/ -#define USB_CLASS_HUB 9
#include "rockchip-u-boot.dtsi"
/ {
@@ -24,44 +22,11 @@ reg = <0x0 0xff620000 0x0 0x100>; };
dfi: dfi@ff630000 {
bootph-all;reg = <0x00 0xff630000 0x00 0x4000>;compatible = "rockchip,rk3399-dfi";rockchip,pmu = <&pmugrf>;clocks = <&cru PCLK_DDR_MON>;clock-names = "pclk_ddr_mon";};
rng: rng@ff8b8000 {
compatible = "rockchip,rk3399-crypto";reg = <0x0 0xff8b8000 0x0 0x1000>;status = "okay";};
dmc: dmc {
bootph-all;compatible = "rockchip,rk3399-dmc";devfreq-events = <&dfi>;interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru SCLK_DDRC>;clock-names = "dmc_clk";reg = <0x0 0xffa80000 0x0 0x08000x0 0xffa80800 0x0 0x18000x0 0xffa82000 0x0 0x20000x0 0xffa84000 0x0 0x10000x0 0xffa88000 0x0 0x08000x0 0xffa88800 0x0 0x18000x0 0xffa8a000 0x0 0x20000x0 0xffa8c000 0x0 0x1000>;};
pmusgrf: syscon@ff330000 { bootph-all; compatible = "rockchip,rk3399-pmusgrf", "syscon"; reg = <0x0 0xff330000 0x0 0xe3d4>; };
};
#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
@@ -93,6 +58,19 @@ bootph-all; };
+&dmc {
- bootph-all;
- reg = <0x0 0xffa80000 0x0 0x0800
0x0 0xffa80800 0x0 0x18000x0 0xffa82000 0x0 0x20000x0 0xffa84000 0x0 0x10000x0 0xffa88000 0x0 0x08000x0 0xffa88800 0x0 0x18000x0 0xffa8a000 0x0 0x20000x0 0xffa8c000 0x0 0x1000>;- status = "okay";
+};
- &emmc_phy { bootph-pre-ram; bootph-some-ram;
@@ -196,3 +174,7 @@ &vopl { bootph-some-ram; };
+&xin24m {
- bootph-all;
+}; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 3871c7fd83b0..6e12c5a920ca 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -19,7 +19,11 @@ #size-cells = <2>;
aliases {
ethernet0 = &gmac;
gpio0 = &gpio0;gpio1 = &gpio1;gpio2 = &gpio2;gpio3 = &gpio3;gpio4 = &gpio4;@@ -124,6 +128,12 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
thermal-idle {#cooling-cells = <2>;duration-us = <10000>;exit-latency-us = <500>;};};
cpu_b1: cpu@101 {
@@ -136,6 +146,12 @@ #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
thermal-idle {#cooling-cells = <2>;duration-us = <10000>;exit-latency-us = <500>;};};
idle-states {
@@ -166,6 +182,15 @@ ports = <&vopl_out>, <&vopb_out>; };
- dmc: memory-controller {
compatible = "rockchip,rk3399-dmc";rockchip,pmu = <&pmugrf>;devfreq-events = <&dfi>;clocks = <&cru SCLK_DDRC>;clock-names = "dmc_clk";status = "disabled";- };
- pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -244,6 +269,33 @@ }; };
- pcie0_ep: pcie-ep@f8000000 {
compatible = "rockchip,rk3399-pcie-ep";reg = <0x0 0xfd000000 0x0 0x1000000>,<0x0 0xfa000000 0x0 0x2000000>;reg-names = "apb-base", "mem-base";clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;clock-names = "aclk", "aclk-perf","hclk", "pm";max-functions = /bits/ 8 <8>;num-lanes = <4>;resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,<&cru SRST_A_PCIE>;reset-names = "core", "mgmt", "mgmt-sticky", "pipe","pm", "pclk", "aclk";phys = <&pcie_phy 0>, <&pcie_phy 1>,<&pcie_phy 2>, <&pcie_phy 3>;phy-names = "pcie-phy-0", "pcie-phy-1","pcie-phy-2", "pcie-phy-3";rockchip,max-outbound-regions = <32>;pinctrl-names = "default";pinctrl-0 = <&pcie_clkreqnb_cpm>;status = "disabled";- };
- gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>;
@@ -361,6 +413,54 @@ status = "disabled"; };
- debug@fe430000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";reg = <0 0xfe430000 0 0x1000>;clocks = <&cru PCLK_COREDBG_L>;clock-names = "apb_pclk";cpu = <&cpu_l0>;- };
- debug@fe432000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";reg = <0 0xfe432000 0 0x1000>;clocks = <&cru PCLK_COREDBG_L>;clock-names = "apb_pclk";cpu = <&cpu_l1>;- };
- debug@fe434000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";reg = <0 0xfe434000 0 0x1000>;clocks = <&cru PCLK_COREDBG_L>;clock-names = "apb_pclk";cpu = <&cpu_l2>;- };
- debug@fe436000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";reg = <0 0xfe436000 0 0x1000>;clocks = <&cru PCLK_COREDBG_L>;clock-names = "apb_pclk";cpu = <&cpu_l3>;- };
- debug@fe610000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";reg = <0 0xfe610000 0 0x1000>;clocks = <&cru PCLK_COREDBG_B>;clock-names = "apb_pclk";cpu = <&cpu_b0>;- };
- debug@fe710000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";reg = <0 0xfe710000 0 0x1000>;clocks = <&cru PCLK_COREDBG_B>;clock-names = "apb_pclk";cpu = <&cpu_b1>;- };
- usbdrd3_0: usb@fe800000 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>;
@@ -483,7 +583,7 @@ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
its: interrupt-controller@fee20000 {
its: msi-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>;@@ -513,6 +613,26 @@ status = "disabled"; };
- crypto0: crypto@ff8b0000 {
compatible = "rockchip,rk3399-crypto";reg = <0x0 0xff8b0000 0x0 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;clock-names = "hclk_master", "hclk_slave", "sclk";resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;reset-names = "master", "slave", "crypto-rst";- };
- crypto1: crypto@ff8b8000 {
compatible = "rockchip,rk3399-crypto";reg = <0x0 0xff8b8000 0x0 0x4000>;interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;clock-names = "hclk_master", "hclk_slave", "sclk";resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;reset-names = "master", "slave", "crypto-rst";- };
- i2c1: i2c@ff110000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>;
@@ -993,7 +1113,9 @@ power-domain@RK3399_PD_VDU { reg = <RK3399_PD_VDU>; clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
<&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>; pm_qos = <&qos_video_m1_r>, <&qos_video_m1_w>; #power-domain-cells = <0>;@@ -1235,6 +1357,15 @@ status = "disabled"; };
- dfi: dfi@ff630000 {
reg = <0x00 0xff630000 0x00 0x4000>;compatible = "rockchip,rk3399-dfi";rockchip,pmu = <&pmugrf>;interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru PCLK_DDR_MON>;clock-names = "pclk_ddr_mon";- };
- vpu: video-codec@ff650000 { compatible = "rockchip,rk3399-vpu"; reg = <0x0 0xff650000 0x0 0x800>;
@@ -1251,7 +1382,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff650800 0x0 0x40>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vpu_mmu";@@ -1260,7 +1390,7 @@
vdec: video-codec@ff660000 { compatible = "rockchip,rk3399-vdec";
reg = <0x0 0xff660000 0x0 0x400>;
reg = <0x0 0xff660000 0x0 0x480>;@@ -1273,7 +1403,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vdec_mmu";@@ -1284,7 +1413,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff670800 0x0 0x40>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "iep_mmu";@@ -1356,9 +1484,11 @@ clock-names = "apb_pclk"; };
- pmucru: pmu-clock-controller@ff750000 {
- pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>;
clocks = <&xin24m>;clock-names = "xin24m";@@ -1369,6 +1499,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>;
clocks = <&xin24m>;clock-names = "xin24m";@@ -1382,7 +1514,8 @@ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, <&cru ACLK_VIO>, <&cru ACLK_HDCP>, <&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>;
<&cru PCLK_DDR>,<&cru ACLK_VDU>;@@ -1393,7 +1526,8 @@ <100000000>, <50000000>, <400000000>, <400000000>, <200000000>,
<200000000>;
<200000000>,<400000000>;};
grf: syscon@ff770000 {
@@ -1477,6 +1611,7 @@ reg = <0xf780 0x24>; clocks = <&sdhci>; clock-names = "emmcclk";
drive-impedance-ohm = <50>; #phy-cells = <0>; status = "disabled";@@ -1487,7 +1622,6 @@ clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>;
drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled";@@ -1582,8 +1716,9 @@ dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
pinctrl-names = "default";
pinctrl-names = "bclk_on", "bclk_off";pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;@@ -1619,7 +1754,7 @@
vopl: vop@ff8f0000 { compatible = "rockchip,rk3399-vop-lit";
reg = <0x0 0xff8f0000 0x0 0x3efc>;
reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;@@ -1666,7 +1801,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff8f3f00 0x0 0x100>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";@@ -1676,7 +1810,7 @@
vopb: vop@ff900000 { compatible = "rockchip,rk3399-vop-big";
reg = <0x0 0xff900000 0x0 0x3efc>;
reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;@@ -1723,7 +1857,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff903f00 0x0 0x100>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopb_mmu";@@ -1761,7 +1894,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";@@ -1769,11 +1901,36 @@ rockchip,disable-mmu-reset; };
- isp1: isp1@ff920000 {
compatible = "rockchip,rk3399-cif-isp";reg = <0x0 0xff920000 0x0 0x4000>;interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru SCLK_ISP1>,<&cru ACLK_ISP1_WRAPPER>,<&cru HCLK_ISP1_WRAPPER>;clock-names = "isp", "aclk", "hclk";iommus = <&isp1_mmu>;phys = <&mipi_dsi1>;phy-names = "dphy";power-domains = <&power RK3399_PD_ISP1>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;#address-cells = <1>;#size-cells = <0>;};};- };
- isp1_mmu: iommu@ff924000 { compatible = "rockchip,iommu"; reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";@@ -1802,10 +1959,10 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>,
<&cru PLL_VPLL>,
<&cru SCLK_HDMI_CEC>, <&cru PCLK_VIO_GRF>,
<&cru SCLK_HDMI_CEC>;clock-names = "iahb", "isfr", "vpll", "grf", "cec";
<&cru PLL_VPLL>;clock-names = "iahb", "isfr", "cec", "grf", "ref";@@ -1829,7 +1986,7 @@ }; };
- mipi_dsi: mipi@ff960000 {
- mipi_dsi: dsi@ff960000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -1857,15 +2014,20 @@ reg = <0>; remote-endpoint = <&vopb_out_mipi>; };
mipi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_mipi>; }; };mipi_out: port@1 {reg = <1>;};
- mipi_dsi1: mipi@ff968000 {
- mipi_dsi1: dsi@ff968000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff968000 0x0 0x8000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -1878,6 +2040,7 @@ rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>;
#phy-cells = <0>;status = "disabled";
ports {
@@ -1899,10 +2062,14 @@ remote-endpoint = <&vopl_out_mipi1>; }; };
mipi1_out: port@1 {reg = <1>;};
- edp: edp@ff970000 {
- edp: dp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -1919,6 +2086,7 @@ ports { #address-cells = <1>; #size-cells = <0>;
edp_in: port@0 { reg = <0>; #address-cells = <1>;@@ -1934,6 +2102,10 @@ remote-endpoint = <&vopl_out_edp>; }; };
edp_out: port@1 {reg = <1>;};@@ -1946,6 +2118,7 @@ interrupt-names = "job", "mmu", "gpu"; clocks = <&cru ACLK_GPU>; #cooling-cells = <2>;
dynamic-power-coefficient = <2640>;@@ -1958,7 +2131,7 @@ #size-cells = <2>; ranges;
gpio0: gpio0@ff720000 {
gpio0: gpio@ff720000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>;@@ -1971,7 +2144,7 @@ #interrupt-cells = <0x2>; };
gpio1: gpio1@ff730000 {
gpio1: gpio@ff730000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>;@@ -1984,7 +2157,7 @@ #interrupt-cells = <0x2>; };
gpio2: gpio2@ff780000 {
gpio2: gpio@ff780000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>;@@ -1997,7 +2170,7 @@ #interrupt-cells = <0x2>; };
gpio3: gpio3@ff788000 {
gpio3: gpio@ff788000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>;@@ -2010,7 +2183,7 @@ #interrupt-cells = <0x2>; };
gpio4: gpio4@ff790000 {
gpio4: gpio@ff790000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>;@@ -2108,12 +2281,38 @@ output-low; };
pcfg_input_enable: pcfg-input-enable {input-enable;};pcfg_input_pull_up: pcfg-input-pull-up {input-enable;bias-pull-up;};pcfg_input_pull_down: pcfg-input-pull-down {input-enable;bias-pull-down;};clock { clk_32k: clk-32k { rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; };
cif {cif_clkin: cif-clkin {rockchip,pins =<2 RK_PB2 3 &pcfg_pull_none>;};cif_clkouta: cif-clkouta {rockchip,pins =<2 RK_PB3 3 &pcfg_pull_none>;};};edp { edp_hpd: edp-hpd { rockchip,pins =
@@ -2264,6 +2463,16 @@ <4 RK_PA0 1 &pcfg_pull_none>; };
i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {rockchip,pins =<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,<3 RK_PD1 1 &pcfg_pull_none>,<3 RK_PD2 1 &pcfg_pull_none>,<3 RK_PD3 1 &pcfg_pull_none>,<3 RK_PD7 1 &pcfg_pull_none>,<4 RK_PA0 1 &pcfg_pull_none>;};i2s0_8ch_bus: i2s0-8ch-bus { rockchip,pins = <3 RK_PD0 1 &pcfg_pull_none>,@@ -2276,6 +2485,19 @@ <3 RK_PD7 1 &pcfg_pull_none>, <4 RK_PA0 1 &pcfg_pull_none>; };
i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {rockchip,pins =<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,<3 RK_PD1 1 &pcfg_pull_none>,<3 RK_PD2 1 &pcfg_pull_none>,<3 RK_PD3 1 &pcfg_pull_none>,<3 RK_PD4 1 &pcfg_pull_none>,<3 RK_PD5 1 &pcfg_pull_none>,<3 RK_PD6 1 &pcfg_pull_none>,<3 RK_PD7 1 &pcfg_pull_none>,<4 RK_PA0 1 &pcfg_pull_none>;};};
i2s1 {
@@ -2287,6 +2509,15 @@ <4 RK_PA6 1 &pcfg_pull_none>, <4 RK_PA7 1 &pcfg_pull_none>; };
i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {rockchip,pins =<4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,<4 RK_PA4 1 &pcfg_pull_none>,<4 RK_PA5 1 &pcfg_pull_none>,<4 RK_PA6 1 &pcfg_pull_none>,<4 RK_PA7 1 &pcfg_pull_none>;};};
sdio0 {
Sync rk3399-gru related device tree from linux v6.8.
The spi_flash symbol is no longer part of upstream DT, it is re-defined to allow exising use in related u-boot.dtsi-files.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++++++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-gru.dtsi | 52 +++++- 5 files changed, 254 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts index e6c1c94c8d69..1cba1d857c96 100644 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -16,6 +16,7 @@ "google,bob-rev7", "google,bob-rev6", "google,bob-rev5", "google,bob-rev4", "google,bob", "google,gru", "rockchip,rk3399"; + chassis-type = "convertible";
edp_panel: edp-panel { compatible = "boe,nv101wxmn51"; @@ -69,7 +70,7 @@ &spi0 { status = "okay";
- cr50@0 { + tpm@0 { compatible = "google,cr50"; reg = <0>; interrupt-parent = <&gpio0>; @@ -87,3 +88,8 @@ }; }; }; + +&wlan_host_wake_l { + /* Kevin has an external pull up, but Bob does not. */ + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +}; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi index 1384dabbdf40..cacbad35cfc8 100644 --- a/arch/arm/dts/rk3399-gru-chromebook.dtsi +++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi @@ -198,7 +198,6 @@ power-supply = <&pp3300_disp>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; - pwm-delay-us = <10000>; };
gpio_keys: gpio-keys { @@ -206,7 +205,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>;
- wake_on_bt: wake-on-bt { + wake_on_bt: key-wake-on-bt { label = "Wake-on-Bluetooth"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; @@ -234,9 +233,24 @@ extcon = <&usbc_extcon0>, <&usbc_extcon1>; };
+&dmc { + center-supply = <&ppvar_centerlogic>; + rockchip,pd-idle-dis-freq-hz = <800000000>; + rockchip,sr-idle-dis-freq-hz = <800000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz = <800000000>; +}; + &edp { status = "okay";
+ /* + * eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only + * set this here, because rk3399-gru.dtsi ensures we can generate this + * off GPLL=600MHz, whereas some other RK3399 boards may not. + */ + assigned-clocks = <&cru PCLK_EDP>; + assigned-clock-rates = <24000000>; + ports { edp_out: port@1 { reg = <1>; @@ -251,6 +265,182 @@ }; };
+&gpio0 { + gpio-line-names = /* GPIO0 A 0-7 */ + "AP_RTC_CLK_IN", + "EC_AP_INT_L", + "PP1800_AUDIO_EN", + "BT_HOST_WAKE_L", + "WLAN_MODULE_PD_L", + "H1_INT_OD_L", + "CENTERLOGIC_DVS_PWM", + "", + + /* GPIO0 B 0-4 */ + "WIFI_HOST_WAKE_L", + "PMUIO2_33_18_L", + "PP1500_EN", + "AP_EC_WARM_RESET_REQ", + "PP3000_EN"; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A 0-7 */ + "", + "", + "SPK_PA_EN", + "", + "TRACKPAD_INT_L", + "AP_EC_S3_S0_L", + "AP_EC_OVERTEMP", + "AP_SPI_FLASH_MISO", + + /* GPIO1 B 0-7 */ + "AP_SPI_FLASH_MOSI_R", + "AP_SPI_FLASH_CLK_R", + "AP_SPI_FLASH_CS_L_R", + "WLAN_MODULE_RESET_L", + "WIFI_DISABLE_L", + "MIC_INT", + "", + "AP_I2C_DVS_SDA", + + /* GPIO1 C 0-7 */ + "AP_I2C_DVS_SCL", + "AP_BL_EN", + /* + * AP_FLASH_WP is crossystem ABI. Schematics call it + * AP_FW_WP or CPU1_FW_WP, depending on the variant. + */ + "AP_FLASH_WP", + "LITCPU_DVS_PWM", + "AP_I2C_AUDIO_SDA", + "AP_I2C_AUDIO_SCL", + "", + "HEADSET_INT_L"; +}; + +&gpio2 { + gpio-line-names = /* GPIO2 A 0-7 */ + "", + "", + "SD_IO_PWR_EN", + "", + "", + "", + "", + "", + + /* GPIO2 B 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO2 C 0-7 */ + "", + "", + "", + "", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + + /* GPIO2 D 0-4 */ + "BT_DEV_WAKE_L", + "", + "WIFI_PCIE_CLKREQ_L", + "WIFI_PERST_L", + "SD_PWR_3000_1800_L"; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A 0-7 */ + "", + "", + "", + "", + "AP_SPI_TPM_MISO", + "AP_SPI_TPM_MOSI_R", + "AP_SPI_TPM_CLK_R", + "AP_SPI_TPM_CS_L_R", + + /* GPIO3 B 0-7 */ + "EC_IN_RW", + "", + "AP_I2C_TP_SDA", + "AP_I2C_TP_SCL", + "AP_I2C_TP_PU_EN", + "TOUCH_INT_L", + "", + "", + + /* GPIO3 C 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO3 D 0-7 */ + "I2S0_SCLK", + "I2S0_LRCK_RX", + "I2S0_LRCK_TX", + "I2S0_SDI_0", + "I2S0_SDI_1", + "", + "I2S0_SDO_1", + "I2S0_SDO_0"; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A 0-7 */ + "I2S_MCLK", + "AP_I2C_MIC_SDA", + "AP_I2C_MIC_SCL", + "", + "", + "", + "", + "", + + /* GPIO4 B 0-7 */ + "", + "", + "", + "", + "", + "", + "", + "", + + /* GPIO4 C 0-7 */ + "AP_I2C_TS_SDA", + "AP_I2C_TS_SCL", + "GPU_DVS_PWM", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "", + "BIGCPU_DVS_PWM", + "EDP_HPD_3V0", + + /* GPIO4 D 0-5 */ + "SD_CARD_DET_L", + "USB_DP_HPD", + "TOUCH_RESET_L", + "PP3300_DISP_EN", + "", + "SD_SLOT_PWR_EN"; +}; + ap_i2c_mic: &i2c1 { status = "okay";
@@ -286,7 +476,7 @@ ap_i2c_tp: &i2c5 { };
&cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; @@ -319,8 +509,7 @@ ap_i2c_tp: &i2c5 { &pci_rootport { mvl_wifi: wifi@0,0 { compatible = "pci1b4b,2b42"; - reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 - 0x83010000 0x0 0x00100000 0x0 0x00100000>; + reg = <0x0000 0x0 0x0 0x0 0x0>; interrupt-parent = <&gpio0>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; @@ -395,6 +584,7 @@ ap_i2c_tp: &i2c5 { };
wlan_host_wake_l: wlan-host-wake-l { + /* Kevin has an external pull up, but Bob does not */ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts index 2bbef9fcbe27..2cc9b3386c16 100644 --- a/arch/arm/dts/rk3399-gru-kevin.dts +++ b/arch/arm/dts/rk3399-gru-kevin.dts @@ -24,6 +24,7 @@ "google,kevin-rev9", "google,kevin-rev8", "google,kevin-rev7", "google,kevin-rev6", "google,kevin", "google,gru", "rockchip,rk3399"; + chassis-type = "convertible";
/* Power tree */
@@ -91,7 +92,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
- pen-insert { + switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 0cc40eb6d6f6..6bdc892bd913 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -78,12 +78,14 @@ /delete-property/ bootph-pre-ram; };
+&spi1 { + spi_flash: flash@0 { + bootph-all; + }; +}; + &spi5 { spi-activate-delay = <100>; spi-max-frequency = <3000000>; spi-deactivate-delay = <200>; }; - -&spi_flash { - bootph-all; -}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index b80f19066b57..d90fe4d40d48 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -250,7 +250,7 @@ pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
enable-active-high; - enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; states = <1800000 0x1>, <3000000 0x0>; @@ -286,7 +286,7 @@
sound: sound { compatible = "rockchip,rk3399-gru-sound"; - rockchip,cpu = <&i2s0 &i2s2>; + rockchip,cpu = <&i2s0 &spdif>; }; };
@@ -373,6 +373,34 @@ <200000000>; };
+&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + + rockchip,pd-idle-ns = <160>; + rockchip,sr-idle-ns = <10240>; + rockchip,sr-mc-gate-idle-ns = <40960>; + rockchip,srpd-lite-idle-ns = <61440>; + rockchip,standby-idle-ns = <81920>; + + rockchip,ddr3_odt_dis_freq = <666000000>; + rockchip,lpddr3_odt_dis_freq = <666000000>; + rockchip,lpddr4_odt_dis_freq = <666000000>; + + rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz = <0>; + rockchip,standby-idle-dis-freq-hz = <928000000>; +}; + +&dmc_opp_table { + opp03 { + opp-suspend; + }; +}; + &emmc_phy { status = "okay"; }; @@ -437,10 +465,6 @@ ap_i2c_audio: &i2c8 { status = "okay"; };
-&i2s2 { - status = "okay"; -}; - &io_domains { status = "okay";
@@ -461,10 +485,11 @@ ap_i2c_audio: &i2c8 { vpcie0v9-supply = <&pp900_pcie>;
pci_rootport: pcie@0,0 { - reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; + reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; + device_type = "pci"; }; };
@@ -537,13 +562,24 @@ ap_i2c_audio: &i2c8 { vqmmc-supply = <&ppvar_sd_card_io>; };
+&spdif { + status = "okay"; + + /* + * SPDIF is routed internally to DP; we either don't use these pins, or + * mux them to something else. + */ + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + &spi1 { status = "okay";
pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>;
- spi_flash: spiflash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>;
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-gru related device tree from linux v6.8.
The spi_flash symbol is no longer part of upstream DT, it is re-defined to allow exising use in related u-boot.dtsi-files.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++++++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-gru.dtsi | 52 +++++- 5 files changed, 254 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts index e6c1c94c8d69..1cba1d857c96 100644 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -16,6 +16,7 @@ "google,bob-rev7", "google,bob-rev6", "google,bob-rev5", "google,bob-rev4", "google,bob", "google,gru", "rockchip,rk3399";
chassis-type = "convertible";
edp_panel: edp-panel { compatible = "boe,nv101wxmn51";
@@ -69,7 +70,7 @@ &spi0 { status = "okay";
- cr50@0 {
- tpm@0 { compatible = "google,cr50"; reg = <0>; interrupt-parent = <&gpio0>;
@@ -87,3 +88,8 @@ }; }; };
+&wlan_host_wake_l {
- /* Kevin has an external pull up, but Bob does not. */
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+}; diff --git a/arch/arm/dts/rk3399-gru-chromebook.dtsi b/arch/arm/dts/rk3399-gru-chromebook.dtsi index 1384dabbdf40..cacbad35cfc8 100644 --- a/arch/arm/dts/rk3399-gru-chromebook.dtsi +++ b/arch/arm/dts/rk3399-gru-chromebook.dtsi @@ -198,7 +198,6 @@ power-supply = <&pp3300_disp>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>;
pwm-delay-us = <10000>;};
gpio_keys: gpio-keys {
@@ -206,7 +205,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>;
wake_on_bt: wake-on-bt {
wake_on_bt: key-wake-on-bt { label = "Wake-on-Bluetooth"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>;@@ -234,9 +233,24 @@ extcon = <&usbc_extcon0>, <&usbc_extcon1>; };
+&dmc {
- center-supply = <&ppvar_centerlogic>;
- rockchip,pd-idle-dis-freq-hz = <800000000>;
- rockchip,sr-idle-dis-freq-hz = <800000000>;
- rockchip,sr-mc-gate-idle-dis-freq-hz = <800000000>;
+};
&edp { status = "okay";
/*
* eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only* set this here, because rk3399-gru.dtsi ensures we can generate this* off GPLL=600MHz, whereas some other RK3399 boards may not.*/assigned-clocks = <&cru PCLK_EDP>;
assigned-clock-rates = <24000000>;
ports { edp_out: port@1 { reg = <1>;
@@ -251,6 +265,182 @@ }; };
+&gpio0 {
- gpio-line-names = /* GPIO0 A 0-7 */
"AP_RTC_CLK_IN","EC_AP_INT_L","PP1800_AUDIO_EN","BT_HOST_WAKE_L","WLAN_MODULE_PD_L","H1_INT_OD_L","CENTERLOGIC_DVS_PWM","",/* GPIO0 B 0-4 */"WIFI_HOST_WAKE_L","PMUIO2_33_18_L","PP1500_EN","AP_EC_WARM_RESET_REQ","PP3000_EN";+};
+&gpio1 {
- gpio-line-names = /* GPIO1 A 0-7 */
"","","SPK_PA_EN","","TRACKPAD_INT_L","AP_EC_S3_S0_L","AP_EC_OVERTEMP","AP_SPI_FLASH_MISO",/* GPIO1 B 0-7 */"AP_SPI_FLASH_MOSI_R","AP_SPI_FLASH_CLK_R","AP_SPI_FLASH_CS_L_R","WLAN_MODULE_RESET_L","WIFI_DISABLE_L","MIC_INT","","AP_I2C_DVS_SDA",/* GPIO1 C 0-7 */"AP_I2C_DVS_SCL","AP_BL_EN",/** AP_FLASH_WP is crossystem ABI. Schematics call it* AP_FW_WP or CPU1_FW_WP, depending on the variant.*/"AP_FLASH_WP","LITCPU_DVS_PWM","AP_I2C_AUDIO_SDA","AP_I2C_AUDIO_SCL","","HEADSET_INT_L";+};
+&gpio2 {
- gpio-line-names = /* GPIO2 A 0-7 */
"","","SD_IO_PWR_EN","","","","","",/* GPIO2 B 0-7 */"","","","","","","","",/* GPIO2 C 0-7 */"","","","","AP_SPI_EC_MISO","AP_SPI_EC_MOSI","AP_SPI_EC_CLK","AP_SPI_EC_CS_L",/* GPIO2 D 0-4 */"BT_DEV_WAKE_L","","WIFI_PCIE_CLKREQ_L","WIFI_PERST_L","SD_PWR_3000_1800_L";+};
+&gpio3 {
- gpio-line-names = /* GPIO3 A 0-7 */
"","","","","AP_SPI_TPM_MISO","AP_SPI_TPM_MOSI_R","AP_SPI_TPM_CLK_R","AP_SPI_TPM_CS_L_R",/* GPIO3 B 0-7 */"EC_IN_RW","","AP_I2C_TP_SDA","AP_I2C_TP_SCL","AP_I2C_TP_PU_EN","TOUCH_INT_L","","",/* GPIO3 C 0-7 */"","","","","","","","",/* GPIO3 D 0-7 */"I2S0_SCLK","I2S0_LRCK_RX","I2S0_LRCK_TX","I2S0_SDI_0","I2S0_SDI_1","","I2S0_SDO_1","I2S0_SDO_0";+};
+&gpio4 {
- gpio-line-names = /* GPIO4 A 0-7 */
"I2S_MCLK","AP_I2C_MIC_SDA","AP_I2C_MIC_SCL","","","","","",/* GPIO4 B 0-7 */"","","","","","","","",/* GPIO4 C 0-7 */"AP_I2C_TS_SDA","AP_I2C_TS_SCL","GPU_DVS_PWM","UART_DBG_TX_AP_RX","UART_AP_TX_DBG_RX","","BIGCPU_DVS_PWM","EDP_HPD_3V0",/* GPIO4 D 0-5 */"SD_CARD_DET_L","USB_DP_HPD","TOUCH_RESET_L","PP3300_DISP_EN","","SD_SLOT_PWR_EN";+};
- ap_i2c_mic: &i2c1 { status = "okay";
@@ -286,7 +476,7 @@ ap_i2c_tp: &i2c5 { };
&cros_ec {
- cros_ec_pwm: ec-pwm {
- cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; };
@@ -319,8 +509,7 @@ ap_i2c_tp: &i2c5 { &pci_rootport { mvl_wifi: wifi@0,0 { compatible = "pci1b4b,2b42";
reg = <0x83010000 0x0 0x00000000 0x0 0x001000000x83010000 0x0 0x00100000 0x0 0x00100000>;
reg = <0x0000 0x0 0x0 0x0 0x0>;@@ -395,6 +584,7 @@ ap_i2c_tp: &i2c5 { };
wlan_host_wake_l: wlan-host-wake-l {
/* Kevin has an external pull up, but Bob does not */diff --git a/arch/arm/dts/rk3399-gru-kevin.dts b/arch/arm/dts/rk3399-gru-kevin.dts index 2bbef9fcbe27..2cc9b3386c16 100644 --- a/arch/arm/dts/rk3399-gru-kevin.dts +++ b/arch/arm/dts/rk3399-gru-kevin.dts @@ -24,6 +24,7 @@ "google,kevin-rev9", "google,kevin-rev8", "google,kevin-rev7", "google,kevin-rev6", "google,kevin", "google,gru", "rockchip,rk3399";
chassis-type = "convertible";
/* Power tree */
@@ -91,7 +92,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
- pen-insert {
- switch-pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 0cc40eb6d6f6..6bdc892bd913 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -78,12 +78,14 @@ /delete-property/ bootph-pre-ram; };
+&spi1 {
- spi_flash: flash@0 {
bootph-all;- };
+};
- &spi5 { spi-activate-delay = <100>; spi-max-frequency = <3000000>; spi-deactivate-delay = <200>; };
-&spi_flash {
- bootph-all;
-}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index b80f19066b57..d90fe4d40d48 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -250,7 +250,7 @@ pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>;
enable-active-high;
enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;@@ -286,7 +286,7 @@
sound: sound { compatible = "rockchip,rk3399-gru-sound";
rockchip,cpu = <&i2s0 &i2s2>;
rockchip,cpu = <&i2s0 &spdif>;@@ -373,6 +373,34 @@ <200000000>; };
+&dfi {
- status = "okay";
+};
+&dmc {
- status = "okay";
- rockchip,pd-idle-ns = <160>;
- rockchip,sr-idle-ns = <10240>;
- rockchip,sr-mc-gate-idle-ns = <40960>;
- rockchip,srpd-lite-idle-ns = <61440>;
- rockchip,standby-idle-ns = <81920>;
- rockchip,ddr3_odt_dis_freq = <666000000>;
- rockchip,lpddr3_odt_dis_freq = <666000000>;
- rockchip,lpddr4_odt_dis_freq = <666000000>;
- rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
- rockchip,srpd-lite-idle-dis-freq-hz = <0>;
- rockchip,standby-idle-dis-freq-hz = <928000000>;
+};
+&dmc_opp_table {
- opp03 {
opp-suspend;- };
+};
- &emmc_phy { status = "okay"; };
@@ -437,10 +465,6 @@ ap_i2c_audio: &i2c8 { status = "okay"; };
-&i2s2 {
- status = "okay";
-};
- &io_domains { status = "okay";
@@ -461,10 +485,11 @@ ap_i2c_audio: &i2c8 { vpcie0v9-supply = <&pp900_pcie>;
pci_rootport: pcie@0,0 {
reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>;
reg = <0x0000 0 0 0 0>;device_type = "pci";@@ -537,13 +562,24 @@ ap_i2c_audio: &i2c8 { vqmmc-supply = <&ppvar_sd_card_io>; };
+&spdif {
- status = "okay";
- /*
* SPDIF is routed internally to DP; we either don't use these pins, or* mux them to something else.*/- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
+};
&spi1 { status = "okay";
pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>;
- spi_flash: spiflash@0 {
- flash@0 { compatible = "jedec,spi-nor"; reg = <0>;
Sync rk3399-puma related device tree from linux v6.8.
SPL_MAX_SIZE is not adjusted to the now common 0x40000 (256 KiB) due to TPL+SPL combined (idbloader.img) is limited to max 224 KiB because of:
SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Because FIT payload is located at sector 0x200 instead of the more Rockchip common 0x4000, TPL+SPL cannot take up more than 224 KiB:
(0x200 - 64) x 512 = 0x38000 (224 KiB)
Also adjust SPL_PAD_TO to match the 0x200 sector offset.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 20 ++-------- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++++++++++++++++++--- arch/arm/dts/rk3399-puma.dtsi | 17 ++++++++- configs/puma-rk3399_defconfig | 2 +- 4 files changed, 57 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index f48d395f972a..65340f98d595 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -30,18 +30,6 @@ aliases { spi5 = &spi5; }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-init-microvolt = <950000>; - vin-supply = <&vcc5v0_sys>; - }; };
&binman { @@ -87,10 +75,6 @@ bootph-all; };
-&haikou_pin_hog { - bootph-all; -}; - &norflash { bootph-pre-ram; bootph-some-ram; @@ -111,3 +95,7 @@ &uart0_xfer { bootph-all; }; + +&vdd_log { + regulator-init-microvolt = <950000>; +}; diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts index 115c14c0a3c6..18a98c4648ea 100644 --- a/arch/arm/dts/rk3399-puma-haikou.dts +++ b/arch/arm/dts/rk3399-puma-haikou.dts @@ -5,6 +5,7 @@
/dts-v1/; #include "rk3399-puma.dtsi" +#include <dt-bindings/input/input.h>
/ { model = "Theobroma Systems RK3399-Q7 SoM"; @@ -18,6 +19,38 @@ stdout-path = "serial0:115200n8"; };
+ gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&haikou_keys_pin>; + pinctrl-names = "default"; + + button-batlow-n { + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + label = "BATLOW#"; + linux,code = <KEY_BATTERY>; + }; + + button-slp-btn-n { + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + label = "SLP_BTN#"; + linux,code = <KEY_SLEEP>; + }; + + button-wake-n { + gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>; + label = "WAKE#"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + + switch-lid-btn-n { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + label = "LID_BTN#"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + }; + }; + leds { pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
@@ -165,11 +198,8 @@ };
&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&haikou_pin_hog>; - - hog { - haikou_pin_hog: haikou-pin-hog { + buttons { + haikou_keys_pin: haikou-keys-pin { rockchip,pins = /* LID_BTN */ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, @@ -177,7 +207,7 @@ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, - /* BIOS_DISABLE# */ + /* WAKE# */ <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index aa3e21bd6c8f..c08e69391c01 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -9,6 +9,7 @@
/ { aliases { + ethernet0 = &gmac; mmc0 = &sdhci; };
@@ -27,7 +28,7 @@
extcon_usb3: extcon-usb3 { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + id-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb3_id>; }; @@ -119,6 +120,20 @@ drive-impedance-ohm = <33>; };
+&gpio0 { + /* + * The BIOS_DISABLE hog is a feedback pin for the actual status of the + * signal. This usually represents the state of a switch on the baseboard. + * The pin has a 10k pull-up resistor connected, so no pull-up setting is needed. + */ + bios-disable-hog { + gpios = <RK_PB0 GPIO_ACTIVE_HIGH>; + gpio-hog; + input; + line-name = "bios_disable"; + }; +}; + &gmac { assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index cc3d2cf3755d..26d524cabb06 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 -CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_PAD_TO=0x38000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000 CONFIG_SPL_BSS_MAX_SIZE=0x10000
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
Sync rk3399-puma related device tree from linux v6.8.
SPL_MAX_SIZE is not adjusted to the now common 0x40000 (256 KiB) due to TPL+SPL combined (idbloader.img) is limited to max 224 KiB because of:
SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Because FIT payload is located at sector 0x200 instead of the more Rockchip common 0x4000, TPL+SPL cannot take up more than 224 KiB:
(0x200 - 64) x 512 = 0x38000 (224 KiB)
Also adjust SPL_PAD_TO to match the 0x200 sector offset.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 20 ++-------- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++++++++++++++++++--- arch/arm/dts/rk3399-puma.dtsi | 17 ++++++++- configs/puma-rk3399_defconfig | 2 +- 4 files changed, 57 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index f48d395f972a..65340f98d595 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -30,18 +30,6 @@ aliases { spi5 = &spi5; };
vdd_log: vdd-log {
compatible = "pwm-regulator";pwms = <&pwm2 0 25000 1>;regulator-name = "vdd_log";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <800000>;regulator-max-microvolt = <1400000>;regulator-init-microvolt = <950000>;vin-supply = <&vcc5v0_sys>;}; };
&binman {
@@ -87,10 +75,6 @@ bootph-all; };
-&haikou_pin_hog {
- bootph-all;
-};
- &norflash { bootph-pre-ram; bootph-some-ram;
@@ -111,3 +95,7 @@ &uart0_xfer { bootph-all; };
+&vdd_log {
- regulator-init-microvolt = <950000>;
+}; diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts index 115c14c0a3c6..18a98c4648ea 100644 --- a/arch/arm/dts/rk3399-puma-haikou.dts +++ b/arch/arm/dts/rk3399-puma-haikou.dts @@ -5,6 +5,7 @@
/dts-v1/; #include "rk3399-puma.dtsi" +#include <dt-bindings/input/input.h>
/ { model = "Theobroma Systems RK3399-Q7 SoM"; @@ -18,6 +19,38 @@ stdout-path = "serial0:115200n8"; };
- gpio-keys {
compatible = "gpio-keys";pinctrl-0 = <&haikou_keys_pin>;pinctrl-names = "default";
To make sure we keep the same behavior, we would need to enable CONFIG_BUTTON_GPIO in the defconfig for it to do the pinmuxing.
The impact would be limited, so that's something we could deal with later on if you mind having a commit for that in this series.
button-batlow-n {gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;label = "BATLOW#";linux,code = <KEY_BATTERY>;};button-slp-btn-n {gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;label = "SLP_BTN#";linux,code = <KEY_SLEEP>;};button-wake-n {gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;label = "WAKE#";linux,code = <KEY_WAKEUP>;wakeup-source;};switch-lid-btn-n {gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;label = "LID_BTN#";linux,code = <SW_LID>;linux,input-type = <EV_SW>;};- };
- leds { pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
@@ -165,11 +198,8 @@ };
&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&haikou_pin_hog>;
- hog {
haikou_pin_hog: haikou-pin-hog {
- buttons {
haikou_keys_pin: haikou-keys-pin { rockchip,pins = /* LID_BTN */ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,@@ -177,7 +207,7 @@ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
/* BIOS_DISABLE# */
/* WAKE# */ <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index aa3e21bd6c8f..c08e69391c01 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -9,6 +9,7 @@
/ { aliases {
ethernet0 = &gmac;@@ -27,7 +28,7 @@
extcon_usb3: extcon-usb3 { compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
id-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;@@ -119,6 +120,20 @@ drive-impedance-ohm = <33>; };
+&gpio0 {
- /*
* The BIOS_DISABLE hog is a feedback pin for the actual status of the* signal. This usually represents the state of a switch on the baseboard.* The pin has a 10k pull-up resistor connected, so no pull-up setting is needed.*/- bios-disable-hog {
gpios = <RK_PB0 GPIO_ACTIVE_HIGH>;gpio-hog;input;line-name = "bios_disable";- };
+};
- &gmac { assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>;
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index cc3d2cf3755d..26d524cabb06 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 -CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_PAD_TO=0x38000
Those are unrelated changes, please in a different commit (but thanks for catching my mistakes :) ).
Reviewed-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Thanks, Quentin
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-puma related device tree from linux v6.8.
SPL_MAX_SIZE is not adjusted to the now common 0x40000 (256 KiB) due to TPL+SPL combined (idbloader.img) is limited to max 224 KiB because of:
SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Because FIT payload is located at sector 0x200 instead of the more Rockchip common 0x4000, TPL+SPL cannot take up more than 224 KiB:
(0x200 - 64) x 512 = 0x38000 (224 KiB)
Also adjust SPL_PAD_TO to match the 0x200 sector offset.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 20 ++-------- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++++++++++++++++++--- arch/arm/dts/rk3399-puma.dtsi | 17 ++++++++- configs/puma-rk3399_defconfig | 2 +- 4 files changed, 57 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index f48d395f972a..65340f98d595 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -30,18 +30,6 @@ aliases { spi5 = &spi5; };
vdd_log: vdd-log {
compatible = "pwm-regulator";pwms = <&pwm2 0 25000 1>;regulator-name = "vdd_log";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <800000>;regulator-max-microvolt = <1400000>;regulator-init-microvolt = <950000>;vin-supply = <&vcc5v0_sys>;}; };
&binman {
@@ -87,10 +75,6 @@ bootph-all; };
-&haikou_pin_hog {
- bootph-all;
-};
- &norflash { bootph-pre-ram; bootph-some-ram;
@@ -111,3 +95,7 @@ &uart0_xfer { bootph-all; };
+&vdd_log {
- regulator-init-microvolt = <950000>;
+}; diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts index 115c14c0a3c6..18a98c4648ea 100644 --- a/arch/arm/dts/rk3399-puma-haikou.dts +++ b/arch/arm/dts/rk3399-puma-haikou.dts @@ -5,6 +5,7 @@
/dts-v1/; #include "rk3399-puma.dtsi" +#include <dt-bindings/input/input.h>
/ { model = "Theobroma Systems RK3399-Q7 SoM"; @@ -18,6 +19,38 @@ stdout-path = "serial0:115200n8"; };
- gpio-keys {
compatible = "gpio-keys";pinctrl-0 = <&haikou_keys_pin>;pinctrl-names = "default";button-batlow-n {gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;label = "BATLOW#";linux,code = <KEY_BATTERY>;};button-slp-btn-n {gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;label = "SLP_BTN#";linux,code = <KEY_SLEEP>;};button-wake-n {gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;label = "WAKE#";linux,code = <KEY_WAKEUP>;wakeup-source;};switch-lid-btn-n {gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;label = "LID_BTN#";linux,code = <SW_LID>;linux,input-type = <EV_SW>;};- };
- leds { pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
@@ -165,11 +198,8 @@ };
&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&haikou_pin_hog>;
- hog {
haikou_pin_hog: haikou-pin-hog {
- buttons {
haikou_keys_pin: haikou-keys-pin { rockchip,pins = /* LID_BTN */ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,@@ -177,7 +207,7 @@ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
/* BIOS_DISABLE# */
/* WAKE# */ <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index aa3e21bd6c8f..c08e69391c01 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -9,6 +9,7 @@
/ { aliases {
ethernet0 = &gmac;@@ -27,7 +28,7 @@
extcon_usb3: extcon-usb3 { compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
id-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;@@ -119,6 +120,20 @@ drive-impedance-ohm = <33>; };
+&gpio0 {
- /*
* The BIOS_DISABLE hog is a feedback pin for the actual status of the* signal. This usually represents the state of a switch on the baseboard.* The pin has a 10k pull-up resistor connected, so no pull-up setting is needed.*/- bios-disable-hog {
gpios = <RK_PB0 GPIO_ACTIVE_HIGH>;gpio-hog;input;line-name = "bios_disable";- };
+};
- &gmac { assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>;
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index cc3d2cf3755d..26d524cabb06 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -27,7 +27,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 -CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_PAD_TO=0x38000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xff8e0000 CONFIG_SPL_BSS_MAX_SIZE=0x10000
Sync rk3399-rock-pi-n10 related device tree from linux v6.8.
Remove SPL_GPIO=y, board does not use gpio in SPL.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++++++++++++++++++ arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 ++++++-- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++++++++ configs/rock-pi-n10-rk3399pro_defconfig | 8 ++-- 4 files changed, 89 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi index 717cb3dc816e..793951655b73 100644 --- a/arch/arm/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/dts/rk3288-vmarc-som.dtsi @@ -231,11 +231,43 @@ }; };
+&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio5>; + interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + &i2c5 { status = "okay"; };
+&io_domains { + bb-supply = <&vcc_io>; + flash0-supply = <&vccio_flash>; + gpio1830-supply = <&vcc_18>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_wl>; + status = "okay"; +}; + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { drive-strength = <8>; }; @@ -251,6 +283,12 @@ }; };
+ sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus4: sdmmc-bus4 { rockchip,pins = @@ -282,6 +320,16 @@ }; };
+&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi index e1cb426f2aa5..8823c924dc1d 100644 --- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi +++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi @@ -13,8 +13,9 @@ compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; + ethernet0 = &gmac; + mmc0 = &sdhci; + mmc1 = &sdmmc; };
vcc3v3_pcie: vcc-pcie-regulator { @@ -297,11 +298,10 @@ clock-frequency = <400000>; status = "okay";
- hym8563: hym8563@51 { + hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "hym8563"; pinctrl-names = "default"; pinctrl-0 = <&hym8563_int>; @@ -347,7 +347,7 @@
pcie { pcie_pwr: pcie-pwr { - rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; };
@@ -381,6 +381,16 @@ pmu1830-supply = <&vcc_1v8>; };
+&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; +}; + &sdhci { bus-width = <8>; mmc-hs400-1_8v; diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi index 26b53eac4706..da1d548b7330 100644 --- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi @@ -15,6 +15,14 @@ #clock-cells = <0>; };
+ sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -78,6 +86,19 @@ status = "okay"; };
+&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 234d0c9ab0f5..6d93b9e58003 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" @@ -18,7 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -36,17 +35,20 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-n10 related device tree from linux v6.8.
Remove SPL_GPIO=y, board does not use gpio in SPL.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++++++++++++++++++ arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 ++++++-- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++++++++ configs/rock-pi-n10-rk3399pro_defconfig | 8 ++-- 4 files changed, 89 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi index 717cb3dc816e..793951655b73 100644 --- a/arch/arm/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/dts/rk3288-vmarc-som.dtsi @@ -231,11 +231,43 @@ }; };
+&i2c1 {
- clock-frequency = <400000>;
- status = "okay";
- hym8563: rtc@51 {
compatible = "haoyu,hym8563";reg = <0x51>;interrupt-parent = <&gpio5>;interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <0>;clock-output-names = "hym8563";pinctrl-names = "default";pinctrl-0 = <&hym8563_int>;- };
+};
- &i2c5 { status = "okay"; };
+&io_domains {
- bb-supply = <&vcc_io>;
- flash0-supply = <&vccio_flash>;
- gpio1830-supply = <&vcc_18>;
- gpio30-supply = <&vcc_io>;
- sdcard-supply = <&vccio_sd>;
- wifi-supply = <&vcc_wl>;
- status = "okay";
+};
- &pinctrl {
- hym8563 {
hym8563_int: hym8563-int {rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;};- };
- pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { drive-strength = <8>; };
@@ -251,6 +283,12 @@ }; };
- sdio-pwrseq {
wifi_enable_h: wifi-enable-h {rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- sdmmc { sdmmc_bus4: sdmmc-bus4 { rockchip,pins =
@@ -282,6 +320,16 @@ }; };
+&sdio_pwrseq {
- /*
* On the module itself this is one of these (depending* on the actual card populated):* - SDIO_RESET_L_WL_REG_ON* - PDN (power down when low)*/- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */
+};
- &usbphy { status = "okay"; };
diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi index e1cb426f2aa5..8823c924dc1d 100644 --- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi +++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi @@ -13,8 +13,9 @@ compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
aliases {
mmc0 = &sdmmc;mmc1 = &sdhci;
ethernet0 = &gmac;mmc0 = &sdhci;mmc1 = &sdmmc;};
vcc3v3_pcie: vcc-pcie-regulator {
@@ -297,11 +298,10 @@ clock-frequency = <400000>; status = "okay";
- hym8563: hym8563@51 {
- hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>;
clock-frequency = <32768>;@@ -347,7 +347,7 @@
pcie { pcie_pwr: pcie-pwr {
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;@@ -381,6 +381,16 @@ pmu1830-supply = <&vcc_1v8>; };
+&sdio_pwrseq {
- /*
* On the module itself this is one of these (depending* on the actual card populated):* - SDIO_RESET_L_WL_REG_ON* - PDN (power down when low)*/- reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+};
- &sdhci { bus-width = <8>; mmc-hs400-1_8v;
diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi index 26b53eac4706..da1d548b7330 100644 --- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi @@ -15,6 +15,14 @@ #clock-cells = <0>; };
- sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";clocks = <&hym8563>;clock-names = "ext_clock";pinctrl-names = "default";pinctrl-0 = <&wifi_enable_h>;- };
- vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin";
@@ -78,6 +86,19 @@ status = "okay"; };
+&sdio0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cap-sdio-irq;
- keep-power-in-suspend;
- mmc-pwrseq = <&sdio_pwrseq>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
- sd-uhs-sdr104;
- status = "okay";
+};
- &sdmmc { bus-width = <4>; cap-mmc-highspeed;
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index 234d0c9ab0f5..6d93b9e58003 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" @@ -18,7 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" # CONFIG_CONSOLE_MUX is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -36,17 +35,20 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set
Sync rk3399-eaidk-610 device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-eaidk-610.dts | 3 ++- configs/eaidk-610-rk3399_defconfig | 11 ++++++++--- 2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-eaidk-610.dts b/arch/arm/dts/rk3399-eaidk-610.dts index d1f343345f67..173da81fc231 100644 --- a/arch/arm/dts/rk3399-eaidk-610.dts +++ b/arch/arm/dts/rk3399-eaidk-610.dts @@ -15,6 +15,7 @@ compatible = "openailab,eaidk-610", "rockchip,rk3399";
aliases { + ethernet0 = &gmac; mmc0 = &sdio0; mmc1 = &sdmmc; mmc2 = &sdhci; @@ -773,7 +774,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index eba6f90c605b..d9cde9ecced5 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -30,14 +31,19 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -50,5 +56,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-eaidk-610 device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-eaidk-610.dts | 3 ++- configs/eaidk-610-rk3399_defconfig | 11 ++++++++--- 2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-eaidk-610.dts b/arch/arm/dts/rk3399-eaidk-610.dts index d1f343345f67..173da81fc231 100644 --- a/arch/arm/dts/rk3399-eaidk-610.dts +++ b/arch/arm/dts/rk3399-eaidk-610.dts @@ -15,6 +15,7 @@ compatible = "openailab,eaidk-610", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;@@ -773,7 +774,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index eba6f90c605b..d9cde9ecced5 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -30,14 +31,19 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 @@ -50,5 +56,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-leez-p710 device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-leez-p710.dts | 8 +++++--- configs/leez-rk3399_defconfig | 10 ++++++++-- 2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts index 7c93f840bc64..cb69e2145fa9 100644 --- a/arch/arm/dts/rk3399-leez-p710.dts +++ b/arch/arm/dts/rk3399-leez-p710.dts @@ -5,6 +5,7 @@
/dts-v1/; #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -14,6 +15,7 @@ compatible = "leez,p710", "rockchip,rk3399";
aliases { + ethernet0 = &gmac; mmc0 = &sdio0; mmc1 = &sdmmc; mmc2 = &sdhci; @@ -55,7 +57,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vim-supply = <&vcc3v3_sys>; + vin-supply = <&vcc3v3_sys>; };
vcc3v3_sys: vcc3v3-sys { @@ -102,12 +104,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; }; };
@@ -509,7 +511,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 13453e523444..903125aa5c1d 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -30,12 +31,18 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -57,5 +64,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-leez-p710 device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-leez-p710.dts | 8 +++++--- configs/leez-rk3399_defconfig | 10 ++++++++-- 2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts index 7c93f840bc64..cb69e2145fa9 100644 --- a/arch/arm/dts/rk3399-leez-p710.dts +++ b/arch/arm/dts/rk3399-leez-p710.dts @@ -5,6 +5,7 @@
/dts-v1/; #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -14,6 +15,7 @@ compatible = "leez,p710", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;@@ -55,7 +57,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
vim-supply = <&vcc3v3_sys>;
vin-supply = <&vcc3v3_sys>;};
vcc3v3_sys: vcc3v3-sys {
@@ -102,12 +104,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc5v0_sys>;
vin-supply = <&vcc5v0_sys>;@@ -509,7 +511,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 13453e523444..903125aa5c1d 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -13,7 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -30,12 +31,18 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -57,5 +64,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-evb device tree from linux v6.8.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 11 +---------- arch/arm/dts/rk3399-evb.dts | 3 ++- configs/evb-rk3399_defconfig | 6 +++--- 3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index 9df4a02c3e74..68d86194cc4c 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -12,14 +12,6 @@ }; };
-&i2c0 { - bootph-all; -}; - -&rk808 { - bootph-all; -}; - &tcphy1 { status = "okay"; }; @@ -41,10 +33,9 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 7b717ebec8ff..55eca7a50a1f 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -12,6 +12,7 @@ compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
aliases { + ethernet0 = &gmac; mmc0 = &sdhci; };
@@ -55,7 +56,7 @@ };
edp_panel: edp-panel { - compatible ="lg,lp079qx1-sp0v"; + compatible = "lg,lp079qx1-sp0v"; backlight = <&backlight>; enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; power-supply = <&vcc3v3_s0>; diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index afb79987464f..334259f73eb2 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -15,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -30,7 +30,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_HS400_SUPPORT=y @@ -39,6 +38,8 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -69,5 +70,4 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-evb device tree from linux v6.8.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-evb-u-boot.dtsi | 11 +---------- arch/arm/dts/rk3399-evb.dts | 3 ++- configs/evb-rk3399_defconfig | 6 +++--- 3 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index 9df4a02c3e74..68d86194cc4c 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -12,14 +12,6 @@ }; };
-&i2c0 {
- bootph-all;
-};
-&rk808 {
- bootph-all;
-};
- &tcphy1 { status = "okay"; };
@@ -41,10 +33,9 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed;
- cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <150000000>; pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; status = "okay"; };
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 7b717ebec8ff..55eca7a50a1f 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -12,6 +12,7 @@ compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;@@ -55,7 +56,7 @@ };
edp_panel: edp-panel {
compatible ="lg,lp079qx1-sp0v";
compatible = "lg,lp079qx1-sp0v";diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index afb79987464f..334259f73eb2 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -15,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -30,7 +30,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_HS400_SUPPORT=y @@ -39,6 +38,8 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -69,5 +70,4 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-firefly device tree from linux v6.8.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-firefly.dts | 17 ++++++++++++----- configs/firefly-rk3399_defconfig | 13 +++++++++++-- 2 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index c4dd2a6b4836..260415d99aeb 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -5,6 +5,7 @@
/dts-v1/; #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/usb/pd.h> #include "rk3399.dtsi" @@ -15,6 +16,7 @@ compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
aliases { + ethernet0 = &gmac; mmc0 = &sdio0; mmc1 = &sdmmc; mmc2 = &sdhci; @@ -86,7 +88,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>;
- power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; @@ -245,12 +247,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; };
@@ -298,6 +300,11 @@ status = "okay"; };
+&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; @@ -770,8 +777,8 @@ sd-uhs-sdr104;
/* Power supply */ - vqmmc-supply = &vcc1v8_s3; /* IO line */ - vmmc-supply = &vcc_sdio; /* card's power */ + vqmmc-supply = <&vcc1v8_s3>; /* IO line */ + vmmc-supply = <&vcc_sdio>; /* card's power */
#address-cells = <1>; #size-cells = <0>; @@ -781,7 +788,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index db98926b627a..2f81a2ed0da6 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -14,9 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -32,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -61,5 +71,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-firefly device tree from linux v6.8.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-firefly.dts | 17 ++++++++++++----- configs/firefly-rk3399_defconfig | 13 +++++++++++-- 2 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index c4dd2a6b4836..260415d99aeb 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -5,6 +5,7 @@
/dts-v1/; #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/usb/pd.h> #include "rk3399.dtsi" @@ -15,6 +16,7 @@ compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;@@ -86,7 +88,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>;
power {
key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power";@@ -245,12 +247,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc_sys>;
vin-supply = <&vcc_sys>;@@ -298,6 +300,11 @@ status = "okay"; };
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
- &hdmi { ddc-i2c-bus = <&i2c3>; pinctrl-names = "default";
@@ -770,8 +777,8 @@ sd-uhs-sdr104;
/* Power supply */
- vqmmc-supply = &vcc1v8_s3; /* IO line */
- vmmc-supply = &vcc_sdio; /* card's power */
vqmmc-supply = <&vcc1v8_s3>; /* IO line */
vmmc-supply = <&vcc_sdio>; /* card's power */
#address-cells = <1>; #size-cells = <0>;
@@ -781,7 +788,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index db98926b627a..2f81a2ed0da6 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -14,9 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -32,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -61,5 +71,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-orangepi device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-orangepi.dts | 12 +++++++----- configs/orangepi-rk3399_defconfig | 10 ++++++++-- 2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts index 04b54abea3cc..e7551449e718 100644 --- a/arch/arm/dts/rk3399-orangepi.dts +++ b/arch/arm/dts/rk3399-orangepi.dts @@ -7,6 +7,7 @@
#include "dt-bindings/pwm/pwm.h" #include "dt-bindings/input/input.h" +#include <dt-bindings/interrupt-controller/irq.h> #include "dt-bindings/usb/pd.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -16,6 +17,7 @@ compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
aliases { + ethernet0 = &gmac; mmc0 = &sdio0; mmc1 = &sdmmc; mmc2 = &sdhci; @@ -51,13 +53,13 @@ press-threshold-microvolt = <300000>; };
- back { + button-back { label = "Back"; linux,code = <KEY_BACK>; press-threshold-microvolt = <985000>; };
- menu { + button-menu { label = "Menu"; linux,code = <KEY_MENU>; press-threshold-microvolt = <1314000>; @@ -77,7 +79,7 @@ compatible = "gpio-keys"; autorepeat;
- power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; @@ -166,12 +168,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; };
@@ -735,7 +737,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 703732ad15f0..2d0c9b77e584 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -31,12 +32,18 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y @@ -58,5 +65,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-orangepi device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-orangepi.dts | 12 +++++++----- configs/orangepi-rk3399_defconfig | 10 ++++++++-- 2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts index 04b54abea3cc..e7551449e718 100644 --- a/arch/arm/dts/rk3399-orangepi.dts +++ b/arch/arm/dts/rk3399-orangepi.dts @@ -7,6 +7,7 @@
#include "dt-bindings/pwm/pwm.h" #include "dt-bindings/input/input.h" +#include <dt-bindings/interrupt-controller/irq.h> #include "dt-bindings/usb/pd.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -16,6 +17,7 @@ compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;@@ -51,13 +53,13 @@ press-threshold-microvolt = <300000>; };
back {
button-back { label = "Back"; linux,code = <KEY_BACK>; press-threshold-microvolt = <985000>;
menu {
button-menu { label = "Menu"; linux,code = <KEY_MENU>; press-threshold-microvolt = <1314000>;@@ -77,7 +79,7 @@ compatible = "gpio-keys"; autorepeat;
power {
key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Power";@@ -166,12 +168,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc_sys>;
vin-supply = <&vcc_sys>;@@ -735,7 +737,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 703732ad15f0..2d0c9b77e584 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -31,12 +32,18 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y @@ -58,5 +65,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-roc-pc related device tree from linux v6.8.
Add SF_DEFAULT_SPEED=30000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-roc-pc.dtsi | 15 ++++++++------- configs/roc-pc-mezzanine-rk3399_defconfig | 11 ++++++++++- configs/roc-pc-rk3399_defconfig | 7 +++++-- 3 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi index d1aaf8e83391..ca7a446b6568 100644 --- a/arch/arm/dts/rk3399-roc-pc.dtsi +++ b/arch/arm/dts/rk3399-roc-pc.dtsi @@ -14,6 +14,7 @@ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
aliases { + ethernet0 = &gmac; mmc0 = &sdmmc; mmc1 = &sdhci; }; @@ -41,7 +42,7 @@ keyup-threshold-microvolt = <1500000>; poll-interval = <100>;
- recovery { + button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>; @@ -54,7 +55,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key_l>;
- power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; @@ -271,6 +272,8 @@ };
&hdmi { + avdd-0v9-supply = <&vcca0v9_hdmi>; + avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; @@ -310,8 +313,6 @@ vcc10-supply = <&vcc3v3_sys>; vcc11-supply = <&vcc3v3_sys>; vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; vddio-supply = <&vcc_3v0>;
regulators { @@ -371,8 +372,8 @@ }; };
- vcc1v8_hdmi: LDO_REG2 { - regulator-name = "vcc1v8_hdmi"; + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -735,7 +736,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <10000000>; + spi-max-frequency = <30000000>; }; };
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index e13356faabbc..85a20957fa37 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -19,6 +20,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,14 +43,21 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -61,6 +70,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -84,5 +94,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index dee342898d1f..b8adf430e9ea 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -43,12 +42,17 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -85,5 +89,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-roc-pc related device tree from linux v6.8.
Add SF_DEFAULT_SPEED=30000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-roc-pc.dtsi | 15 ++++++++------- configs/roc-pc-mezzanine-rk3399_defconfig | 11 ++++++++++- configs/roc-pc-rk3399_defconfig | 7 +++++-- 3 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/rk3399-roc-pc.dtsi b/arch/arm/dts/rk3399-roc-pc.dtsi index d1aaf8e83391..ca7a446b6568 100644 --- a/arch/arm/dts/rk3399-roc-pc.dtsi +++ b/arch/arm/dts/rk3399-roc-pc.dtsi @@ -14,6 +14,7 @@ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;@@ -41,7 +42,7 @@ keyup-threshold-microvolt = <1500000>; poll-interval = <100>;
recovery {
button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>;@@ -54,7 +55,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwr_key_l>;
power {
key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power";@@ -271,6 +272,8 @@ };
&hdmi {
- avdd-0v9-supply = <&vcca0v9_hdmi>;
- avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>;
@@ -310,8 +313,6 @@ vcc10-supply = <&vcc3v3_sys>; vcc11-supply = <&vcc3v3_sys>; vcc12-supply = <&vcc3v3_sys>;
vcc13-supply = <&vcc3v3_sys>;vcc14-supply = <&vcc3v3_sys>;vddio-supply = <&vcc_3v0>;
regulators {
@@ -371,8 +372,8 @@ }; };
vcc1v8_hdmi: LDO_REG2 {regulator-name = "vcc1v8_hdmi";
vcca1v8_hdmi: LDO_REG2 {regulator-name = "vcca1v8_hdmi"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>;@@ -735,7 +736,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>;
spi-max-frequency = <10000000>;
spi-max-frequency = <30000000>;diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index e13356faabbc..85a20957fa37 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -19,6 +20,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -41,14 +43,21 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -61,6 +70,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -84,5 +94,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index dee342898d1f..b8adf430e9ea 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -43,12 +42,17 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -85,5 +89,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-nanopi-4 related device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y, boards does not use pwm-regulator compatible.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +------------------------ arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 4 ++ arch/arm/dts/rk3399-nanopi4.dtsi | 7 ++-- configs/nanopc-t4-rk3399_defconfig | 14 +++++-- configs/nanopi-m4-2gb-rk3399_defconfig | 18 ++++++-- configs/nanopi-m4-rk3399_defconfig | 18 ++++++-- configs/nanopi-m4b-rk3399_defconfig | 18 ++++++-- configs/nanopi-neo4-rk3399_defconfig | 18 ++++++-- configs/nanopi-r4s-rk3399_defconfig | 12 +++--- 12 files changed, 91 insertions(+), 81 deletions(-)
diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts index 452728b82e42..3bf8f959e42c 100644 --- a/arch/arm/dts/rk3399-nanopc-t4.dts +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -39,7 +39,7 @@ keyup-threshold-microvolt = <1800000>; poll-interval = <100>;
- recovery { + button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>; diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts index 60358ab8c7df..e9cf71f224a3 100644 --- a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts @@ -10,57 +10,4 @@ */
/dts-v1/; -#include "rk3399-nanopi4.dtsi" - -/ { - model = "FriendlyElec NanoPi M4"; - compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; - - vdd_5v: vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - }; - - vcc5v0_core: vcc5v0-core { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_core"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_5v>; - }; - - vcc5v0_usb1: vcc5v0-usb1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb1"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb2: vcc5v0-usb2 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb2"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&vcc3v3_sys { - vin-supply = <&vcc5v0_core>; -}; - -&u2phy0_host { - phy-supply = <&vcc5v0_usb1>; -}; - -&u2phy1_host { - phy-supply = <&vcc5v0_usb2>; -}; - -&vbus_typec { - regulator-always-on; - vin-supply = <&vdd_5v>; -}; +#include "rk3399-nanopi-m4.dts" diff --git a/arch/arm/dts/rk3399-nanopi-m4b.dts b/arch/arm/dts/rk3399-nanopi-m4b.dts index 72182c58cc46..65cb21837b0c 100644 --- a/arch/arm/dts/rk3399-nanopi-m4b.dts +++ b/arch/arm/dts/rk3399-nanopi-m4b.dts @@ -19,7 +19,7 @@ keyup-threshold-microvolt = <1500000>; poll-interval = <100>;
- recovery { + button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>; diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts index cef4d18b599d..fe5b52610010 100644 --- a/arch/arm/dts/rk3399-nanopi-r4s.dts +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -46,9 +46,9 @@ gpio-keys { pinctrl-0 = <&reset_button_pin>;
- /delete-node/ power; + /delete-node/ key-power;
- reset { + key-reset { debounce-interval = <50>; gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; label = "reset"; diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index e0d7a518dfc2..757361249968 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -20,3 +20,7 @@ &vcc3v0_sd { bootph-pre-ram; }; + +&vcc_sdio { + regulator-init-microvolt = <3000000>; +}; diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi index 8c0ff6c96e03..b7f1e47978a6 100644 --- a/arch/arm/dts/rk3399-nanopi4.dtsi +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -18,6 +18,7 @@
/ { aliases { + ethernet0 = &gmac; mmc0 = &sdio0; mmc1 = &sdmmc; mmc2 = &sdhci; @@ -111,7 +112,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key>;
- power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; @@ -167,6 +168,7 @@ };
&emmc_phy { + rockchip,enable-strobe-pulldown; status = "okay"; };
@@ -267,7 +269,7 @@ interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; + pinctrl-0 = <&pmic_int_l>, <&ap_pwroff>, <&clk_32k>; rockchip,system-power-controller; wakeup-source;
@@ -374,7 +376,6 @@ vcc_sdio: LDO_REG4 { regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <3000000>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc_sdio"; diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 89c36e273a9b..93d163b70f4f 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -14,9 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -32,20 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -68,5 +77,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index eb1d2c1f51fc..10bd9fba5388 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index bc0b90b3d861..f5305549716c 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 678f4d9d823f..70de7e0a6d7f 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index d9b7a90e8402..95c5766a41f8 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 1fcccf2bae6e..488d86605f67 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -31,14 +32,16 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y @@ -66,5 +69,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-nanopi-4 related device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y, boards does not use pwm-regulator compatible.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +------------------------ arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 4 ++ arch/arm/dts/rk3399-nanopi4.dtsi | 7 ++-- configs/nanopc-t4-rk3399_defconfig | 14 +++++-- configs/nanopi-m4-2gb-rk3399_defconfig | 18 ++++++-- configs/nanopi-m4-rk3399_defconfig | 18 ++++++-- configs/nanopi-m4b-rk3399_defconfig | 18 ++++++-- configs/nanopi-neo4-rk3399_defconfig | 18 ++++++-- configs/nanopi-r4s-rk3399_defconfig | 12 +++--- 12 files changed, 91 insertions(+), 81 deletions(-)
diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts index 452728b82e42..3bf8f959e42c 100644 --- a/arch/arm/dts/rk3399-nanopc-t4.dts +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -39,7 +39,7 @@ keyup-threshold-microvolt = <1800000>; poll-interval = <100>;
recovery {
button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>;diff --git a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts index 60358ab8c7df..e9cf71f224a3 100644 --- a/arch/arm/dts/rk3399-nanopi-m4-2gb.dts +++ b/arch/arm/dts/rk3399-nanopi-m4-2gb.dts @@ -10,57 +10,4 @@ */
/dts-v1/; -#include "rk3399-nanopi4.dtsi"
-/ {
- model = "FriendlyElec NanoPi M4";
- compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
- vdd_5v: vdd-5v {
compatible = "regulator-fixed";regulator-name = "vdd_5v";regulator-always-on;regulator-boot-on;- };
- vcc5v0_core: vcc5v0-core {
compatible = "regulator-fixed";regulator-name = "vcc5v0_core";regulator-always-on;regulator-boot-on;vin-supply = <&vdd_5v>;- };
- vcc5v0_usb1: vcc5v0-usb1 {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb1";regulator-always-on;regulator-boot-on;vin-supply = <&vcc5v0_sys>;- };
- vcc5v0_usb2: vcc5v0-usb2 {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb2";regulator-always-on;regulator-boot-on;vin-supply = <&vcc5v0_sys>;- };
-};
-&vcc3v3_sys {
- vin-supply = <&vcc5v0_core>;
-};
-&u2phy0_host {
- phy-supply = <&vcc5v0_usb1>;
-};
-&u2phy1_host {
- phy-supply = <&vcc5v0_usb2>;
-};
-&vbus_typec {
- regulator-always-on;
- vin-supply = <&vdd_5v>;
-}; +#include "rk3399-nanopi-m4.dts" diff --git a/arch/arm/dts/rk3399-nanopi-m4b.dts b/arch/arm/dts/rk3399-nanopi-m4b.dts index 72182c58cc46..65cb21837b0c 100644 --- a/arch/arm/dts/rk3399-nanopi-m4b.dts +++ b/arch/arm/dts/rk3399-nanopi-m4b.dts @@ -19,7 +19,7 @@ keyup-threshold-microvolt = <1500000>; poll-interval = <100>;
recovery {
button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>;diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts index cef4d18b599d..fe5b52610010 100644 --- a/arch/arm/dts/rk3399-nanopi-r4s.dts +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -46,9 +46,9 @@ gpio-keys { pinctrl-0 = <&reset_button_pin>;
/delete-node/ power;
/delete-node/ key-power;
reset {
key-reset { debounce-interval = <50>; gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; label = "reset";diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index e0d7a518dfc2..757361249968 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -20,3 +20,7 @@ &vcc3v0_sd { bootph-pre-ram; };
+&vcc_sdio {
- regulator-init-microvolt = <3000000>;
+}; diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi index 8c0ff6c96e03..b7f1e47978a6 100644 --- a/arch/arm/dts/rk3399-nanopi4.dtsi +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -18,6 +18,7 @@
/ { aliases {
ethernet0 = &gmac;@@ -111,7 +112,7 @@ pinctrl-names = "default"; pinctrl-0 = <&power_key>;
power {
key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power";@@ -167,6 +168,7 @@ };
&emmc_phy {
- rockchip,enable-strobe-pulldown; status = "okay"; };
@@ -267,7 +269,7 @@ interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
pinctrl-0 = <&pmic_int_l>, <&ap_pwroff>, <&clk_32k>;@@ -374,7 +376,6 @@ vcc_sdio: LDO_REG4 { regulator-always-on; regulator-boot-on;
regulator-init-microvolt = <3000000>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc_sdio";diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 89c36e273a9b..93d163b70f4f 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -14,9 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -32,20 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -68,5 +77,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index eb1d2c1f51fc..10bd9fba5388 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index bc0b90b3d861..f5305549716c 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index 678f4d9d823f..70de7e0a6d7f 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index d9b7a90e8402..95c5766a41f8 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -6,15 +6,18 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -22,6 +25,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,19 +33,28 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -63,5 +76,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 1fcccf2bae6e..488d86605f67 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -14,7 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -31,14 +32,16 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y @@ -66,5 +69,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-rock960 related device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y and DM_REGULATOR_GPIO=y, boards does not use pwm-regulator or regulator-gpio compatible.
Add USB_XHCI_HCD=y, USB_DWC3=y and USB_DWC3_GENERIC=y to support USB3.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support RockUSB and UMS gadget.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-ficus.dts | 4 ++++ arch/arm/dts/rk3399-rock960.dtsi | 5 ++++- configs/ficus-rk3399_defconfig | 22 +++++++++++++++++----- configs/rock960-rk3399_defconfig | 14 +++++++++++--- 4 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 1ce85a5816e4..30e4879f322c 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -13,6 +13,10 @@ model = "96boards RK3399 Ficus"; compatible = "vamrs,ficus", "rockchip,rk3399";
+ aliases { + ethernet0 = &gmac; + }; + chosen { stdout-path = "serial2:1500000n8"; }; diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index 25dc61c26a94..c920ddf44baf 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -7,6 +7,7 @@
#include "rk3399.dtsi" #include "rk3399-opp.dtsi" +#include <dt-bindings/interrupt-controller/irq.h>
/ { aliases { @@ -127,6 +128,8 @@ };
&hdmi { + avdd-0v9-supply = <&vcca0v9_hdmi>; + avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; @@ -528,7 +531,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index f4e3ebba8f46..0d97b7ecb3c7 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -5,15 +5,18 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -21,6 +24,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,27 +33,35 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y -CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 3b5ab7dc5781..e19b28753156 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,11 +12,11 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_USE_PREBOOT=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -28,6 +28,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -37,6 +39,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -52,6 +57,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -71,9 +77,11 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On Sun, 31 Mar 2024 at 21:34, Jonas Karlman jonas@kwiboo.se wrote:
Sync rk3399-rock960 related device tree from linux v6.8.
TBH I wouldn't class this as "Sync device tree from linux v6.8", it does a dozen other things as well!
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y and DM_REGULATOR_GPIO=y, boards does not use pwm-regulator or regulator-gpio compatible.
Add USB_XHCI_HCD=y, USB_DWC3=y and USB_DWC3_GENERIC=y to support USB3.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Does it init nvme and friends?
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support RockUSB and UMS gadget.
Does this have effect on boot speed?
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
arch/arm/dts/rk3399-ficus.dts | 4 ++++ arch/arm/dts/rk3399-rock960.dtsi | 5 ++++- configs/ficus-rk3399_defconfig | 22 +++++++++++++++++----- configs/rock960-rk3399_defconfig | 14 +++++++++++--- 4 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 1ce85a5816e4..30e4879f322c 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -13,6 +13,10 @@ model = "96boards RK3399 Ficus"; compatible = "vamrs,ficus", "rockchip,rk3399";
aliases {ethernet0 = &gmac;};chosen { stdout-path = "serial2:1500000n8"; };diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index 25dc61c26a94..c920ddf44baf 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -7,6 +7,7 @@
#include "rk3399.dtsi" #include "rk3399-opp.dtsi" +#include <dt-bindings/interrupt-controller/irq.h>
/ { aliases { @@ -127,6 +128,8 @@ };
&hdmi {
avdd-0v9-supply = <&vcca0v9_hdmi>;avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>;@@ -528,7 +531,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>;diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index f4e3ebba8f46..0d97b7ecb3c7 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -5,15 +5,18 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -21,6 +24,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,27 +33,35 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y -CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 3b5ab7dc5781..e19b28753156 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,11 +12,11 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_USE_PREBOOT=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -28,6 +28,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -37,6 +39,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -52,6 +57,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -71,9 +77,11 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -- 2.43.2
Hi Peter,
On 2024-04-03 06:53, Peter Robinson wrote:
On Sun, 31 Mar 2024 at 21:34, Jonas Karlman jonas@kwiboo.se wrote:
Sync rk3399-rock960 related device tree from linux v6.8.
TBH I wouldn't class this as "Sync device tree from linux v6.8", it does a dozen other things as well!
Agree, I have updated the commit subject to "Sync DT from v6.8 and update defconfig" in v2, not sure that will fully address your concern.
This series tries to update all rk3399 boards to v6.8 DT and enable a few similar options (when DT node exists) across all RK3399 boards.
Some boards was missing a lot of features/options that already is supported on other RK3399 boards and having a bigger "get up to date" commit makes sense to me :-)
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y and DM_REGULATOR_GPIO=y, boards does not use pwm-regulator or regulator-gpio compatible.
Add USB_XHCI_HCD=y, USB_DWC3=y and USB_DWC3_GENERIC=y to support USB3.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Does it init nvme and friends?
Yes, it should init nvme and friends after it has tried to find extlinux/script/efi on faster boot media (sdhci/sdmmc).
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support RockUSB and UMS gadget.
Does this have effect on boot speed?
It should not affect boot speed, end-user will have to run a rockusb/ums cmd on cli to use this feature.
Regards, Jonas
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
arch/arm/dts/rk3399-ficus.dts | 4 ++++ arch/arm/dts/rk3399-rock960.dtsi | 5 ++++- configs/ficus-rk3399_defconfig | 22 +++++++++++++++++----- configs/rock960-rk3399_defconfig | 14 +++++++++++--- 4 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 1ce85a5816e4..30e4879f322c 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -13,6 +13,10 @@ model = "96boards RK3399 Ficus"; compatible = "vamrs,ficus", "rockchip,rk3399";
aliases {ethernet0 = &gmac;};chosen { stdout-path = "serial2:1500000n8"; };diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index 25dc61c26a94..c920ddf44baf 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -7,6 +7,7 @@
#include "rk3399.dtsi" #include "rk3399-opp.dtsi" +#include <dt-bindings/interrupt-controller/irq.h>
/ { aliases { @@ -127,6 +128,8 @@ };
&hdmi {
avdd-0v9-supply = <&vcca0v9_hdmi>;avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>;@@ -528,7 +531,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>;diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index f4e3ebba8f46..0d97b7ecb3c7 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -5,15 +5,18 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -21,6 +24,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,27 +33,35 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y -CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 3b5ab7dc5781..e19b28753156 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,11 +12,11 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_USE_PREBOOT=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -28,6 +28,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -37,6 +39,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -52,6 +57,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -71,9 +77,11 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y -- 2.43.2
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-rock960 related device tree from linux v6.8.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove REGULATOR_PWM=y and DM_REGULATOR_GPIO=y, boards does not use pwm-regulator or regulator-gpio compatible.
Add USB_XHCI_HCD=y, USB_DWC3=y and USB_DWC3_GENERIC=y to support USB3.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support RockUSB and UMS gadget.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-ficus.dts | 4 ++++ arch/arm/dts/rk3399-rock960.dtsi | 5 ++++- configs/ficus-rk3399_defconfig | 22 +++++++++++++++++----- configs/rock960-rk3399_defconfig | 14 +++++++++++--- 4 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 1ce85a5816e4..30e4879f322c 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -13,6 +13,10 @@ model = "96boards RK3399 Ficus"; compatible = "vamrs,ficus", "rockchip,rk3399";
- aliases {
ethernet0 = &gmac;- };
- chosen { stdout-path = "serial2:1500000n8"; };
diff --git a/arch/arm/dts/rk3399-rock960.dtsi b/arch/arm/dts/rk3399-rock960.dtsi index 25dc61c26a94..c920ddf44baf 100644 --- a/arch/arm/dts/rk3399-rock960.dtsi +++ b/arch/arm/dts/rk3399-rock960.dtsi @@ -7,6 +7,7 @@
#include "rk3399.dtsi" #include "rk3399-opp.dtsi" +#include <dt-bindings/interrupt-controller/irq.h>
/ { aliases { @@ -127,6 +128,8 @@ };
&hdmi {
- avdd-0v9-supply = <&vcca0v9_hdmi>;
- avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>;
@@ -528,7 +531,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index f4e3ebba8f46..0d97b7ecb3c7 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -5,15 +5,18 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_ROCK960_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -21,6 +24,7 @@ CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -29,27 +33,35 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y -CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 3b5ab7dc5781..e19b28753156 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -12,11 +12,11 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_USE_PREBOOT=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" CONFIG_SYS_PBSIZE=1052 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y @@ -28,6 +28,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y # CONFIG_CMD_SF is not set CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -37,6 +39,9 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_ROCKCHIP_IODOMAIN=y @@ -52,6 +57,7 @@ CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -71,9 +77,11 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-khadas related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support RockUSB and UMS gadget.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 +++ arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 5 +++ arch/arm/dts/rk3399-khadas-edge-v.dts | 4 +++ arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +++--- configs/khadas-edge-captain-rk3399_defconfig | 33 ++++++++++++++++++-- configs/khadas-edge-rk3399_defconfig | 27 +++++++++++++--- configs/khadas-edge-v-rk3399_defconfig | 33 ++++++++++++++++++-- 7 files changed, 100 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts b/arch/arm/dts/rk3399-khadas-edge-captain.dts index 8302e51def52..99ac4ed0f13f 100644 --- a/arch/arm/dts/rk3399-khadas-edge-captain.dts +++ b/arch/arm/dts/rk3399-khadas-edge-captain.dts @@ -10,6 +10,10 @@ / { model = "Khadas Edge-Captain"; compatible = "khadas,edge-captain", "rockchip,rk3399"; + + aliases { + ethernet0 = &gmac; + }; };
&gmac { diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi index 4a3b23e48313..dd7a84d2b4a8 100644 --- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi @@ -6,6 +6,11 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
+&spiflash { + bootph-pre-ram; + bootph-some-ram; +}; + &vdd_log { regulator-init-microvolt = <950000>; }; diff --git a/arch/arm/dts/rk3399-khadas-edge-v.dts b/arch/arm/dts/rk3399-khadas-edge-v.dts index f5dcb99dc349..e12e7b4d64ca 100644 --- a/arch/arm/dts/rk3399-khadas-edge-v.dts +++ b/arch/arm/dts/rk3399-khadas-edge-v.dts @@ -10,6 +10,10 @@ / { model = "Khadas Edge-V"; compatible = "khadas,edge-v", "rockchip,rk3399"; + + aliases { + ethernet0 = &gmac; + }; };
&gmac { diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi index d5c7648c841d..9d9297bc5f04 100644 --- a/arch/arm/dts/rk3399-khadas-edge.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge.dtsi @@ -6,6 +6,7 @@
/dts-v1/; #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -80,12 +81,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vsys_3v3>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vsys_3v3>; };
vsys: vsys { @@ -122,7 +123,7 @@ keyup-threshold-microvolt = <1800000>; poll-interval = <100>;
- recovery { + button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>; @@ -135,7 +136,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>;
- power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; @@ -682,7 +683,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; @@ -705,7 +706,6 @@ &sdhci { bus-width = <8>; mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; non-removable; status = "okay"; }; diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 230b9d796442..cf6516656e9a 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -3,51 +3,76 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -63,5 +88,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 9f13cbf58398..f752731dec01 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -3,20 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " @@ -24,21 +31,28 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_PHY_REALTEK=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -47,6 +61,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -62,5 +77,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index abc4f2054cfd..f321d10a7694 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -3,51 +3,76 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -63,5 +88,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-khadas related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add DM_RESET=y to support reset signals.
Add PCI=y, CMD_PCI=y and NVME_PCI=y to support PCIe and NVMe boot.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add CMD_ROCKUSB=y, CMD_USB_MASS_STORAGE=y and USB_GADGET=y to support RockUSB and UMS gadget.
Remove CONFIG_NET_RANDOM_ETHADDR=y, ethaddr and eth1addr is set based on cpuid read from eFUSE.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add MMC_SDHCI_SDMA=y to use DMA transfer for eMMC.
Add DM_ETH_PHY=y to support ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y and PHY_ROCKCHIP_TYPEC=y to support USB PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 +++ arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 5 +++ arch/arm/dts/rk3399-khadas-edge-v.dts | 4 +++ arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +++--- configs/khadas-edge-captain-rk3399_defconfig | 33 ++++++++++++++++++-- configs/khadas-edge-rk3399_defconfig | 27 +++++++++++++--- configs/khadas-edge-v-rk3399_defconfig | 33 ++++++++++++++++++-- 7 files changed, 100 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts b/arch/arm/dts/rk3399-khadas-edge-captain.dts index 8302e51def52..99ac4ed0f13f 100644 --- a/arch/arm/dts/rk3399-khadas-edge-captain.dts +++ b/arch/arm/dts/rk3399-khadas-edge-captain.dts @@ -10,6 +10,10 @@ / { model = "Khadas Edge-Captain"; compatible = "khadas,edge-captain", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;}; };
&gmac {
diff --git a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi index 4a3b23e48313..dd7a84d2b4a8 100644 --- a/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi @@ -6,6 +6,11 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi"
+&spiflash {
- bootph-pre-ram;
- bootph-some-ram;
+};
- &vdd_log { regulator-init-microvolt = <950000>; };
diff --git a/arch/arm/dts/rk3399-khadas-edge-v.dts b/arch/arm/dts/rk3399-khadas-edge-v.dts index f5dcb99dc349..e12e7b4d64ca 100644 --- a/arch/arm/dts/rk3399-khadas-edge-v.dts +++ b/arch/arm/dts/rk3399-khadas-edge-v.dts @@ -10,6 +10,10 @@ / { model = "Khadas Edge-V"; compatible = "khadas,edge-v", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;}; };
&gmac {
diff --git a/arch/arm/dts/rk3399-khadas-edge.dtsi b/arch/arm/dts/rk3399-khadas-edge.dtsi index d5c7648c841d..9d9297bc5f04 100644 --- a/arch/arm/dts/rk3399-khadas-edge.dtsi +++ b/arch/arm/dts/rk3399-khadas-edge.dtsi @@ -6,6 +6,7 @@
/dts-v1/; #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -80,12 +81,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vsys_3v3>;
vin-supply = <&vsys_3v3>;};
vsys: vsys {
@@ -122,7 +123,7 @@ keyup-threshold-microvolt = <1800000>; poll-interval = <100>;
recovery {
button-recovery { label = "Recovery"; linux,code = <KEY_VENDOR>; press-threshold-microvolt = <18000>;@@ -135,7 +136,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>;
power {
key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power";@@ -682,7 +683,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;@@ -705,7 +706,6 @@ &sdhci { bus-width = <8>; mmc-hs400-1_8v;
- mmc-hs400-enhanced-strobe; non-removable; status = "okay"; };
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index 230b9d796442..cf6516656e9a 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -3,51 +3,76 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -63,5 +88,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 9f13cbf58398..f752731dec01 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -3,20 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " @@ -24,21 +31,28 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_PHY_REALTEK=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_GMAC_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y @@ -47,6 +61,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -62,5 +77,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index abc4f2054cfd..f321d10a7694 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -3,51 +3,76 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v" +CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb" CONFIG_SYS_PBSIZE=1048 CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_SYS_PROMPT="kedge# " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -63,5 +88,7 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++ arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++ configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++----- configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++-- configs/rock-pi-4-rk3399_defconfig | 8 +++++++ configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++-- 10 files changed, 114 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 9785b97b9eea..b5ee644a83dd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -11,3 +11,15 @@ &pcfg_pull_up_8ma { bootph-pre-ram; }; + +&spi1 { + status = "okay"; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts index 8bfd5f88d1ef..7baf9d1b22fd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus.dts +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -15,6 +15,7 @@ compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
aliases { + ethernet0 = &gmac; mmc0 = &sdhci; mmc1 = &sdmmc; }; diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi index 85ee5770add0..2213d0093052 100644 --- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi @@ -4,3 +4,15 @@ */
#include "rk3399-rock-pi-4-u-boot.dtsi" + +&spi1 { + status = "okay"; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi index b1b7f4ffb1d4..281a12180703 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -12,6 +12,7 @@
/ { aliases { + ethernet0 = &gmac; mmc0 = &sdhci; mmc1 = &sdmmc; }; @@ -44,7 +45,7 @@ sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>; - clock-names = "ext_clock"; + clock-names = "lpo"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; @@ -492,6 +493,7 @@
&i2s0 { pinctrl-0 = <&i2s0_2ch_bus>; + pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; rockchip,capture-channels = <2>; rockchip,playback-channels = <2>; status = "okay"; diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi index 85ee5770add0..38385621deb1 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi @@ -4,3 +4,10 @@ */
#include "rk3399-rock-pi-4-u-boot.dtsi" + +&spi1 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts index d32efab74e94..de2ebe4cb4f3 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ b/arch/arm/dts/rk3399-rock-pi-4c.dts @@ -43,6 +43,16 @@ hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; };
+&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &uart0 { status = "okay";
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 2024defb2bf0..e97fde17acc2 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -3,22 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -26,7 +31,6 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -40,23 +44,32 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +90,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 9b2303fdf792..13f5f84b9836 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y @@ -36,14 +43,25 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -54,9 +72,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +97,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index e5a2bba8e7ff..d474d91053c1 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -43,6 +44,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -54,8 +57,12 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -66,6 +73,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 4a9d1c531c10..50c6755246f2 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -37,13 +44,25 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -54,9 +73,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +98,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
Hello Jonas,
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
As we know, these boards have no standard connectors for PCI Express expansion cards, which makes me wonder how many users actually use M.2 PCI Express modules with SATA controllers on them with these boards, and need support for them in U-Boot?
I mean, it can't hurt, but frankly, I'm not 100% sure about it.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Otherwise, looking good to me.
Reviewed-by: Dragan Simic dsimic@manjaro.org
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++ arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++ configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++----- configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++-- configs/rock-pi-4-rk3399_defconfig | 8 +++++++ configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++-- 10 files changed, 114 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 9785b97b9eea..b5ee644a83dd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -11,3 +11,15 @@ &pcfg_pull_up_8ma { bootph-pre-ram; };
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts index 8bfd5f88d1ef..7baf9d1b22fd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus.dts +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -15,6 +15,7 @@ compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi index 85ee5770add0..2213d0093052 100644 --- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi @@ -4,3 +4,15 @@ */
#include "rk3399-rock-pi-4-u-boot.dtsi"
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi index b1b7f4ffb1d4..281a12180703 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -12,6 +12,7 @@
/ { aliases {
ethernet0 = &gmac;@@ -44,7 +45,7 @@ sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>;
clock-names = "ext_clock";
clock-names = "lpo";@@ -492,6 +493,7 @@
&i2s0 { pinctrl-0 = <&i2s0_2ch_bus>;
- pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; rockchip,capture-channels = <2>; rockchip,playback-channels = <2>; status = "okay";
diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi index 85ee5770add0..38385621deb1 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi @@ -4,3 +4,10 @@ */
#include "rk3399-rock-pi-4-u-boot.dtsi"
+&spi1 {
- flash@0 {
bootph-pre-ram;bootph-some-ram;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts index d32efab74e94..de2ebe4cb4f3 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ b/arch/arm/dts/rk3399-rock-pi-4c.dts @@ -43,6 +43,16 @@ hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; };
+&spi1 {
- status = "okay";
- flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+};
&uart0 { status = "okay";
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 2024defb2bf0..e97fde17acc2 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -3,22 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -26,7 +31,6 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -40,23 +44,32 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +90,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 9b2303fdf792..13f5f84b9836 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y @@ -36,14 +43,25 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -54,9 +72,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +97,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index e5a2bba8e7ff..d474d91053c1 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -43,6 +44,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -54,8 +57,12 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -66,6 +73,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 4a9d1c531c10..50c6755246f2 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -37,13 +44,25 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -54,9 +73,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +98,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
Hi Dragan,
On 2024-04-01 00:53, Dragan Simic wrote:
Hello Jonas,
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
As we know, these boards have no standard connectors for PCI Express expansion cards, which makes me wonder how many users actually use M.2 PCI Express modules with SATA controllers on them with these boards, and need support for them in U-Boot?
I mean, it can't hurt, but frankly, I'm not 100% sure about it.
With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is very easy to convert the M.2 slot into a standard PCIe X4 slot and use it with a PCIe SATA card. At least that is how I have tested and used this.
I do think there will be many users of PCIe AHCI/SATA, but with this series I try to get all boards to have same feature set as long as there is some way to use a feature.
[1] https://radxa.com/products/accessories/m2-extension-board
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Otherwise, looking good to me.
Reviewed-by: Dragan Simic dsimic@manjaro.org
Thanks!
Regards, Jonas
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++ arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++ configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++----- configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++-- configs/rock-pi-4-rk3399_defconfig | 8 +++++++ configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++-- 10 files changed, 114 insertions(+), 11 deletions(-)
[snip]
On 2024-04-01 01:14, Jonas Karlman wrote:
On 2024-04-01 00:53, Dragan Simic wrote:
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
As we know, these boards have no standard connectors for PCI Express expansion cards, which makes me wonder how many users actually use M.2 PCI Express modules with SATA controllers on them with these boards, and need support for them in U-Boot?
I mean, it can't hurt, but frankly, I'm not 100% sure about it.
With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is very easy to convert the M.2 slot into a standard PCIe X4 slot and use it with a PCIe SATA card. At least that is how I have tested and used this.
I was aware of the M.2 extension board sold by Radxa, but frankly, using it together with another adapter (M.2 to standard PCIe x4 slot) is a cumbersome setup. The whole thing becomes at least three times the size of the SBC, with cables and a dangling PCIe card. :)
I had in mind an M.2 module with a PCIe SATA controller. [2] Something like that, used together with the M.2 extension board, would actually make a rather neat setup.
[2] https://www.reddit.com/r/selfhosted/comments/s0bf1d/m2_sata_expansion_anyone...
I do think there will be many users of PCIe AHCI/SATA, but with this series I try to get all boards to have same feature set as long as there is some way to use a feature.
I guess it can't hurt in the end.
[1] https://radxa.com/products/accessories/m2-extension-board
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Otherwise, looking good to me.
Reviewed-by: Dragan Simic dsimic@manjaro.org
Thanks!
Regards, Jonas
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++ arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++ configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++----- configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++-- configs/rock-pi-4-rk3399_defconfig | 8 +++++++ configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++-- 10 files changed, 114 insertions(+), 11 deletions(-)
[snip]
On 2024-04-01 01:30, Dragan Simic wrote:
On 2024-04-01 01:14, Jonas Karlman wrote:
On 2024-04-01 00:53, Dragan Simic wrote:
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
As we know, these boards have no standard connectors for PCI Express expansion cards, which makes me wonder how many users actually use M.2 PCI Express modules with SATA controllers on them with these boards, and need support for them in U-Boot?
I mean, it can't hurt, but frankly, I'm not 100% sure about it.
With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is very easy to convert the M.2 slot into a standard PCIe X4 slot and use it with a PCIe SATA card. At least that is how I have tested and used this.
I was aware of the M.2 extension board sold by Radxa, but frankly, using it together with another adapter (M.2 to standard PCIe x4 slot) is a cumbersome setup. The whole thing becomes at least three times the size of the SBC, with cables and a dangling PCIe card. :)
I know, it is not ideal, but works for my testing and development proposes :-)
I had in mind an M.2 module with a PCIe SATA controller. [2] Something like that, used together with the M.2 extension board, would actually make a rather neat setup.
I guess the Radxa Penta SATA HAT [3] is most likely use case for having PCIe AHCI enabled.
[3] https://radxa.com/products/accessories/penta-sata-hat/
Regards, Jonas
[2] https://www.reddit.com/r/selfhosted/comments/s0bf1d/m2_sata_expansion_anyone...
I do think there will be many users of PCIe AHCI/SATA, but with this series I try to get all boards to have same feature set as long as there is some way to use a feature.
I guess it can't hurt in the end.
[1] https://radxa.com/products/accessories/m2-extension-board
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Otherwise, looking good to me.
Reviewed-by: Dragan Simic dsimic@manjaro.org
Thanks!
Regards, Jonas
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++ arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++ configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++----- configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++-- configs/rock-pi-4-rk3399_defconfig | 8 +++++++ configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++-- 10 files changed, 114 insertions(+), 11 deletions(-)
[snip]
On 2024-04-01 01:41, Jonas Karlman wrote:
On 2024-04-01 01:30, Dragan Simic wrote:
On 2024-04-01 01:14, Jonas Karlman wrote:
On 2024-04-01 00:53, Dragan Simic wrote:
Please see my comments below.
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
As we know, these boards have no standard connectors for PCI Express expansion cards, which makes me wonder how many users actually use M.2 PCI Express modules with SATA controllers on them with these boards, and need support for them in U-Boot?
I mean, it can't hurt, but frankly, I'm not 100% sure about it.
With the M.2 Extension Board [1] and a M.2 to PCIe X4 adapter it is very easy to convert the M.2 slot into a standard PCIe X4 slot and use it with a PCIe SATA card. At least that is how I have tested and used this.
I was aware of the M.2 extension board sold by Radxa, but frankly, using it together with another adapter (M.2 to standard PCIe x4 slot) is a cumbersome setup. The whole thing becomes at least three times the size of the SBC, with cables and a dangling PCIe card. :)
I know, it is not ideal, but works for my testing and development proposes :-)
I had in mind an M.2 module with a PCIe SATA controller. [2] Something like that, used together with the M.2 extension board, would actually make a rather neat setup.
I guess the Radxa Penta SATA HAT [3] is most likely use case for having PCIe AHCI enabled.
Ah, thanks for reminding me about this hat! I saw it once or twice, but I somehow forgot about it. Yes, that's very nice, and surely a use case for having AHCI support enabled.
[3] https://radxa.com/products/accessories/penta-sata-hat/
Regards, Jonas
[2] https://www.reddit.com/r/selfhosted/comments/s0bf1d/m2_sata_expansion_anyone...
I do think there will be many users of PCIe AHCI/SATA, but with this series I try to get all boards to have same feature set as long as there is some way to use a feature.
I guess it can't hurt in the end.
[1] https://radxa.com/products/accessories/m2-extension-board
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Otherwise, looking good to me.
Reviewed-by: Dragan Simic dsimic@manjaro.org
Thanks!
Regards, Jonas
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++ arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++ configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++----- configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++-- configs/rock-pi-4-rk3399_defconfig | 8 +++++++ configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++-- 10 files changed, 114 insertions(+), 11 deletions(-)
[snip]
Hi Jonas,
On Sun, 2024-03-31 at 20:28 +0000, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Thank you for taking care of this.
Reviewed-by: Christopher Obbard chris.obbard@collabora.com
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++  arch/arm/dts/rk3399-rock-4c-plus.dts        | 1 +  arch/arm/dts/rk3399-rock-4se-u-boot.dtsi    | 12 ++++++++++  arch/arm/dts/rk3399-rock-pi-4.dtsi          | 4 +++-  arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi  | 7 ++++++  arch/arm/dts/rk3399-rock-pi-4c.dts          | 10 ++++++++  configs/rock-4c-plus-rk3399_defconfig       | 24 +++++++++++++++-----  configs/rock-4se-rk3399_defconfig           | 23 +++++++++++++++++--  configs/rock-pi-4-rk3399_defconfig          | 8 +++++++  configs/rock-pi-4c-rk3399_defconfig         | 24 ++++++++++++++++++--  10 files changed, 114 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 9785b97b9eea..b5ee644a83dd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -11,3 +11,15 @@ Â &pcfg_pull_up_8ma { Â bootph-pre-ram; Â };
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399- rock-4c-plus.dts index 8bfd5f88d1ef..7baf9d1b22fd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus.dts +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -15,6 +15,7 @@ Â compatible = "radxa,rock-4c-plus", "rockchip,rk3399"; Â Â aliases {
ethernet0 = &gmac;mmc0 = &sdhci; Â mmc1 = &sdmmc; Â }; diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399- rock-4se-u-boot.dtsi index 85ee5770add0..2213d0093052 100644 --- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi @@ -4,3 +4,15 @@ Â */ Â Â #include "rk3399-rock-pi-4-u-boot.dtsi"
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock- pi-4.dtsi index b1b7f4ffb1d4..281a12180703 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -12,6 +12,7 @@ Â Â / { Â aliases {
ethernet0 = &gmac;mmc0 = &sdhci; Â mmc1 = &sdmmc; Â }; @@ -44,7 +45,7 @@ Â sdio_pwrseq: sdio-pwrseq { Â compatible = "mmc-pwrseq-simple"; Â clocks = <&rk808 1>;
clock-names = "ext_clock";
clock-names = "lpo";pinctrl-names = "default"; Â pinctrl-0 = <&wifi_enable_h>; Â reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; @@ -492,6 +493,7 @@ Â Â &i2s0 { Â pinctrl-0 = <&i2s0_2ch_bus>;
- pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
rockchip,capture-channels = <2>; Â rockchip,playback-channels = <2>; Â status = "okay"; diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi index 85ee5770add0..38385621deb1 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi @@ -4,3 +4,10 @@ Â */ Â Â #include "rk3399-rock-pi-4-u-boot.dtsi"
+&spi1 {
- flash@0 {
bootph-pre-ram;bootph-some-ram;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock- pi-4c.dts index d32efab74e94..de2ebe4cb4f3 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ b/arch/arm/dts/rk3399-rock-pi-4c.dts @@ -43,6 +43,16 @@ Â hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; Â }; Â +&spi1 {
- status = "okay";
- flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+};
&uart0 {  status = "okay";  diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus- rk3399_defconfig index 2024defb2bf0..e97fde17acc2 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -3,22 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y  CONFIG_COUNTER_FREQUENCY=24000000  CONFIG_ARCH_ROCKCHIP=y  CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000  CONFIG_ENV_OFFSET=0x3F8000  CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"  CONFIG_DM_RESET=y  CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y  CONFIG_TARGET_ROCKPI4_RK3399=y  CONFIG_DEBUG_UART_BASE=0xFF1A0000  CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y  CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_PCI=y  CONFIG_DEBUG_UART=y  # CONFIG_ANDROID_BOOT_IMAGE is not set  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb"  CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000  CONFIG_SPL_PAD_TO=0x7f8000  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000  CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y  CONFIG_TPL=y  CONFIG_CMD_BOOTZ=y @@ -26,7 +31,6 @@ CONFIG_CMD_NVEDIT_EFI=y  CONFIG_CMD_DFU=y  CONFIG_CMD_GPT=y  CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y  CONFIG_CMD_USB=y  CONFIG_CMD_ROCKUSB=y  CONFIG_CMD_USB_MASS_STORAGE=y @@ -40,23 +44,32 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y  CONFIG_DFU_MMC=y  CONFIG_ROCKCHIP_GPIO=y  CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y  CONFIG_MMC_DW=y  CONFIG_MMC_DW_ROCKCHIP=y  CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y  CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y  CONFIG_ETH_DESIGNWARE=y  CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME_PCI=y  CONFIG_PHY_ROCKCHIP_INNO_USB2=y  CONFIG_PHY_ROCKCHIP_TYPEC=y  CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y  CONFIG_REGULATOR_RK8XX=y  CONFIG_PWM_ROCKCHIP=y  CONFIG_RAM_ROCKCHIP_LPDDR4=y  CONFIG_BAUDRATE=1500000  CONFIG_DEBUG_UART_SHIFT=2  CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y  CONFIG_SYSRESET=y  CONFIG_USB=y  CONFIG_USB_XHCI_HCD=y @@ -77,7 +90,6 @@ CONFIG_VIDEO=y  CONFIG_DISPLAY=y  CONFIG_VIDEO_ROCKCHIP=y  CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y  CONFIG_ERRNO_STR=y  CONFIG_EFI_CAPSULE_ON_DISK=y  CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se- rk3399_defconfig index 9b2303fdf792..13f5f84b9836 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y  CONFIG_COUNTER_FREQUENCY=24000000  CONFIG_ARCH_ROCKCHIP=y  CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000  CONFIG_ENV_OFFSET=0x3F8000  CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se"  CONFIG_DM_RESET=y  CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y  CONFIG_TARGET_ROCKPI4_RK3399=y  CONFIG_DEBUG_UART_BASE=0xFF1A0000  CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y  CONFIG_SYS_LOAD_ADDR=0x800800  CONFIG_PCI=y  CONFIG_DEBUG_UART=y +CONFIG_AHCI=y  # CONFIG_ANDROID_BOOT_IMAGE is not set  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"  CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000  CONFIG_SPL_PAD_TO=0x7f8000  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000  CONFIG_TPL=y  CONFIG_CMD_BOOTZ=y  CONFIG_CMD_NVEDIT_EFI=y @@ -36,14 +43,25 @@ CONFIG_SPL_OF_CONTROL=y  CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"  CONFIG_ENV_IS_IN_MMC=y  CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y  CONFIG_DFU_MMC=y  CONFIG_ROCKCHIP_GPIO=y  CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y  CONFIG_MMC_DW=y  CONFIG_MMC_DW_ROCKCHIP=y  CONFIG_MMC_SDHCI=y  CONFIG_MMC_SDHCI_SDMA=y  CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y  CONFIG_ETH_DESIGNWARE=y  CONFIG_GMAC_ROCKCHIP=y  CONFIG_NVME_PCI=y @@ -54,9 +72,11 @@ CONFIG_REGULATOR_PWM=y  CONFIG_REGULATOR_RK8XX=y  CONFIG_PWM_ROCKCHIP=y  CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y  CONFIG_BAUDRATE=1500000  CONFIG_DEBUG_UART_SHIFT=2  CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y  CONFIG_SYSRESET=y  CONFIG_USB=y  CONFIG_USB_XHCI_HCD=y @@ -77,7 +97,6 @@ CONFIG_VIDEO=y  CONFIG_DISPLAY=y  CONFIG_VIDEO_ROCKCHIP=y  CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y  CONFIG_ERRNO_STR=y  CONFIG_EFI_CAPSULE_ON_DISK=y  CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4- rk3399_defconfig index e5a2bba8e7ff..d474d91053c1 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_SPI=y  CONFIG_SYS_LOAD_ADDR=0x800800  CONFIG_PCI=y  CONFIG_DEBUG_UART=y +CONFIG_AHCI=y  # CONFIG_ANDROID_BOOT_IMAGE is not set  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"  CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -43,6 +44,8 @@ CONFIG_SPL_OF_CONTROL=y  CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"  CONFIG_ENV_IS_IN_MMC=y  CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y  CONFIG_DFU_MMC=y  CONFIG_ROCKCHIP_GPIO=y  CONFIG_SYS_I2C_ROCKCHIP=y @@ -54,8 +57,12 @@ CONFIG_MMC_SDHCI_SDMA=y  CONFIG_MMC_SDHCI_ROCKCHIP=y  CONFIG_SF_DEFAULT_BUS=1  CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y  CONFIG_SPI_FLASH_WINBOND=y  CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y  CONFIG_ETH_DESIGNWARE=y  CONFIG_GMAC_ROCKCHIP=y  CONFIG_NVME_PCI=y @@ -66,6 +73,7 @@ CONFIG_REGULATOR_PWM=y  CONFIG_REGULATOR_RK8XX=y  CONFIG_PWM_ROCKCHIP=y  CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y  CONFIG_BAUDRATE=1500000  CONFIG_DEBUG_UART_SHIFT=2  CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c- rk3399_defconfig index 4a9d1c531c10..50c6755246f2 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y  CONFIG_COUNTER_FREQUENCY=24000000  CONFIG_ARCH_ROCKCHIP=y  CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000  CONFIG_ENV_OFFSET=0x3F8000  CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"  CONFIG_DM_RESET=y  CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y  CONFIG_TARGET_ROCKPI4_RK3399=y  CONFIG_DEBUG_UART_BASE=0xFF1A0000  CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y  CONFIG_SYS_LOAD_ADDR=0x800800  CONFIG_PCI=y  CONFIG_DEBUG_UART=y +CONFIG_AHCI=y  # CONFIG_ANDROID_BOOT_IMAGE is not set  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"  CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000  CONFIG_SPL_PAD_TO=0x7f8000  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000  CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y  CONFIG_TPL=y  CONFIG_CMD_BOOTZ=y @@ -37,13 +44,25 @@ CONFIG_SPL_OF_CONTROL=y  CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"  CONFIG_ENV_IS_IN_MMC=y  CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y  CONFIG_DFU_MMC=y  CONFIG_ROCKCHIP_GPIO=y  CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y  CONFIG_MMC_DW=y  CONFIG_MMC_DW_ROCKCHIP=y  CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y  CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y  CONFIG_ETH_DESIGNWARE=y  CONFIG_GMAC_ROCKCHIP=y  CONFIG_NVME_PCI=y @@ -54,9 +73,11 @@ CONFIG_REGULATOR_PWM=y  CONFIG_REGULATOR_RK8XX=y  CONFIG_PWM_ROCKCHIP=y  CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y  CONFIG_BAUDRATE=1500000  CONFIG_DEBUG_UART_SHIFT=2  CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y  CONFIG_SYSRESET=y  CONFIG_USB=y  CONFIG_USB_XHCI_HCD=y @@ -77,7 +98,6 @@ CONFIG_VIDEO=y  CONFIG_DISPLAY=y  CONFIG_VIDEO_ROCKCHIP=y  CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y  CONFIG_ERRNO_STR=y  CONFIG_EFI_CAPSULE_ON_DISK=y  CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-rock-pi-4 related device tree from linux v6.8.
Add SPI flash related options to support booting from SPI flash.
Add AHCI=y, SCSI_AHCI=y, AHCI_PCI=y and SCSI=y to support PCIe SATA boot.
Change to SPL_MAX_SIZE=0x40000, SPL can be up to 256 KiB.
Add ROCKCHIP_IODOMAIN=y to configure io-domain voltage.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 ++++++++++ arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +++- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 ++++++ arch/arm/dts/rk3399-rock-pi-4c.dts | 10 ++++++++ configs/rock-4c-plus-rk3399_defconfig | 24 +++++++++++++++----- configs/rock-4se-rk3399_defconfig | 23 +++++++++++++++++-- configs/rock-pi-4-rk3399_defconfig | 8 +++++++ configs/rock-pi-4c-rk3399_defconfig | 24 ++++++++++++++++++-- 10 files changed, 114 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 9785b97b9eea..b5ee644a83dd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -11,3 +11,15 @@ &pcfg_pull_up_8ma { bootph-pre-ram; };
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts index 8bfd5f88d1ef..7baf9d1b22fd 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus.dts +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -15,6 +15,7 @@ compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
aliases {
ethernet0 = &gmac;diff --git a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi index 85ee5770add0..2213d0093052 100644 --- a/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4se-u-boot.dtsi @@ -4,3 +4,15 @@ */
#include "rk3399-rock-pi-4-u-boot.dtsi"
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-pi-4.dtsi b/arch/arm/dts/rk3399-rock-pi-4.dtsi index b1b7f4ffb1d4..281a12180703 100644 --- a/arch/arm/dts/rk3399-rock-pi-4.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4.dtsi @@ -12,6 +12,7 @@
/ { aliases {
ethernet0 = &gmac;@@ -44,7 +45,7 @@ sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>;
clock-names = "ext_clock";
clock-names = "lpo";@@ -492,6 +493,7 @@
&i2s0 { pinctrl-0 = <&i2s0_2ch_bus>;
- pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; rockchip,capture-channels = <2>; rockchip,playback-channels = <2>; status = "okay";
diff --git a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi index 85ee5770add0..38385621deb1 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi @@ -4,3 +4,10 @@ */
#include "rk3399-rock-pi-4-u-boot.dtsi"
+&spi1 {
- flash@0 {
bootph-pre-ram;bootph-some-ram;- };
+}; diff --git a/arch/arm/dts/rk3399-rock-pi-4c.dts b/arch/arm/dts/rk3399-rock-pi-4c.dts index d32efab74e94..de2ebe4cb4f3 100644 --- a/arch/arm/dts/rk3399-rock-pi-4c.dts +++ b/arch/arm/dts/rk3399-rock-pi-4c.dts @@ -43,6 +43,16 @@ hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; };
+&spi1 {
- status = "okay";
- flash@0 {
compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+};
- &uart0 { status = "okay";
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig index 2024defb2bf0..e97fde17acc2 100644 --- a/configs/rock-4c-plus-rk3399_defconfig +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -3,22 +3,27 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_PCI=y CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -26,7 +31,6 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -40,23 +44,32 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +90,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig index 9b2303fdf792..13f5f84b9836 100644 --- a/configs/rock-4se-rk3399_defconfig +++ b/configs/rock-4se-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NVEDIT_EFI=y @@ -36,14 +43,25 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -54,9 +72,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +97,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index e5a2bba8e7ff..d474d91053c1 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -43,6 +44,8 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -54,8 +57,12 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -66,6 +73,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index 4a9d1c531c10..50c6755246f2 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -3,22 +3,29 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_TARGET_ROCKPI4_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -37,13 +44,25 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y CONFIG_DFU_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -54,9 +73,11 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -77,7 +98,6 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
Sync rk3399-rockpro64 device tree from linux v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using the pwr button on the board.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-rockpro64.dtsi | 98 ++++++++++++++++++++++++++++-- configs/rockpro64-rk3399_defconfig | 7 ++- 2 files changed, 97 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi index 6bff8db7d33e..f30b82a10ca3 100644 --- a/arch/arm/dts/rk3399-rockpro64.dtsi +++ b/arch/arm/dts/rk3399-rockpro64.dtsi @@ -11,6 +11,7 @@
/ { aliases { + ethernet0 = &gmac; mmc0 = &sdio0; mmc1 = &sdmmc; mmc2 = &sdhci; @@ -20,6 +21,15 @@ stdout-path = "serial2:1500000n8"; };
+ /* enable for panel backlight support */ + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + pwms = <&pwm0 0 1000000 0>; + status = "disabled"; + }; + clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -33,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>;
- power { + key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power"; @@ -69,6 +79,7 @@
fan: pwm-fan { compatible = "pwm-fan"; + cooling-levels = <0 100 150 200 255>; #cooling-cells = <2>; fan-supply = <&vcc12v_dcin>; pwms = <&pwm1 0 50000 0>; @@ -106,6 +117,14 @@ }; };
+ avdd: avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd"; + regulator-min-microvolt = <11000000>; + regulator-max-microvolt = <11000000>; + vin-supply = <&vcc3v3_s0>; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -212,12 +231,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1700000>; - vin-supply = <&vcc5v0_sys>; }; };
@@ -245,6 +264,34 @@ cpu-supply = <&vdd_cpu_b>; };
+&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &emmc_phy { status = "okay"; }; @@ -371,8 +418,6 @@
vcc3v0_touch: LDO_REG2 { regulator-name = "vcc3v0_touch"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-state-mem { @@ -461,8 +506,6 @@
vcc3v3_s0: SWITCH_REG2 { regulator-name = "vcc3v3_s0"; - regulator-always-on; - regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; @@ -536,6 +579,19 @@ vbus-supply = <&vcc5v0_typec>; status = "okay"; }; + + /* enable for pine64 touch screen support */ + touch: touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>; + AVDD28-supply = <&vcc3v0_touch>; + VDDIO-supply = <&vcc3v0_touch>; + irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; };
&i2s0 { @@ -571,6 +627,36 @@ gpio1830-supply = <&vcc_3v0>; };
+/* enable for pine64 panel display support */ +&mipi_dsi { + clock-master; + status = "disabled"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + mipi_panel: panel@0 { + compatible = "feiyang,fy07024di26a30d"; + reg = <0>; + avdd-supply = <&avdd>; + backlight = <&backlight>; + dvdd-supply = <&vcc3v3_s0>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + &pcie0 { ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 173f8f75020d..4e1af37a1559 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" @@ -20,7 +21,6 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -34,6 +34,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -57,7 +58,10 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -96,5 +100,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-rockpro64 device tree from linux v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using the pwr button on the board.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Looking good to me. Thank you for all these nice cleanups!
Reviewed-by: Dragan Simic dsimic@manjaro.org
arch/arm/dts/rk3399-rockpro64.dtsi | 98 ++++++++++++++++++++++++++++-- configs/rockpro64-rk3399_defconfig | 7 ++- 2 files changed, 97 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi index 6bff8db7d33e..f30b82a10ca3 100644 --- a/arch/arm/dts/rk3399-rockpro64.dtsi +++ b/arch/arm/dts/rk3399-rockpro64.dtsi @@ -11,6 +11,7 @@
/ { aliases {
ethernet0 = &gmac;@@ -20,6 +21,15 @@ stdout-path = "serial2:1500000n8"; };
- /* enable for panel backlight support */
- backlight: backlight {
compatible = "pwm-backlight";brightness-levels = <0 4 8 16 32 64 128 255>;default-brightness-level = <5>;pwms = <&pwm0 0 1000000 0>;status = "disabled";- };
- clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>;
@@ -33,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>;
power {
key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power";@@ -69,6 +79,7 @@
fan: pwm-fan { compatible = "pwm-fan";
cooling-levels = <0 100 150 200 255>;@@ -106,6 +117,14 @@ }; };
- avdd: avdd-regulator {
compatible = "regulator-fixed";regulator-name = "avdd";regulator-min-microvolt = <11000000>;regulator-max-microvolt = <11000000>;vin-supply = <&vcc3v3_s0>;- };
- vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin";
@@ -212,12 +231,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc5v0_sys>;
vin-supply = <&vcc5v0_sys>;};
@@ -245,6 +264,34 @@ cpu-supply = <&vdd_cpu_b>; };
+&cpu_thermal {
- trips {
cpu_warm: cpu_warm {temperature = <55000>;hysteresis = <2000>;type = "active";};cpu_hot: cpu_hot {temperature = <65000>;hysteresis = <2000>;type = "active";};- };
- cooling-maps {
map2 {trip = <&cpu_warm>;cooling-device = <&fan THERMAL_NO_LIMIT 1>;};map3 {trip = <&cpu_hot>;cooling-device = <&fan 2 THERMAL_NO_LIMIT>;};- };
+};
&emmc_phy { status = "okay"; }; @@ -371,8 +418,6 @@
vcc3v0_touch: LDO_REG2 { regulator-name = "vcc3v0_touch";
regulator-always-on;regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-state-mem {@@ -461,8 +506,6 @@
vcc3v3_s0: SWITCH_REG2 { regulator-name = "vcc3v3_s0";
regulator-always-on;regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; };@@ -536,6 +579,19 @@ vbus-supply = <&vcc5v0_typec>; status = "okay"; };
- /* enable for pine64 touch screen support */
- touch: touchscreen@5d {
compatible = "goodix,gt911";reg = <0x5d>;interrupt-parent = <&gpio4>;interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>;AVDD28-supply = <&vcc3v0_touch>;VDDIO-supply = <&vcc3v0_touch>;irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;status = "disabled";- };
};
&i2s0 { @@ -571,6 +627,36 @@ gpio1830-supply = <&vcc_3v0>; };
+/* enable for pine64 panel display support */ +&mipi_dsi {
- clock-master;
- status = "disabled";
- ports {
mipi_out: port@1 {reg = <1>;mipi_out_panel: endpoint {remote-endpoint = <&mipi_in_panel>;};};- };
- mipi_panel: panel@0 {
compatible = "feiyang,fy07024di26a30d";reg = <0>;avdd-supply = <&avdd>;backlight = <&backlight>;dvdd-supply = <&vcc3v3_s0>;port {mipi_in_panel: endpoint {remote-endpoint = <&mipi_out_panel>;};};- };
+};
&pcie0 { ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 173f8f75020d..4e1af37a1559 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" @@ -20,7 +21,6 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -34,6 +34,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -57,7 +58,10 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -96,5 +100,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-rockpro64 device tree from linux v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Remove USE_PREBOOT=y to speed up booting, standard boot will init USB after faster boot media has been evaluated.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using the pwr button on the board.
Add PHY_REALTEK=y and DM_ETH_PHY=y to support ethernet PHY.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-rockpro64.dtsi | 98 ++++++++++++++++++++++++++++-- configs/rockpro64-rk3399_defconfig | 7 ++- 2 files changed, 97 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/rk3399-rockpro64.dtsi b/arch/arm/dts/rk3399-rockpro64.dtsi index 6bff8db7d33e..f30b82a10ca3 100644 --- a/arch/arm/dts/rk3399-rockpro64.dtsi +++ b/arch/arm/dts/rk3399-rockpro64.dtsi @@ -11,6 +11,7 @@
/ { aliases {
ethernet0 = &gmac;@@ -20,6 +21,15 @@ stdout-path = "serial2:1500000n8"; };
- /* enable for panel backlight support */
- backlight: backlight {
compatible = "pwm-backlight";brightness-levels = <0 4 8 16 32 64 128 255>;default-brightness-level = <5>;pwms = <&pwm0 0 1000000 0>;status = "disabled";- };
- clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>;
@@ -33,7 +43,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>;
power {
key-power { debounce-interval = <100>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "GPIO Key Power";@@ -69,6 +79,7 @@
fan: pwm-fan { compatible = "pwm-fan";
cooling-levels = <0 100 150 200 255>;@@ -106,6 +117,14 @@ }; };
- avdd: avdd-regulator {
compatible = "regulator-fixed";regulator-name = "avdd";regulator-min-microvolt = <11000000>;regulator-max-microvolt = <11000000>;vin-supply = <&vcc3v3_s0>;- };
- vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin";
@@ -212,12 +231,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc5v0_sys>;
vin-supply = <&vcc5v0_sys>;@@ -245,6 +264,34 @@ cpu-supply = <&vdd_cpu_b>; };
+&cpu_thermal {
- trips {
cpu_warm: cpu_warm {temperature = <55000>;hysteresis = <2000>;type = "active";};cpu_hot: cpu_hot {temperature = <65000>;hysteresis = <2000>;type = "active";};- };
- cooling-maps {
map2 {trip = <&cpu_warm>;cooling-device = <&fan THERMAL_NO_LIMIT 1>;};map3 {trip = <&cpu_hot>;cooling-device = <&fan 2 THERMAL_NO_LIMIT>;};- };
+};
- &emmc_phy { status = "okay"; };
@@ -371,8 +418,6 @@
vcc3v0_touch: LDO_REG2 { regulator-name = "vcc3v0_touch";
regulator-always-on;regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-state-mem {@@ -461,8 +506,6 @@
vcc3v3_s0: SWITCH_REG2 { regulator-name = "vcc3v3_s0";
regulator-always-on;regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; };@@ -536,6 +579,19 @@ vbus-supply = <&vcc5v0_typec>; status = "okay"; };
/* enable for pine64 touch screen support */
touch: touchscreen@5d {
compatible = "goodix,gt911";reg = <0x5d>;interrupt-parent = <&gpio4>;interrupts = <RK_PD5 IRQ_TYPE_EDGE_FALLING>;AVDD28-supply = <&vcc3v0_touch>;VDDIO-supply = <&vcc3v0_touch>;irq-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;status = "disabled";}; };
&i2s0 {
@@ -571,6 +627,36 @@ gpio1830-supply = <&vcc_3v0>; };
+/* enable for pine64 panel display support */ +&mipi_dsi {
- clock-master;
- status = "disabled";
- ports {
mipi_out: port@1 {reg = <1>;mipi_out_panel: endpoint {remote-endpoint = <&mipi_in_panel>;};};- };
- mipi_panel: panel@0 {
compatible = "feiyang,fy07024di26a30d";reg = <0>;avdd-supply = <&avdd>;backlight = <&backlight>;dvdd-supply = <&vcc3v3_s0>;port {mipi_in_panel: endpoint {remote-endpoint = <&mipi_out_panel>;};};- };
+};
- &pcie0 { ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>;
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 173f8f75020d..4e1af37a1559 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -4,6 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" @@ -20,7 +21,6 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -34,6 +34,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -57,7 +58,10 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y @@ -96,5 +100,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-pinebook-pro device tree from linux v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using the pwr button on the board.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +++++++----------------- configs/pinebook-pro-rk3399_defconfig | 6 ++++-- 2 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts index d6b68d77d63a..054c6a4d1a45 100644 --- a/arch/arm/dts/rk3399-pinebook-pro.dts +++ b/arch/arm/dts/rk3399-pinebook-pro.dts @@ -50,19 +50,9 @@ pinctrl-0 = <&panel_en_pin>; power-supply = <&vcc3v3_panel>;
- ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - panel_in_edp: endpoint@0 { - reg = <0>; - remote-endpoint = <&edp_out_panel>; - }; + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; }; }; }; @@ -76,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lidbtn_pin>;
- lid { + switch-lid { debounce-interval = <20>; gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; label = "Lid"; @@ -92,7 +82,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn_pin>;
- power { + key-power { debounce-interval = <20>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "Power"; @@ -675,7 +665,7 @@ i2c-scl-rising-time-ns = <168>; status = "okay";
- es8316: es8316@11 { + es8316: audio-codec@11 { compatible = "everest,es8316"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; @@ -943,7 +933,7 @@ disable-wp; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - sd-uhs-sdr104; + sd-uhs-sdr50; vmmc-supply = <&vcc3v0_sd>; vqmmc-supply = <&vcc_sdio>; status = "okay"; diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index dd8bc2b72cc3..8ac6ddd49dea 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -64,7 +65,9 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -98,5 +101,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-pinebook-pro device tree from linux v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using the pwr button on the board.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Looking good to me.
Reviewed-by: Dragan Simic dsimic@manjaro.org
arch/arm/dts/rk3399-pinebook-pro.dts | 24 +++++++----------------- configs/pinebook-pro-rk3399_defconfig | 6 ++++-- 2 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts index d6b68d77d63a..054c6a4d1a45 100644 --- a/arch/arm/dts/rk3399-pinebook-pro.dts +++ b/arch/arm/dts/rk3399-pinebook-pro.dts @@ -50,19 +50,9 @@ pinctrl-0 = <&panel_en_pin>; power-supply = <&vcc3v3_panel>;
ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;#address-cells = <1>;#size-cells = <0>;panel_in_edp: endpoint@0 {reg = <0>;remote-endpoint = <&edp_out_panel>;};
port {panel_in_edp: endpoint {remote-endpoint = <&edp_out_panel>; };@@ -76,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lidbtn_pin>;
lid {
switch-lid { debounce-interval = <20>; gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; label = "Lid";@@ -92,7 +82,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn_pin>;
power {
key-power { debounce-interval = <20>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "Power";@@ -675,7 +665,7 @@ i2c-scl-rising-time-ns = <168>; status = "okay";
- es8316: es8316@11 {
- es8316: audio-codec@11 { compatible = "everest,es8316"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>;
@@ -943,7 +933,7 @@ disable-wp; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- sd-uhs-sdr104;
- sd-uhs-sdr50; vmmc-supply = <&vcc3v0_sd>; vqmmc-supply = <&vcc_sdio>; status = "okay";
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index dd8bc2b72cc3..8ac6ddd49dea 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -64,7 +65,9 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -98,5 +101,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-pinebook-pro device tree from linux v6.8.
Add SF_DEFAULT_SPEED=10000000 and SPI_FLASH_SFDP_SUPPORT=y to improve support for booting from SPI flash.
Add CMD_POWEROFF=y to support poweroff using cmdline and power on using the pwr button on the board.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-pinebook-pro.dts | 24 +++++++----------------- configs/pinebook-pro-rk3399_defconfig | 6 ++++-- 2 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts index d6b68d77d63a..054c6a4d1a45 100644 --- a/arch/arm/dts/rk3399-pinebook-pro.dts +++ b/arch/arm/dts/rk3399-pinebook-pro.dts @@ -50,19 +50,9 @@ pinctrl-0 = <&panel_en_pin>; power-supply = <&vcc3v3_panel>;
ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;#address-cells = <1>;#size-cells = <0>;panel_in_edp: endpoint@0 {reg = <0>;remote-endpoint = <&edp_out_panel>;};
port {panel_in_edp: endpoint {remote-endpoint = <&edp_out_panel>; };@@ -76,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lidbtn_pin>;
lid {
switch-lid { debounce-interval = <20>; gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; label = "Lid";@@ -92,7 +82,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pwrbtn_pin>;
power {
key-power { debounce-interval = <20>; gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; label = "Power";@@ -675,7 +665,7 @@ i2c-scl-rising-time-ns = <168>; status = "okay";
- es8316: es8316@11 {
- es8316: audio-codec@11 { compatible = "everest,es8316"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>;
@@ -943,7 +933,7 @@ disable-wp; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- sd-uhs-sdr104;
- sd-uhs-sdr50; vmmc-supply = <&vcc3v0_sd>; vqmmc-supply = <&vcc_sdio>; status = "okay";
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index dd8bc2b72cc3..8ac6ddd49dea 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -4,7 +4,7 @@ CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" @@ -36,6 +36,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -64,7 +65,9 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_NVME_PCI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -98,5 +101,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Sync rk3399-pinephone-pro device tree from linux v6.8.
Add SPI flash related node and options to support booting from SPI flash.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Add SYS_NS16550_MEM32=y to use readl/writel for serial console.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 12 ++ arch/arm/dts/rk3399-pinephone-pro.dts | 147 ++++++++++++++++++ configs/pinephone-pro-rk3399_defconfig | 8 +- 3 files changed, 163 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index dcfcec4f3072..6a248691e29d 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -13,3 +13,15 @@ &sdmmc { max-frequency = <20000000>; }; + +&spi1 { + status = "okay"; + + flash@0 { + bootph-pre-ram; + bootph-some-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts index 04403a76238b..61f3fec5a8b1 100644 --- a/arch/arm/dts/rk3399-pinephone-pro.dts +++ b/arch/arm/dts/rk3399-pinephone-pro.dts @@ -10,6 +10,7 @@ */
/dts-v1/; +#include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/linux-event-codes.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -29,6 +30,31 @@ stdout-path = "serial2:115200n8"; };
+ adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1600000>; + poll-interval = <100>; + + button-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <600000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 50000 0>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -102,6 +128,37 @@ /* WL_REG_ON on module */ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + + /* MIPI DSI panel 1.8v supply */ + vcc1v8_lcd: vcc1v8-lcd { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + }; + + /* MIPI DSI panel 2.8v supply */ + vcc2v8_lcd: vcc2v8-lcd { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc2v8_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc3v3_sys>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + }; +}; + +&cpu_alert0 { + temperature = <65000>; +}; +&cpu_alert1 { + temperature = <68000>; };
&cpu_l0 { @@ -132,6 +189,11 @@ status = "okay"; };
+&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -326,6 +388,25 @@ }; };
+&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + touchscreen@14 { + compatible = "goodix,gt1158"; + reg = <0x14>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc3v0_touch>; + VDDIO-supply = <&vcc3v0_touch>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1440>; + }; +}; + &cluster0_opp { opp04 { status = "disabled"; @@ -355,6 +436,39 @@ status = "okay"; };
+&mipi_dsi { + status = "okay"; + clock-master; + + ports { + mipi_out: port@1 { + #address-cells = <0>; + #size-cells = <0>; + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "hannstar,hsd060bhw4"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; + vcc-supply = <&vcc2v8_lcd>; + iovcc-supply = <&vcc1v8_lcd>; + pinctrl-names = "default"; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + &pmu_io_domains { pmu1830-supply = <&vcc_1v8>; status = "okay"; @@ -422,6 +536,15 @@ status = "okay"; };
+&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-sd-highspeed; @@ -472,3 +595,27 @@ &uart2 { status = "okay"; }; + +&vopb { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, + <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, + <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index c36898364b5d..1bb7b35a255c 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" @@ -33,7 +33,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -54,18 +53,20 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y @@ -85,5 +86,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024-03-31 22:28, Jonas Karlman wrote:
Sync rk3399-pinephone-pro device tree from linux v6.8.
Add SPI flash related node and options to support booting from SPI flash.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Add SYS_NS16550_MEM32=y to use readl/writel for serial console.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Looking good to me.
Reviewed-by: Dragan Simic dsimic@manjaro.org
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 12 ++ arch/arm/dts/rk3399-pinephone-pro.dts | 147 ++++++++++++++++++ configs/pinephone-pro-rk3399_defconfig | 8 +- 3 files changed, 163 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index dcfcec4f3072..6a248691e29d 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -13,3 +13,15 @@ &sdmmc { max-frequency = <20000000>; };
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts index 04403a76238b..61f3fec5a8b1 100644 --- a/arch/arm/dts/rk3399-pinephone-pro.dts +++ b/arch/arm/dts/rk3399-pinephone-pro.dts @@ -10,6 +10,7 @@ */
/dts-v1/; +#include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/linux-event-codes.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -29,6 +30,31 @@ stdout-path = "serial2:115200n8"; };
- adc-keys {
compatible = "adc-keys";io-channels = <&saradc 1>;io-channel-names = "buttons";keyup-threshold-microvolt = <1600000>;poll-interval = <100>;button-up {label = "Volume Up";linux,code = <KEY_VOLUMEUP>;press-threshold-microvolt = <100000>;};button-down {label = "Volume Down";linux,code = <KEY_VOLUMEDOWN>;press-threshold-microvolt = <600000>;};- };
- backlight: backlight {
compatible = "pwm-backlight";pwms = <&pwm0 0 50000 0>;- };
- gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default";
@@ -102,6 +128,37 @@ /* WL_REG_ON on module */ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; };
- /* MIPI DSI panel 1.8v supply */
- vcc1v8_lcd: vcc1v8-lcd {
compatible = "regulator-fixed";enable-active-high;regulator-name = "vcc1v8_lcd";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;vin-supply = <&vcc3v3_sys>;gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";- };
- /* MIPI DSI panel 2.8v supply */
- vcc2v8_lcd: vcc2v8-lcd {
compatible = "regulator-fixed";enable-active-high;regulator-name = "vcc2v8_lcd";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;vin-supply = <&vcc3v3_sys>;gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";- };
+};
+&cpu_alert0 {
- temperature = <65000>;
+}; +&cpu_alert1 {
- temperature = <68000>;
};
&cpu_l0 { @@ -132,6 +189,11 @@ status = "okay"; };
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
&i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -326,6 +388,25 @@ }; };
+&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
- touchscreen@14 {
compatible = "goodix,gt1158";reg = <0x14>;interrupt-parent = <&gpio3>;interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>;irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;AVDD28-supply = <&vcc3v0_touch>;VDDIO-supply = <&vcc3v0_touch>;touchscreen-size-x = <720>;touchscreen-size-y = <1440>;- };
+};
&cluster0_opp { opp04 { status = "disabled"; @@ -355,6 +436,39 @@ status = "okay"; };
+&mipi_dsi {
- status = "okay";
- clock-master;
- ports {
mipi_out: port@1 {#address-cells = <0>;#size-cells = <0>;reg = <1>;mipi_out_panel: endpoint {remote-endpoint = <&mipi_in_panel>;};};- };
- panel@0 {
compatible = "hannstar,hsd060bhw4";reg = <0>;backlight = <&backlight>;reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;vcc-supply = <&vcc2v8_lcd>;iovcc-supply = <&vcc1v8_lcd>;pinctrl-names = "default";port {mipi_in_panel: endpoint {remote-endpoint = <&mipi_out_panel>;};};- };
+};
&pmu_io_domains { pmu1830-supply = <&vcc_1v8>; status = "okay"; @@ -422,6 +536,15 @@ status = "okay"; };
+&pwm0 {
- status = "okay";
+};
+&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
+};
&sdmmc { bus-width = <4>; cap-sd-highspeed; @@ -472,3 +595,27 @@ &uart2 { status = "okay"; };
+&vopb {
- status = "okay";
- assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,
<&cru ACLK_VOP0>, <&cru HCLK_VOP0>;- assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
- assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
+};
+&vopb_mmu {
- status = "okay";
+};
+&vopl {
- status = "okay";
- assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>,
<&cru ACLK_VOP1>, <&cru HCLK_VOP1>;- assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
- assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
+};
+&vopl_mmu {
- status = "okay";
+}; diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index c36898364b5d..1bb7b35a255c 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" @@ -33,7 +33,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -54,18 +53,20 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y @@ -85,5 +86,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
On 2024/4/1 04:28, Jonas Karlman wrote:
Sync rk3399-pinephone-pro device tree from linux v6.8.
Add SPI flash related node and options to support booting from SPI flash.
Remove REGULATOR_PWM=y, board does not use pwm-regulator compatible.
Add SYS_NS16550_MEM32=y to use readl/writel for serial console.
Remove SPL_TINY_MEMSET=y to use full memset in SPL.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 12 ++ arch/arm/dts/rk3399-pinephone-pro.dts | 147 ++++++++++++++++++ configs/pinephone-pro-rk3399_defconfig | 8 +- 3 files changed, 163 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index dcfcec4f3072..6a248691e29d 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -13,3 +13,15 @@ &sdmmc { max-frequency = <20000000>; };
+&spi1 {
- status = "okay";
- flash@0 {
bootph-pre-ram;bootph-some-ram;compatible = "jedec,spi-nor";reg = <0>;spi-max-frequency = <10000000>;- };
+}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts index 04403a76238b..61f3fec5a8b1 100644 --- a/arch/arm/dts/rk3399-pinephone-pro.dts +++ b/arch/arm/dts/rk3399-pinephone-pro.dts @@ -10,6 +10,7 @@ */
/dts-v1/; +#include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/linux-event-codes.h> #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -29,6 +30,31 @@ stdout-path = "serial2:115200n8"; };
- adc-keys {
compatible = "adc-keys";io-channels = <&saradc 1>;io-channel-names = "buttons";keyup-threshold-microvolt = <1600000>;poll-interval = <100>;button-up {label = "Volume Up";linux,code = <KEY_VOLUMEUP>;press-threshold-microvolt = <100000>;};button-down {label = "Volume Down";linux,code = <KEY_VOLUMEDOWN>;press-threshold-microvolt = <600000>;};- };
- backlight: backlight {
compatible = "pwm-backlight";pwms = <&pwm0 0 50000 0>;- };
- gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default";
@@ -102,6 +128,37 @@ /* WL_REG_ON on module */ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; };
- /* MIPI DSI panel 1.8v supply */
- vcc1v8_lcd: vcc1v8-lcd {
compatible = "regulator-fixed";enable-active-high;regulator-name = "vcc1v8_lcd";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;vin-supply = <&vcc3v3_sys>;gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";- };
- /* MIPI DSI panel 2.8v supply */
- vcc2v8_lcd: vcc2v8-lcd {
compatible = "regulator-fixed";enable-active-high;regulator-name = "vcc2v8_lcd";regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;vin-supply = <&vcc3v3_sys>;gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";- };
+};
+&cpu_alert0 {
- temperature = <65000>;
+}; +&cpu_alert1 {
temperature = <68000>; };
&cpu_l0 {
@@ -132,6 +189,11 @@ status = "okay"; };
+&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+};
- &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>;
@@ -326,6 +388,25 @@ }; };
+&i2c3 {
- i2c-scl-rising-time-ns = <450>;
- i2c-scl-falling-time-ns = <15>;
- status = "okay";
- touchscreen@14 {
compatible = "goodix,gt1158";reg = <0x14>;interrupt-parent = <&gpio3>;interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>;irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;AVDD28-supply = <&vcc3v0_touch>;VDDIO-supply = <&vcc3v0_touch>;touchscreen-size-x = <720>;touchscreen-size-y = <1440>;- };
+};
- &cluster0_opp { opp04 { status = "disabled";
@@ -355,6 +436,39 @@ status = "okay"; };
+&mipi_dsi {
- status = "okay";
- clock-master;
- ports {
mipi_out: port@1 {#address-cells = <0>;#size-cells = <0>;reg = <1>;mipi_out_panel: endpoint {remote-endpoint = <&mipi_in_panel>;};};- };
- panel@0 {
compatible = "hannstar,hsd060bhw4";reg = <0>;backlight = <&backlight>;reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;vcc-supply = <&vcc2v8_lcd>;iovcc-supply = <&vcc1v8_lcd>;pinctrl-names = "default";port {mipi_in_panel: endpoint {remote-endpoint = <&mipi_out_panel>;};};- };
+};
- &pmu_io_domains { pmu1830-supply = <&vcc_1v8>; status = "okay";
@@ -422,6 +536,15 @@ status = "okay"; };
+&pwm0 {
- status = "okay";
+};
+&saradc {
- vref-supply = <&vcca1v8_s3>;
- status = "okay";
+};
- &sdmmc { bus-width = <4>; cap-sd-highspeed;
@@ -472,3 +595,27 @@ &uart2 { status = "okay"; };
+&vopb {
- status = "okay";
- assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,
<&cru ACLK_VOP0>, <&cru HCLK_VOP0>;- assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
- assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
+};
+&vopb_mmu {
- status = "okay";
+};
+&vopl {
- status = "okay";
- assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>,
<&cru ACLK_VOP1>, <&cru HCLK_VOP1>;- assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
- assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
+};
+&vopl_mmu {
- status = "okay";
+}; diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig index c36898364b5d..1bb7b35a255c 100644 --- a/configs/pinephone-pro-rk3399_defconfig +++ b/configs/pinephone-pro-rk3399_defconfig @@ -3,7 +3,7 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" @@ -33,7 +33,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y @@ -54,18 +53,20 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_SILICONKAISER=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_ROCKCHIP_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y @@ -85,5 +86,4 @@ CONFIG_VIDEO=y CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_EDP=y -CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
[1] https://lists.denx.de/pipermail/u-boot/2024-March/549611.html
-Sumit
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
-- 2.43.2
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
Reviewability is one of the shortcomings with a switch to OF_UPSTREAM.
Regards, Jonas
[1] https://lists.denx.de/pipermail/u-boot/2024-March/549611.html
-Sumit
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
-- 2.43.2
On 2024-04-01 11:45, Jonas Karlman wrote:
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
Also forgot to mention that these synced DT files still contains some minor modification in #include dtsi paths of files that is shared between rk3288 (armv7) and rk3399 (armv8), so a full sync of rk3288 to linux v6.8 would be recommended before doing a full move to OF_UPSTREAM of rk3399.
Reviewability is one of the shortcomings with a switch to OF_UPSTREAM.
Regards, Jonas
[1] https://lists.denx.de/pipermail/u-boot/2024-March/549611.html
-Sumit
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
-- 2.43.2
On Mon, 1 Apr 2024 at 15:31, Jonas Karlman jonas@kwiboo.se wrote:
On 2024-04-01 11:45, Jonas Karlman wrote:
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
Also forgot to mention that these synced DT files still contains some minor modification in #include dtsi paths of files that is shared between rk3288 (armv7) and rk3399 (armv8),
I can only see rockchip-u-boot.dtsi being shared which should be handled automatically. Is there anything else I am missing here?
-Sumit
On 2024-04-01 12:53, Sumit Garg wrote:
On Mon, 1 Apr 2024 at 15:31, Jonas Karlman jonas@kwiboo.se wrote:
On 2024-04-01 11:45, Jonas Karlman wrote:
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
Also forgot to mention that these synced DT files still contains some minor modification in #include dtsi paths of files that is shared between rk3288 (armv7) and rk3399 (armv8),
I can only see rockchip-u-boot.dtsi being shared which should be handled automatically. Is there anything else I am missing here?
The following is a diff of arch/arm/dts rk3399 DTs after this series compared to fully synced v6.8.
Also the content of cros-ec-keyboard.dtsi was excluded in this sync because it initially caused compile issues.
diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index d90fe4d40d48..789fd0dcc88b 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -684,8 +684,8 @@ ap_i2c_audio: &i2c8 { status = "okay"; };
-#include <cros-ec-keyboard.dtsi> -#include <cros-ec-sbs.dtsi> +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi>
&pinctrl { /* diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10.dts b/arch/arm/dts/rk3399pro-rock-pi-n10.dts index bf026786fa92..c58fb7658d7a 100644 --- a/arch/arm/dts/rk3399pro-rock-pi-n10.dts +++ b/arch/arm/dts/rk3399pro-rock-pi-n10.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3399.dtsi" #include "rk3399-opp.dtsi" -#include <rockchip-radxa-dalang-carrier.dtsi> +#include <arm/rockchip/rockchip-radxa-dalang-carrier.dtsi> #include "rk3399pro-vmarc-som.dtsi"
/ {
Regards, Jonas
-Sumit
On Mon, 1 Apr 2024 at 16:34, Jonas Karlman jonas@kwiboo.se wrote:
On 2024-04-01 12:53, Sumit Garg wrote:
On Mon, 1 Apr 2024 at 15:31, Jonas Karlman jonas@kwiboo.se wrote:
On 2024-04-01 11:45, Jonas Karlman wrote:
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
Also forgot to mention that these synced DT files still contains some minor modification in #include dtsi paths of files that is shared between rk3288 (armv7) and rk3399 (armv8),
I can only see rockchip-u-boot.dtsi being shared which should be handled automatically. Is there anything else I am missing here?
The following is a diff of arch/arm/dts rk3399 DTs after this series compared to fully synced v6.8.
This is due to the different DTS directory structure within U-Boot. With OF_UPSTREAM, these modifications aren't required anymore.
Also the content of cros-ec-keyboard.dtsi was excluded in this sync because it initially caused compile issues.
I suppose that's due to missing #include <dt-bindings/input/cros-ec-keyboard.h> for cros-ec-keyboard.dtsi. Once you enable OF_UPSTREAM then let me know if you encounter such issues.
-Sumit
diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index d90fe4d40d48..789fd0dcc88b 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -684,8 +684,8 @@ ap_i2c_audio: &i2c8 { status = "okay"; };
-#include <cros-ec-keyboard.dtsi> -#include <cros-ec-sbs.dtsi> +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi>
&pinctrl { /* diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10.dts b/arch/arm/dts/rk3399pro-rock-pi-n10.dts index bf026786fa92..c58fb7658d7a 100644 --- a/arch/arm/dts/rk3399pro-rock-pi-n10.dts +++ b/arch/arm/dts/rk3399pro-rock-pi-n10.dts @@ -8,7 +8,7 @@ /dts-v1/; #include "rk3399.dtsi" #include "rk3399-opp.dtsi" -#include <rockchip-radxa-dalang-carrier.dtsi> +#include <arm/rockchip/rockchip-radxa-dalang-carrier.dtsi> #include "rk3399pro-vmarc-som.dtsi"
/ {
Regards, Jonas
-Sumit
On Mon, 1 Apr 2024 at 15:15, Jonas Karlman jonas@kwiboo.se wrote:
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
That's fair given it's a long pending DT sync.
Reviewability is one of the shortcomings with a switch to OF_UPSTREAM.
I suppose the reasoning behind this thinking can be that people are used to reviewing DTs alongside driver changes. However, these patches aren't actual DT changes but rather DT imports which IMHO is a distraction for the reviewer. The actual DT can be looked into dts/upstream/ directory while reviewing the changes.
-Sumit
Regards, Jonas
[1] https://lists.denx.de/pipermail/u-boot/2024-March/549611.html
-Sumit
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
-- 2.43.2
On 2024-04-01 12:08, Sumit Garg wrote:
On Mon, 1 Apr 2024 at 15:15, Jonas Karlman jonas@kwiboo.se wrote:
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
That's fair given it's a long pending DT sync.
Reviewability is one of the shortcomings with a switch to OF_UPSTREAM.
I suppose the reasoning behind this thinking can be that people are used to reviewing DTs alongside driver changes. However, these patches aren't actual DT changes but rather DT imports which IMHO is a distraction for the reviewer. The actual DT can be looked into dts/upstream/ directory while reviewing the changes.
Things like following was easier to spot when reviewing DT syncs: - A property that U-Boot depends on gets removed, as in [1]. - Some DT changes can break changes that has been made to u-boot.dtsi files, e.g. a symbol to a node is no longer available in upstream but referenced in u-boot.dtsi files (happened in this series). - Changes in DT may require a workaround in a u-boot.dtsi file. - u-boot.dtsi contains workarounds that has not yet been upstream but can be removed in a future DT sync. - Driver incompatibilities due to initial driver imported from vendor ended up not fully compatible with upstream linux driver / dt-binding.
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id...
Regards, Jonas
-Sumit
Regards, Jonas
[1] https://lists.denx.de/pipermail/u-boot/2024-March/549611.html
-Sumit
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
On Mon, 1 Apr 2024 at 15:54, Jonas Karlman jonas@kwiboo.se wrote:
On 2024-04-01 12:08, Sumit Garg wrote:
On Mon, 1 Apr 2024 at 15:15, Jonas Karlman jonas@kwiboo.se wrote:
Hi Sumit,
On 2024-04-01 10:52, Sumit Garg wrote:
Hi Jonas,
On Mon, 1 Apr 2024 at 01:59, Jonas Karlman jonas@kwiboo.se wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
Thanks for putting this effort together. A switch to v6.8 tag for OF_UPSTREAM will happen as part of patch [1]. So if you want to save further effort then you can just rebase with a switch to OF_UPSTREAM once that patch [1] lands in next.
Because this is a jump of device tree files from v5.14-rc1 to v6.8, reviewability and being able to cherry-pick these changes to my rk3xxx-2024.04 branch, I think it is much more appropriate to first sync everything to v6.8 and then in a separate series move to OF_UPSTREAM. Else it can be very hard to understand some of the changes that has been and was needed to be made to u-boot.dtsi files.
That's fair given it's a long pending DT sync.
Reviewability is one of the shortcomings with a switch to OF_UPSTREAM.
I suppose the reasoning behind this thinking can be that people are used to reviewing DTs alongside driver changes. However, these patches aren't actual DT changes but rather DT imports which IMHO is a distraction for the reviewer. The actual DT can be looked into dts/upstream/ directory while reviewing the changes.
Things like following was easier to spot when reviewing DT syncs:
- A property that U-Boot depends on gets removed, as in [1].
That seems to be due to DT bindings compliance check where DT bindings are the ABI. Although it is unfortunate due to dependency on legacy DT, now we have the same dtbs_check in U-Boot too:
$ make <target>_defconfig $ make -j`nproc` dtbs_check
This shall keep U-Boot in compliance with DT bindings and help avoid such dependencies.
- Some DT changes can break changes that has been made to u-boot.dtsi files, e.g. a symbol to a node is no longer available in upstream but referenced in u-boot.dtsi files (happened in this series).
Node names aren't a DT ABI so we should expect some changes there.
- Changes in DT may require a workaround in a u-boot.dtsi file.
- u-boot.dtsi contains workarounds that has not yet been upstream but can be removed in a future DT sync.
Agree, we should try to minimize modifications via u-boot.dtsi especially all the bootph* related properties should be posted upstream.
- Driver incompatibilities due to initial driver imported from vendor ended up not fully compatible with upstream linux driver / dt-binding.
Given all the above and the big jump in DT sync for Rockchip platforms, I am fine with the transition being step by step.
-Sumit
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id...
Hi Jonas,
On 3/31/24 22:28, Jonas Karlman wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
That's a patch series I warmly welcome, we've been long overdue an update of Rockchip's DTs in U-Boot.
Here's to hope we can migrate to use OF_UPSTREAM sooner rather than later and this is a very big step in that direction, so thank you.
Cheers, Quentin
Hi Jonas,
Overall this series looks good, and I'll be able to test it fro next week when I'm back near devices.
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
That's quite a lot for a single series, it can make it hard to review and test all across a number of devices.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
This I like :)
I should be able to test this on, from mem, 6 rk3399 devices once I'm back home.
Peter
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
-- 2.43.2
Hi Jonas,
On 2024/4/1 04:28, Jonas Karlman wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
This patch set not able to apply after this dependent patchset update to v2,
please help to send a new version.
Thanks,
- Kever
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
Hi Kever,
On 2024-04-23 13:27, Kever Yang wrote:
Hi Jonas,
On 2024/4/1 04:28, Jonas Karlman wrote:
This series adds support for new clocks used in linux v6.8 device trees, enables use of FIT signature check for checksum validation and fixes loading FIT from SD-card when loading FIT from eMMC fails.
After this series it should be possible to move RK3399 boards to use OF_UPSTREAM in a future patch once dts/upstream move to a v6.8+ tag.
I have runtime tested this series on following devices:
- 96boards Rock960
- Khadas Edge Captain
- Pine64 PineBook Pro
- Pine64 RockPro64
- Radxa ROCK 4C+
- Radxa ROCK 4SE
- Radxa ROCK Pi 4A
- Radxa ROCK Pi 4B+
This series depends on the following series:
- Enable booting from SPI flash on ROCK Pi 4 [1]
- rockchip: spl: Cache boot source id for later use [2]
This patch set not able to apply after this dependent patchset update to v2,
please help to send a new version.
Thanks, I will try to split this series in two parts and send a v2 in a day or two.
First part will focus on patches up to and including "rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC". And second part will focus on updating DTs from v5.x to v6.8, and any pre-requirement for doing so.
Will also send a "third" part that moves the recently updated SoCs to OF_UPSTREAM, i.e. rk3308, rk3328, rk3399, rk356x and possible rk3588.
Regards, Jonas
Thanks,
- Kever
A copy of this series and all its depends can be found at [3]
[1] https://patchwork.ozlabs.org/cover/1912469/ [2] https://patchwork.ozlabs.org/cover/1915071/ [3] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3399-dt-sync-v1
Jonas Karlman (31): rockchip: rk3399-gru: Fix max SPL size on bob and kevin rockchip: rk3399-ficus: Enable TPL and use common bss and stack addr rockchip: rk3399: Sort imply statements alphabetically rockchip: rk3399: Enable ARMv8 crypto and FIT checksum validation rockchip: rk3399: Enable random generator on all boards rockchip: rk3399: Imply support for GbE PHY rockchip: rk3399: Enable DT overlay support on all boards rockchip: rk3399: Remove use of xPL_MISC_DRIVERS options rockchip: rk3399: Add a default spl-boot-order prop rockchip: rk3399: Fix loading FIT from SD-card when booting from eMMC clk: rockchip: rk3399: Rename SCLK_DDRCLK to SCLK_DDRC clk: rockchip: rk3399: Add dummy support for ACLK_VDU clock clk: rockchip: rk3399: Add dummy support for SCLK_PCIEPHY_REF clock clk: rockchip: rk3399: Add SCLK_USB3OTGx_REF support rockchip: rk3399: Sync soc device tree from linux v6.8 rockchip: rk3399-gru: Sync device tree from linux v6.8 rockchip: rk3399-puma: Sync DT from linux v6.8 rockchip: rk3399-rock-pi-n10: Sync device tree from linux v6.8 rockchip: rk3399-eaidk-610: Sync device tree from linux v6.8 rockchip: rk3399-leez: Sync device tree from linux v6.8 rockchip: rk3399-evb: Sync device tree from linux v6.8 rockchip: rk3399-firefly: Sync device tree from linux v6.8 rockchip: rk3399-orangepi: Sync device tree from linux v6.8 rockchip: rk3399-roc-pc: Sync device tree from linux v6.8 rockchip: rk3399-nanopi-4: Sync device tree from linux v6.8 rockchip: rk3399-rock960: Sync device tree from linux v6.8 rockchip: rk3399-khadas: Sync device tree from linux v6.8 rockchip: rk3399-rock-pi-4: Sync device tree from linux v6.8 rockchip: rk3399-rockpro64: Sync device tree from linux v6.8 rockchip: rk3399-pinebook-pro: Sync device tree from linux v6.8 rockchip: rk3399-pinephone-pro: Sync device tree from linux v6.8
arch/arm/dts/rk3288-vmarc-som.dtsi | 48 +++ arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 1 - arch/arm/dts/rk3399-eaidk-610.dts | 3 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +- arch/arm/dts/rk3399-evb.dts | 3 +- arch/arm/dts/rk3399-ficus-u-boot.dtsi | 10 +- arch/arm/dts/rk3399-ficus.dts | 4 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 - arch/arm/dts/rk3399-firefly.dts | 17 +- arch/arm/dts/rk3399-gru-bob.dts | 8 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 200 +++++++++++- arch/arm/dts/rk3399-gru-kevin.dts | 3 +- arch/arm/dts/rk3399-gru-u-boot.dtsi | 34 ++- arch/arm/dts/rk3399-gru.dtsi | 52 +++- arch/arm/dts/rk3399-khadas-edge-captain.dts | 4 + arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi | 7 +- arch/arm/dts/rk3399-khadas-edge-v.dts | 4 + arch/arm/dts/rk3399-khadas-edge.dtsi | 10 +- arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 6 - arch/arm/dts/rk3399-leez-p710.dts | 8 +- arch/arm/dts/rk3399-nanopc-t4.dts | 2 +- arch/arm/dts/rk3399-nanopi-m4-2gb.dts | 55 +--- arch/arm/dts/rk3399-nanopi-m4b.dts | 2 +- arch/arm/dts/rk3399-nanopi-r4s.dts | 4 +- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 18 +- arch/arm/dts/rk3399-nanopi4.dtsi | 7 +- arch/arm/dts/rk3399-op1-opp.dtsi | 31 +- arch/arm/dts/rk3399-opp.dtsi | 6 +- arch/arm/dts/rk3399-orangepi-u-boot.dtsi | 12 + arch/arm/dts/rk3399-orangepi.dts | 12 +- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 23 +- arch/arm/dts/rk3399-pinebook-pro.dts | 24 +- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 24 +- arch/arm/dts/rk3399-pinephone-pro.dts | 147 +++++++++ arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 27 +- arch/arm/dts/rk3399-puma-haikou.dts | 42 ++- arch/arm/dts/rk3399-puma.dtsi | 17 +- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 45 +-- arch/arm/dts/rk3399-roc-pc.dtsi | 15 +- arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 20 ++ arch/arm/dts/rk3399-rock-4c-plus.dts | 1 + arch/arm/dts/rk3399-rock-4se-u-boot.dtsi | 12 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 - arch/arm/dts/rk3399-rock-pi-4.dtsi | 4 +- arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi | 7 + arch/arm/dts/rk3399-rock-pi-4c.dts | 10 + arch/arm/dts/rk3399-rock960-u-boot.dtsi | 11 +- arch/arm/dts/rk3399-rock960.dtsi | 5 +- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 22 +- arch/arm/dts/rk3399-rockpro64.dtsi | 98 +++++- arch/arm/dts/rk3399-u-boot.dtsi | 129 +++++--- arch/arm/dts/rk3399.dtsi | 289 ++++++++++++++++-- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 6 - arch/arm/dts/rk3399pro-vmarc-som.dtsi | 20 +- .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 ++ arch/arm/mach-rockchip/Kconfig | 38 ++- configs/chromebook_bob_defconfig | 6 +- configs/chromebook_kevin_defconfig | 6 +- configs/eaidk-610-rk3399_defconfig | 13 +- configs/evb-rk3399_defconfig | 10 +- configs/ficus-rk3399_defconfig | 38 +-- configs/firefly-rk3399_defconfig | 17 +- configs/khadas-edge-captain-rk3399_defconfig | 35 ++- configs/khadas-edge-rk3399_defconfig | 29 +- configs/khadas-edge-v-rk3399_defconfig | 35 ++- configs/leez-rk3399_defconfig | 13 +- configs/nanopc-t4-rk3399_defconfig | 18 +- configs/nanopi-m4-2gb-rk3399_defconfig | 22 +- configs/nanopi-m4-rk3399_defconfig | 22 +- configs/nanopi-m4b-rk3399_defconfig | 22 +- configs/nanopi-neo4-rk3399_defconfig | 22 +- configs/nanopi-r4s-rk3399_defconfig | 16 +- configs/orangepi-rk3399_defconfig | 14 +- configs/pinebook-pro-rk3399_defconfig | 13 +- configs/pinephone-pro-rk3399_defconfig | 13 +- configs/puma-rk3399_defconfig | 5 +- configs/roc-pc-mezzanine-rk3399_defconfig | 15 +- configs/roc-pc-rk3399_defconfig | 13 +- configs/rock-4c-plus-rk3399_defconfig | 27 +- configs/rock-4se-rk3399_defconfig | 28 +- configs/rock-pi-4-rk3399_defconfig | 13 +- configs/rock-pi-4c-rk3399_defconfig | 27 +- configs/rock-pi-n10-rk3399pro_defconfig | 10 +- configs/rock960-rk3399_defconfig | 18 +- configs/rockpro64-rk3399_defconfig | 16 +- drivers/clk/rockchip/clk_rk3399.c | 12 +- include/dt-bindings/clock/rk3399-cru.h | 30 +- 87 files changed, 1700 insertions(+), 531 deletions(-)
participants (7)
-
Christopher Obbard -
Dragan Simic -
Jonas Karlman -
Kever Yang -
Peter Robinson -
Quentin Schulz -
Sumit Garg