At present the cleanup() method is called on every transfer. It should only be called on failing transfers. Fix this and tidy up the error handling a little.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/tpm/tpm-uclass.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c index 1b11c93194..71d5807006 100644 --- a/drivers/tpm/tpm-uclass.c +++ b/drivers/tpm/tpm-uclass.c @@ -72,7 +72,7 @@ int tpm_xfer(struct udevice *dev, const uint8_t *sendbuf, size_t send_size, struct tpm_ops *ops = tpm_get_ops(dev); ulong start, stop; uint count, ordinal; - int ret, ret2; + int ret, ret2 = 0;

if (ops->xfer) return ops->xfer(dev, sendbuf, send_size, recvbuf, recv_size); @@ -120,9 +120,16 @@ int tpm_xfer(struct udevice *dev, const uint8_t *sendbuf, size_t send_size, } } while (ret);

- ret2 = ops->cleanup ? ops->cleanup(dev) : 0; + if (ret) { + if (ops->cleanup) { + ret2 = ops->cleanup(dev); + if (ret2) + return log_msg_ret("cleanup", ret2); + } + return log_msg_ret("xfer", ret); + }

- return ret2 ? ret2 : ret; + return 0; }

UCLASS_DRIVER(tpm) = {

Add a means to avoid configuring a device when needed. Add an explanation of why this is useful to the binding file.

Signed-off-by: Simon Glass sjg@chromium.org ---

doc/device-tree-bindings/pci/x86-pci.txt | 24 ++++++++++++++++++++++++ drivers/pci/pci-uclass.c | 2 ++ 2 files changed, 26 insertions(+)

diff --git a/doc/device-tree-bindings/pci/x86-pci.txt b/doc/device-tree-bindings/pci/x86-pci.txt index 3aa5bd9a46..62b29a4e36 100644 --- a/doc/device-tree-bindings/pci/x86-pci.txt +++ b/doc/device-tree-bindings/pci/x86-pci.txt @@ -10,6 +10,17 @@ Optional properties: configuration in TPL/SPL to reduce code size and boot time, since these phases only know about a small subset of PCI devices.

+For PCI devices the following optional property is available: + +- pci,no-autoconfig : Don't automatically configure this PCI device at all. + This is used when the device is statically configured and must maintain + this same config throughout the boot process. An example is a serial + UART being used to debug PCI configuration, since reconfiguring it stops + the UART from working until the driver is re-probed, and this can cause + output to be lost. This should not generally be used in production code, + although it is often harmless. + + Example:

pci { @@ -21,4 +32,17 @@ pci { 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000 0x01000000 0x0 0x1000 0x1000 0 0xefff>; u-boot,skip-auto-config-until-reloc; + + + serial: serial@18,2 { + reg = <0x0200c210 0 0 0 0>; + u-boot,dm-pre-reloc; + compatible = "intel,apl-ns16550"; + early-regs = <0xde000000 0x20>; + reg-shift = <2>; + clock-frequency = <1843200>; + current-speed = <115200>; + acpi,name = "URT3"; + pci,no-autoconfig; + }; }; diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index bb272b67a1..f5f713fdf4 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -535,6 +535,8 @@ int pci_auto_config_devices(struct udevice *bus) int ret;

debug("%s: device %s\n", __func__, dev->name); + if (dev_read_bool(dev, "pci,no-autoconfig")) + continue; ret = dm_pciauto_config_device(dev); if (ret < 0) return ret;

Some files are taken or modified from coreboot, but the files are no-longer part of the coreboot project. Fix the wording in a few places.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/coreboot/timestamp.c | 4 ++-- arch/x86/include/asm/arch-coreboot/timestamp.h | 4 ++-- arch/x86/include/asm/intel_pinctrl_defs.h | 2 -- 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index e698200d70..e8ccaf2212 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * Modified from the coreboot version */

#include <common.h> diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h index 9320afba56..85d42c02c4 100644 --- a/arch/x86/include/asm/arch-coreboot/timestamp.h +++ b/arch/x86/include/asm/arch-coreboot/timestamp.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * Taken from the coreboot version */

#ifndef __COREBOOT_TIMESTAMP_H__ diff --git a/arch/x86/include/asm/intel_pinctrl_defs.h b/arch/x86/include/asm/intel_pinctrl_defs.h index 6da06bb52b..1ea141f082 100644 --- a/arch/x86/include/asm/intel_pinctrl_defs.h +++ b/arch/x86/include/asm/intel_pinctrl_defs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This file is part of the coreboot project. - * * Copyright (C) 2015-2016 Intel Corp. * Copyright 2019 Google LLC *

With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot.

At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed.

Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration.

Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix.

Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/apollolake/p2sb.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-)

diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c index 7b5a473bbd..a3d8e094e7 100644 --- a/arch/x86/cpu/apollolake/p2sb.c +++ b/arch/x86/cpu/apollolake/p2sb.c @@ -92,27 +92,25 @@ int apl_p2sb_ofdata_to_platdata(struct udevice *dev)

#if !CONFIG_IS_ENABLED(OF_PLATDATA) int ret; + u32 base[2];

+ ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base)); + if (ret) + return log_msg_ret("Missing/short early-regs", ret); + plat->mmio_base = base[0]; + /* TPL sets up the initial BAR */ if (spl_phase() == PHASE_TPL) { - u32 base[2]; - - /* TPL sets up the initial BAR */ - ret = dev_read_u32_array(dev, "early-regs", base, - ARRAY_SIZE(base)); - if (ret) - return log_msg_ret("Missing/short early-regs", ret); - plat->mmio_base = base[0]; plat->bdf = pci_get_devfn(dev); if (plat->bdf < 0) return log_msg_ret("Cannot get p2sb PCI address", - plat->bdf); + plat->bdf); } + upriv->mmio_base = plat->mmio_base; #else plat->mmio_base = plat->dtplat.early_regs[0]; plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]); -#endif upriv->mmio_base = plat->mmio_base; - debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base); +#endif

return 0; } @@ -121,17 +119,8 @@ static int apl_p2sb_probe(struct udevice *dev) { if (spl_phase() == PHASE_TPL) return apl_p2sb_early_init(dev); - else { - struct p2sb_platdata *plat = dev_get_platdata(dev); - - plat->mmio_base = dev_read_addr_pci(dev); - /* Don't set BDF since it should not be used */ - if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE) - return -EINVAL; - - if (spl_phase() == PHASE_SPL) - return apl_p2sb_spl_init(dev); - } + else if (spl_phase() == PHASE_SPL) + return apl_p2sb_spl_init(dev);

return 0; }

Add a sandbox test for the basic ACPI functionality we have so far.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/sandbox/dts/test.dts | 4 +++ include/dm/uclass-id.h | 1 + test/dm/Makefile | 1 + test/dm/acpi.c | 55 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+) create mode 100644 test/dm/acpi.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 1a8a50e27d..34dc7fda98 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -206,6 +206,10 @@ compatible = "denx,u-boot-devres-test"; };

+ acpi-test { + compatible = "denx,u-boot-acpi-test"; + }; + clocks { clk_fixed: clk-fixed { compatible = "fixed-clock"; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index c9f49df3f2..f49ea5d852 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -20,6 +20,7 @@ enum uclass_id { UCLASS_TEST_PROBE, UCLASS_TEST_DUMMY, UCLASS_TEST_DEVRES, + UCLASS_TEST_ACPI, UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ UCLASS_I2C_EMUL_PARENT, /* parent for I2C device emulators */ diff --git a/test/dm/Makefile b/test/dm/Makefile index 85cc0f7fb8..fab157b5d8 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_UT_DM) += test-uclass.o # subsystem you must add sandbox tests here. obj-$(CONFIG_UT_DM) += core.o ifneq ($(CONFIG_SANDBOX),) +obj-$(CONFIG_ACPIGEN) += acpi.o obj-$(CONFIG_SOUND) += audio.o obj-$(CONFIG_BLK) += blk.o obj-$(CONFIG_BOARD) += board.o diff --git a/test/dm/acpi.c b/test/dm/acpi.c new file mode 100644 index 0000000000..e3519d4689 --- /dev/null +++ b/test/dm/acpi.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for ACPI table generation + * + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ + +#include <common.h> +#include <dm.h> +#include <dm/acpi.h> +#include <dm/test.h> +#include <test/ut.h> + +#define ACPI_TEST_DEV_NAME "ABCD" + +static int testacpi_get_name(const struct udevice *dev, char *out_name) +{ + return acpi_return_name(out_name, ACPI_TEST_DEV_NAME); +} + +struct acpi_ops testacpi_ops = { + .get_name = testacpi_get_name, +}; + +static const struct udevice_id testacpi_ids[] = { + { .compatible = "denx,u-boot-acpi-test" }, + { } +}; + +U_BOOT_DRIVER(testacpi_drv) = { + .name = "testacpi_drv", + .of_match = testacpi_ids, + .id = UCLASS_TEST_ACPI, + acpi_ops_ptr(&testacpi_ops) +}; + +UCLASS_DRIVER(testacpi) = { + .name = "testacpi", + .id = UCLASS_TEST_ACPI, +}; + +/* Test ACPI get_name() */ +static int dm_test_acpi_get_name(struct unit_test_state *uts) +{ + char name[ACPI_NAME_MAX]; + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_TEST_ACPI, &dev)); + ut_assertok(acpi_get_name(dev, name)); + ut_asserteq_str(ACPI_TEST_DEV_NAME, name); + + return 0; +} +DM_TEST(dm_test_acpi_get_name, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

This file is potentially useful to other architectures saddled with ACPI so move it into a common location.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/baytrail/acpi.c | 2 +- arch/x86/cpu/cpu.c | 2 +- arch/x86/cpu/quark/acpi.c | 2 +- arch/x86/cpu/tangier/acpi.c | 2 +- arch/x86/include/asm/acpi_table.h | 376 ---------------------------- arch/x86/lib/acpi.c | 2 +- arch/x86/lib/acpi_s3.c | 2 +- arch/x86/lib/acpi_table.c | 2 +- arch/x86/lib/tables.c | 2 +- arch/x86/lib/zimage.c | 2 +- include/acpi_table.h | 394 ++++++++++++++++++++++++++++++ lib/efi_loader/efi_acpi.c | 2 +- 12 files changed, 404 insertions(+), 386 deletions(-) create mode 100644 include/acpi_table.h

diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index f44228e693..856af95556 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -8,7 +8,7 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/io.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index d82305303a..3891de088f 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -27,7 +27,7 @@ #include <malloc.h> #include <syscon.h> #include <asm/acpi.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/control_regs.h> #include <asm/coreboot_tables.h> #include <asm/cpu.h> diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 7b6fc2f4a5..dd562a6e2f 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -4,7 +4,7 @@ */

#include <common.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 8b128138b0..768c4dcbc8 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -9,7 +9,7 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 7588913f93..22d54057f1 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -9,382 +9,6 @@ #ifndef __ASM_ACPI_TABLE_H__ #define __ASM_ACPI_TABLE_H__

-#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ -#define OEM_ID "U-BOOT" /* U-Boot */ -#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ -#define ASLC_ID "INTL" /* Intel ASL Compiler */ - -#define ACPI_RSDP_REV_ACPI_1_0 0 -#define ACPI_RSDP_REV_ACPI_2_0 2 - -/* - * RSDP (Root System Description Pointer) - * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum - */ -struct acpi_rsdp { - char signature[8]; /* RSDP signature */ - u8 checksum; /* Checksum of the first 20 bytes */ - char oem_id[6]; /* OEM ID */ - u8 revision; /* 0 for ACPI 1.0, others 2 */ - u32 rsdt_address; /* Physical address of RSDT (32 bits) */ - u32 length; /* Total RSDP length (incl. extended part) */ - u64 xsdt_address; /* Physical address of XSDT (64 bits) */ - u8 ext_checksum; /* Checksum of the whole table */ - u8 reserved[3]; -}; - -/* Generic ACPI header, provided by (almost) all tables */ -struct __packed acpi_table_header { - char signature[4]; /* ACPI signature (4 ASCII characters) */ - u32 length; /* Table length in bytes (incl. header) */ - u8 revision; /* Table version (not ACPI version!) */ - volatile u8 checksum; /* To make sum of entire table == 0 */ - char oem_id[6]; /* OEM identification */ - char oem_table_id[8]; /* OEM table identification */ - u32 oem_revision; /* OEM revision number */ - char aslc_id[4]; /* ASL compiler vendor ID */ - u32 aslc_revision; /* ASL compiler revision number */ -}; - -/* A maximum number of 32 ACPI tables ought to be enough for now */ -#define MAX_ACPI_TABLES 32 - -/* RSDT (Root System Description Table) */ -struct acpi_rsdt { - struct acpi_table_header header; - u32 entry[MAX_ACPI_TABLES]; -}; - -/* XSDT (Extended System Description Table) */ -struct acpi_xsdt { - struct acpi_table_header header; - u64 entry[MAX_ACPI_TABLES]; -}; - -/* FADT Preferred Power Management Profile */ -enum acpi_pm_profile { - ACPI_PM_UNSPECIFIED = 0, - ACPI_PM_DESKTOP, - ACPI_PM_MOBILE, - ACPI_PM_WORKSTATION, - ACPI_PM_ENTERPRISE_SERVER, - ACPI_PM_SOHO_SERVER, - ACPI_PM_APPLIANCE_PC, - ACPI_PM_PERFORMANCE_SERVER, - ACPI_PM_TABLET -}; - -/* FADT flags for p_lvl2_lat and p_lvl3_lat */ -#define ACPI_FADT_C2_NOT_SUPPORTED 101 -#define ACPI_FADT_C3_NOT_SUPPORTED 1001 - -/* FADT Boot Architecture Flags */ -#define ACPI_FADT_LEGACY_FREE 0x00 -#define ACPI_FADT_LEGACY_DEVICES (1 << 0) -#define ACPI_FADT_8042 (1 << 1) -#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) -#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) -#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) - -/* FADT Feature Flags */ -#define ACPI_FADT_WBINVD (1 << 0) -#define ACPI_FADT_WBINVD_FLUSH (1 << 1) -#define ACPI_FADT_C1_SUPPORTED (1 << 2) -#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) -#define ACPI_FADT_POWER_BUTTON (1 << 4) -#define ACPI_FADT_SLEEP_BUTTON (1 << 5) -#define ACPI_FADT_FIXED_RTC (1 << 6) -#define ACPI_FADT_S4_RTC_WAKE (1 << 7) -#define ACPI_FADT_32BIT_TIMER (1 << 8) -#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) -#define ACPI_FADT_RESET_REGISTER (1 << 10) -#define ACPI_FADT_SEALED_CASE (1 << 11) -#define ACPI_FADT_HEADLESS (1 << 12) -#define ACPI_FADT_SLEEP_TYPE (1 << 13) -#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) -#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) -#define ACPI_FADT_S4_RTC_VALID (1 << 16) -#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) -#define ACPI_FADT_APIC_CLUSTER (1 << 18) -#define ACPI_FADT_APIC_PHYSICAL (1 << 19) -#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) -#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) - -enum acpi_address_space_type { - ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ - ACPI_ADDRESS_SPACE_IO, /* System I/O */ - ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ - ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ - ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ - ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ - ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ -}; - -enum acpi_address_space_size { - ACPI_ACCESS_SIZE_UNDEFINED = 0, - ACPI_ACCESS_SIZE_BYTE_ACCESS, - ACPI_ACCESS_SIZE_WORD_ACCESS, - ACPI_ACCESS_SIZE_DWORD_ACCESS, - ACPI_ACCESS_SIZE_QWORD_ACCESS -}; - -struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ -}; - -/* FADT (Fixed ACPI Description Table) */ -struct __packed acpi_fadt { - struct acpi_table_header header; - u32 firmware_ctrl; - u32 dsdt; - u8 res1; - u8 preferred_pm_profile; - u16 sci_int; - u32 smi_cmd; - u8 acpi_enable; - u8 acpi_disable; - u8 s4bios_req; - u8 pstate_cnt; - u32 pm1a_evt_blk; - u32 pm1b_evt_blk; - u32 pm1a_cnt_blk; - u32 pm1b_cnt_blk; - u32 pm2_cnt_blk; - u32 pm_tmr_blk; - u32 gpe0_blk; - u32 gpe1_blk; - u8 pm1_evt_len; - u8 pm1_cnt_len; - u8 pm2_cnt_len; - u8 pm_tmr_len; - u8 gpe0_blk_len; - u8 gpe1_blk_len; - u8 gpe1_base; - u8 cst_cnt; - u16 p_lvl2_lat; - u16 p_lvl3_lat; - u16 flush_size; - u16 flush_stride; - u8 duty_offset; - u8 duty_width; - u8 day_alrm; - u8 mon_alrm; - u8 century; - u16 iapc_boot_arch; - u8 res2; - u32 flags; - struct acpi_gen_regaddr reset_reg; - u8 reset_value; - u16 arm_boot_arch; - u8 minor_revision; - u32 x_firmware_ctl_l; - u32 x_firmware_ctl_h; - u32 x_dsdt_l; - u32 x_dsdt_h; - struct acpi_gen_regaddr x_pm1a_evt_blk; - struct acpi_gen_regaddr x_pm1b_evt_blk; - struct acpi_gen_regaddr x_pm1a_cnt_blk; - struct acpi_gen_regaddr x_pm1b_cnt_blk; - struct acpi_gen_regaddr x_pm2_cnt_blk; - struct acpi_gen_regaddr x_pm_tmr_blk; - struct acpi_gen_regaddr x_gpe0_blk; - struct acpi_gen_regaddr x_gpe1_blk; -}; - -/* FACS flags */ -#define ACPI_FACS_S4BIOS_F (1 << 0) -#define ACPI_FACS_64BIT_WAKE_F (1 << 1) - -/* FACS (Firmware ACPI Control Structure) */ -struct acpi_facs { - char signature[4]; /* "FACS" */ - u32 length; /* Length in bytes (>= 64) */ - u32 hardware_signature; /* Hardware signature */ - u32 firmware_waking_vector; /* Firmware waking vector */ - u32 global_lock; /* Global lock */ - u32 flags; /* FACS flags */ - u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ - u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* Version 2 */ - u8 res1[3]; - u32 ospm_flags; /* OSPM enabled flags */ - u8 res2[24]; -}; - -/* MADT flags */ -#define ACPI_MADT_PCAT_COMPAT (1 << 0) - -/* MADT (Multiple APIC Description Table) */ -struct acpi_madt { - struct acpi_table_header header; - u32 lapic_addr; /* Local APIC address */ - u32 flags; /* Multiple APIC flags */ -}; - -/* MADT: APIC Structure Type*/ -enum acpi_apic_types { - ACPI_APIC_LAPIC = 0, /* Processor local APIC */ - ACPI_APIC_IOAPIC, /* I/O APIC */ - ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ - ACPI_APIC_NMI_SRC, /* NMI source */ - ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ - ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ - ACPI_APIC_IOSAPIC, /* I/O SAPIC */ - ACPI_APIC_LSAPIC, /* Local SAPIC */ - ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ - ACPI_APIC_LX2APIC, /* Processor local x2APIC */ - ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ -}; - -/* MADT: Processor Local APIC Structure */ - -#define LOCAL_APIC_FLAG_ENABLED (1 << 0) - -struct acpi_madt_lapic { - u8 type; /* Type (0) */ - u8 length; /* Length in bytes (8) */ - u8 processor_id; /* ACPI processor ID */ - u8 apic_id; /* Local APIC ID */ - u32 flags; /* Local APIC flags */ -}; - -/* MADT: I/O APIC Structure */ -struct acpi_madt_ioapic { - u8 type; /* Type (1) */ - u8 length; /* Length in bytes (12) */ - u8 ioapic_id; /* I/O APIC ID */ - u8 reserved; - u32 ioapic_addr; /* I/O APIC address */ - u32 gsi_base; /* Global system interrupt base */ -}; - -/* MADT: Interrupt Source Override Structure */ -struct __packed acpi_madt_irqoverride { - u8 type; /* Type (2) */ - u8 length; /* Length in bytes (10) */ - u8 bus; /* ISA (0) */ - u8 source; /* Bus-relative int. source (IRQ) */ - u32 gsirq; /* Global system interrupt */ - u16 flags; /* MPS INTI flags */ -}; - -/* MADT: Local APIC NMI Structure */ -struct __packed acpi_madt_lapic_nmi { - u8 type; /* Type (4) */ - u8 length; /* Length in bytes (6) */ - u8 processor_id; /* ACPI processor ID */ - u16 flags; /* MPS INTI flags */ - u8 lint; /* Local APIC LINT# */ -}; - -/* MCFG (PCI Express MMIO config space BAR description table) */ -struct acpi_mcfg { - struct acpi_table_header header; - u8 reserved[8]; -}; - -struct acpi_mcfg_mmconfig { - u32 base_address_l; - u32 base_address_h; - u16 pci_segment_group_number; - u8 start_bus_number; - u8 end_bus_number; - u8 reserved[4]; -}; - -/* PM1_CNT bit defines */ -#define PM1_CNT_SCI_EN (1 << 0) - -/* ACPI global NVS structure */ -struct acpi_global_nvs; - -/* CSRT (Core System Resource Table) */ -struct acpi_csrt { - struct acpi_table_header header; -}; - -struct acpi_csrt_group { - u32 length; - u32 vendor_id; - u32 subvendor_id; - u16 device_id; - u16 subdevice_id; - u16 revision; - u16 reserved; - u32 shared_info_length; -}; - -struct acpi_csrt_shared_info { - u16 major_version; - u16 minor_version; - u32 mmio_base_low; - u32 mmio_base_high; - u32 gsi_interrupt; - u8 interrupt_polarity; - u8 interrupt_mode; - u8 num_channels; - u8 dma_address_width; - u16 base_request_line; - u16 num_handshake_signals; - u32 max_block_size; -}; - -/* DBG2 definitions are partially used for SPCR interface_type */ - -/* Types for port_type field */ - -#define ACPI_DBG2_SERIAL_PORT 0x8000 -#define ACPI_DBG2_1394_PORT 0x8001 -#define ACPI_DBG2_USB_PORT 0x8002 -#define ACPI_DBG2_NET_PORT 0x8003 - -/* Subtypes for port_subtype field */ - -#define ACPI_DBG2_16550_COMPATIBLE 0x0000 -#define ACPI_DBG2_16550_SUBSET 0x0001 -#define ACPI_DBG2_ARM_PL011 0x0003 -#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D -#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E -#define ACPI_DBG2_ARM_DCC 0x000F -#define ACPI_DBG2_BCM2835 0x0010 - -#define ACPI_DBG2_1394_STANDARD 0x0000 - -#define ACPI_DBG2_USB_XHCI 0x0000 -#define ACPI_DBG2_USB_EHCI 0x0001 - -#define ACPI_DBG2_UNKNOWN 0x00FF - -/* SPCR (Serial Port Console Redirection table) */ -struct __packed acpi_spcr { - struct acpi_table_header header; - u8 interface_type; - u8 reserved[3]; - struct acpi_gen_regaddr serial_port; - u8 interrupt_type; - u8 pc_interrupt; - u32 interrupt; /* Global system interrupt */ - u8 baud_rate; - u8 parity; - u8 stop_bits; - u8 flow_control; - u8 terminal_type; - u8 reserved1; - u16 pci_device_id; /* Must be 0xffff if not PCI device */ - u16 pci_vendor_id; /* Must be 0xffff if not PCI device */ - u8 pci_bus; - u8 pci_device; - u8 pci_function; - u32 pci_flags; - u8 pci_segment; - u32 reserved2; -}; - /* These can be used by the target port */

void acpi_fill_header(struct acpi_table_header *header, char *signature); diff --git a/arch/x86/lib/acpi.c b/arch/x86/lib/acpi.c index cba9c24dd4..2f4cd736f7 100644 --- a/arch/x86/lib/acpi.c +++ b/arch/x86/lib/acpi.c @@ -4,7 +4,7 @@ */

#include <common.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/io.h> #include <asm/tables.h>

diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 197636c4b5..74a78fd193 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -6,7 +6,7 @@ #include <common.h> #include <acpi_s3.h> #include <asm/acpi.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/post.h> #include <linux/linkage.h>

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 0d69cf271f..71913b6f65 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -13,7 +13,7 @@ #include <serial.h> #include <version.h> #include <asm/acpi/global_nvs.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/ioapic.h> #include <asm/lapic.h> #include <asm/mpspec.h> diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 99f1429363..e359828c8e 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -8,7 +8,7 @@ #include <asm/sfi.h> #include <asm/mpspec.h> #include <asm/tables.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/coreboot_tables.h>

/** diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 9b5e767ccc..180b18349d 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -16,7 +16,7 @@ #include <env.h> #include <irq_func.h> #include <malloc.h> -#include <asm/acpi_table.h> +#include <acpi_table.h> #include <asm/io.h> #include <asm/ptrace.h> #include <asm/zimage.h> diff --git a/include/acpi_table.h b/include/acpi_table.h new file mode 100644 index 0000000000..b4404a632c --- /dev/null +++ b/include/acpi_table.h @@ -0,0 +1,394 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Helpers for ACPI table generation + * + * Based on acpi.c from coreboot + * + * Copyright 2019 Google LLC + * + * Copyright (C) 2015, Saket Sinha saket.sinha89@gmail.com + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + */ + +#ifndef __ACPI_TABLE_H__ +#define __ACPI_TABLE_H__ + +#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ +#define OEM_ID "U-BOOT" /* U-Boot */ +#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ +#define ASLC_ID "INTL" /* Intel ASL Compiler */ + +#define ACPI_RSDP_REV_ACPI_1_0 0 +#define ACPI_RSDP_REV_ACPI_2_0 2 + +/* + * RSDP (Root System Description Pointer) + * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum + */ +struct acpi_rsdp { + char signature[8]; /* RSDP signature */ + u8 checksum; /* Checksum of the first 20 bytes */ + char oem_id[6]; /* OEM ID */ + u8 revision; /* 0 for ACPI 1.0, others 2 */ + u32 rsdt_address; /* Physical address of RSDT (32 bits) */ + u32 length; /* Total RSDP length (incl. extended part) */ + u64 xsdt_address; /* Physical address of XSDT (64 bits) */ + u8 ext_checksum; /* Checksum of the whole table */ + u8 reserved[3]; +}; + +/* Generic ACPI header, provided by (almost) all tables */ +struct __packed acpi_table_header { + char signature[4]; /* ACPI signature (4 ASCII characters) */ + u32 length; /* Table length in bytes (incl. header) */ + u8 revision; /* Table version (not ACPI version!) */ + volatile u8 checksum; /* To make sum of entire table == 0 */ + char oem_id[6]; /* OEM identification */ + char oem_table_id[8]; /* OEM table identification */ + u32 oem_revision; /* OEM revision number */ + char aslc_id[4]; /* ASL compiler vendor ID */ + u32 aslc_revision; /* ASL compiler revision number */ +}; + +/* A maximum number of 32 ACPI tables ought to be enough for now */ +#define MAX_ACPI_TABLES 32 + +/* RSDT (Root System Description Table) */ +struct acpi_rsdt { + struct acpi_table_header header; + u32 entry[MAX_ACPI_TABLES]; +}; + +/* XSDT (Extended System Description Table) */ +struct acpi_xsdt { + struct acpi_table_header header; + u64 entry[MAX_ACPI_TABLES]; +}; + +/* FADT Preferred Power Management Profile */ +enum acpi_pm_profile { + ACPI_PM_UNSPECIFIED = 0, + ACPI_PM_DESKTOP, + ACPI_PM_MOBILE, + ACPI_PM_WORKSTATION, + ACPI_PM_ENTERPRISE_SERVER, + ACPI_PM_SOHO_SERVER, + ACPI_PM_APPLIANCE_PC, + ACPI_PM_PERFORMANCE_SERVER, + ACPI_PM_TABLET +}; + +/* FADT flags for p_lvl2_lat and p_lvl3_lat */ +#define ACPI_FADT_C2_NOT_SUPPORTED 101 +#define ACPI_FADT_C3_NOT_SUPPORTED 1001 + +/* FADT Boot Architecture Flags */ +#define ACPI_FADT_LEGACY_FREE 0x00 +#define ACPI_FADT_LEGACY_DEVICES BIT(0) +#define ACPI_FADT_8042 BIT(1) +#define ACPI_FADT_VGA_NOT_PRESENT BIT(2) +#define ACPI_FADT_MSI_NOT_SUPPORTED BIT(3) +#define ACPI_FADT_NO_PCIE_ASPM_CONTROL BIT(4) + +/* FADT Feature Flags */ +#define ACPI_FADT_WBINVD BIT(0) +#define ACPI_FADT_WBINVD_FLUSH BIT(1) +#define ACPI_FADT_C1_SUPPORTED BIT(2) +#define ACPI_FADT_C2_MP_SUPPORTED BIT(3) +#define ACPI_FADT_POWER_BUTTON BIT(4) +#define ACPI_FADT_SLEEP_BUTTON BIT(5) +#define ACPI_FADT_FIXED_RTC BIT(6) +#define ACPI_FADT_S4_RTC_WAKE BIT(7) +#define ACPI_FADT_32BIT_TIMER BIT(8) +#define ACPI_FADT_DOCKING_SUPPORTED BIT(9) +#define ACPI_FADT_RESET_REGISTER BIT(10) +#define ACPI_FADT_SEALED_CASE BIT(11) +#define ACPI_FADT_HEADLESS BIT(12) +#define ACPI_FADT_SLEEP_TYPE BIT(13) +#define ACPI_FADT_PCI_EXPRESS_WAKE BIT(14) +#define ACPI_FADT_PLATFORM_CLOCK BIT(15) +#define ACPI_FADT_S4_RTC_VALID BIT(16) +#define ACPI_FADT_REMOTE_POWER_ON BIT(17) +#define ACPI_FADT_APIC_CLUSTER BIT(18) +#define ACPI_FADT_APIC_PHYSICAL BIT(19) +#define ACPI_FADT_HW_REDUCED_ACPI BIT(20) +#define ACPI_FADT_LOW_PWR_IDLE_S0 BIT(21) + +enum acpi_address_space_type { + ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */ + ACPI_ADDRESS_SPACE_IO, /* System I/O */ + ACPI_ADDRESS_SPACE_PCI, /* PCI config space */ + ACPI_ADDRESS_SPACE_EC, /* Embedded controller */ + ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */ + ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */ + ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ +}; + +enum acpi_address_space_size { + ACPI_ACCESS_SIZE_UNDEFINED = 0, + ACPI_ACCESS_SIZE_BYTE_ACCESS, + ACPI_ACCESS_SIZE_WORD_ACCESS, + ACPI_ACCESS_SIZE_DWORD_ACCESS, + ACPI_ACCESS_SIZE_QWORD_ACCESS +}; + +struct acpi_gen_regaddr { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ +}; + +/* FADT (Fixed ACPI Description Table) */ +struct __packed acpi_fadt { + struct acpi_table_header header; + u32 firmware_ctrl; + u32 dsdt; + u8 res1; + u8 preferred_pm_profile; + u16 sci_int; + u32 smi_cmd; + u8 acpi_enable; + u8 acpi_disable; + u8 s4bios_req; + u8 pstate_cnt; + u32 pm1a_evt_blk; + u32 pm1b_evt_blk; + u32 pm1a_cnt_blk; + u32 pm1b_cnt_blk; + u32 pm2_cnt_blk; + u32 pm_tmr_blk; + u32 gpe0_blk; + u32 gpe1_blk; + u8 pm1_evt_len; + u8 pm1_cnt_len; + u8 pm2_cnt_len; + u8 pm_tmr_len; + u8 gpe0_blk_len; + u8 gpe1_blk_len; + u8 gpe1_base; + u8 cst_cnt; + u16 p_lvl2_lat; + u16 p_lvl3_lat; + u16 flush_size; + u16 flush_stride; + u8 duty_offset; + u8 duty_width; + u8 day_alrm; + u8 mon_alrm; + u8 century; + u16 iapc_boot_arch; + u8 res2; + u32 flags; + struct acpi_gen_regaddr reset_reg; + u8 reset_value; + u16 arm_boot_arch; + u8 minor_revision; + u32 x_firmware_ctl_l; + u32 x_firmware_ctl_h; + u32 x_dsdt_l; + u32 x_dsdt_h; + struct acpi_gen_regaddr x_pm1a_evt_blk; + struct acpi_gen_regaddr x_pm1b_evt_blk; + struct acpi_gen_regaddr x_pm1a_cnt_blk; + struct acpi_gen_regaddr x_pm1b_cnt_blk; + struct acpi_gen_regaddr x_pm2_cnt_blk; + struct acpi_gen_regaddr x_pm_tmr_blk; + struct acpi_gen_regaddr x_gpe0_blk; + struct acpi_gen_regaddr x_gpe1_blk; +}; + +/* FACS flags */ +#define ACPI_FACS_S4BIOS_F BIT(0) +#define ACPI_FACS_64BIT_WAKE_F BIT(1) + +/* FACS (Firmware ACPI Control Structure) */ +struct acpi_facs { + char signature[4]; /* "FACS" */ + u32 length; /* Length in bytes (>= 64) */ + u32 hardware_signature; /* Hardware signature */ + u32 firmware_waking_vector; /* Firmware waking vector */ + u32 global_lock; /* Global lock */ + u32 flags; /* FACS flags */ + u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ + u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ + u8 version; /* Version 2 */ + u8 res1[3]; + u32 ospm_flags; /* OSPM enabled flags */ + u8 res2[24]; +}; + +/* MADT flags */ +#define ACPI_MADT_PCAT_COMPAT BIT(0) + +/* MADT (Multiple APIC Description Table) */ +struct acpi_madt { + struct acpi_table_header header; + u32 lapic_addr; /* Local APIC address */ + u32 flags; /* Multiple APIC flags */ +}; + +/* MADT: APIC Structure Type*/ +enum acpi_apic_types { + ACPI_APIC_LAPIC = 0, /* Processor local APIC */ + ACPI_APIC_IOAPIC, /* I/O APIC */ + ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ + ACPI_APIC_NMI_SRC, /* NMI source */ + ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ + ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ + ACPI_APIC_IOSAPIC, /* I/O SAPIC */ + ACPI_APIC_LSAPIC, /* Local SAPIC */ + ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ + ACPI_APIC_LX2APIC, /* Processor local x2APIC */ + ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ +}; + +/* MADT: Processor Local APIC Structure */ + +#define LOCAL_APIC_FLAG_ENABLED BIT(0) + +struct acpi_madt_lapic { + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (8) */ + u8 processor_id; /* ACPI processor ID */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Local APIC flags */ +}; + +/* MADT: I/O APIC Structure */ +struct acpi_madt_ioapic { + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (12) */ + u8 ioapic_id; /* I/O APIC ID */ + u8 reserved; + u32 ioapic_addr; /* I/O APIC address */ + u32 gsi_base; /* Global system interrupt base */ +}; + +/* MADT: Interrupt Source Override Structure */ +struct __packed acpi_madt_irqoverride { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (10) */ + u8 bus; /* ISA (0) */ + u8 source; /* Bus-relative int. source (IRQ) */ + u32 gsirq; /* Global system interrupt */ + u16 flags; /* MPS INTI flags */ +}; + +/* MADT: Local APIC NMI Structure */ +struct __packed acpi_madt_lapic_nmi { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (6) */ + u8 processor_id; /* ACPI processor ID */ + u16 flags; /* MPS INTI flags */ + u8 lint; /* Local APIC LINT# */ +}; + +/* MCFG (PCI Express MMIO config space BAR description table) */ +struct acpi_mcfg { + struct acpi_table_header header; + u8 reserved[8]; +}; + +struct acpi_mcfg_mmconfig { + u32 base_address_l; + u32 base_address_h; + u16 pci_segment_group_number; + u8 start_bus_number; + u8 end_bus_number; + u8 reserved[4]; +}; + +/* PM1_CNT bit defines */ +#define PM1_CNT_SCI_EN BIT(0) + +/* ACPI global NVS structure */ +struct acpi_global_nvs; + +/* CSRT (Core System Resource Table) */ +struct acpi_csrt { + struct acpi_table_header header; +}; + +struct acpi_csrt_group { + u32 length; + u32 vendor_id; + u32 subvendor_id; + u16 device_id; + u16 subdevice_id; + u16 revision; + u16 reserved; + u32 shared_info_length; +}; + +struct acpi_csrt_shared_info { + u16 major_version; + u16 minor_version; + u32 mmio_base_low; + u32 mmio_base_high; + u32 gsi_interrupt; + u8 interrupt_polarity; + u8 interrupt_mode; + u8 num_channels; + u8 dma_address_width; + u16 base_request_line; + u16 num_handshake_signals; + u32 max_block_size; +}; + +/* DBG2 definitions are partially used for SPCR interface_type */ + +/* Types for port_type field */ + +#define ACPI_DBG2_SERIAL_PORT 0x8000 +#define ACPI_DBG2_1394_PORT 0x8001 +#define ACPI_DBG2_USB_PORT 0x8002 +#define ACPI_DBG2_NET_PORT 0x8003 + +/* Subtypes for port_subtype field */ + +#define ACPI_DBG2_16550_COMPATIBLE 0x0000 +#define ACPI_DBG2_16550_SUBSET 0x0001 +#define ACPI_DBG2_ARM_PL011 0x0003 +#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D +#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E +#define ACPI_DBG2_ARM_DCC 0x000F +#define ACPI_DBG2_BCM2835 0x0010 + +#define ACPI_DBG2_1394_STANDARD 0x0000 + +#define ACPI_DBG2_USB_XHCI 0x0000 +#define ACPI_DBG2_USB_EHCI 0x0001 + +#define ACPI_DBG2_UNKNOWN 0x00FF + +/* SPCR (Serial Port Console Redirection table) */ +struct __packed acpi_spcr { + struct acpi_table_header header; + u8 interface_type; + u8 reserved[3]; + struct acpi_gen_regaddr serial_port; + u8 interrupt_type; + u8 pc_interrupt; + u32 interrupt; /* Global system interrupt */ + u8 baud_rate; + u8 parity; + u8 stop_bits; + u8 flow_control; + u8 terminal_type; + u8 reserved1; + u16 pci_device_id; /* Must be 0xffff if not PCI device */ + u16 pci_vendor_id; /* Must be 0xffff if not PCI device */ + u8 pci_bus; + u8 pci_device; + u8 pci_function; + u32 pci_flags; + u8 pci_segment; + u32 reserved2; +}; + +#include <asm/acpi_table.h> + +#endif /* __ACPI_TABLE_H__ */ diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c index a4e5e53d15..74d8f5567f 100644 --- a/lib/efi_loader/efi_acpi.c +++ b/lib/efi_loader/efi_acpi.c @@ -7,7 +7,7 @@

#include <common.h> #include <efi_loader.h> -#include <asm/acpi_table.h> +#include <acpi_table.h>

static const efi_guid_t acpi_guid = EFI_ACPI_TABLE_GUID;

The ASL compiler cannot handle C structures and the like so needs some sort of header guard around these.

We already have an __ASSEMBLY__ #define but it seems best to create a new one for ACPI since the rules may be different.

Add the check to a few files that ACPI always includes.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/acpi_table.h | 4 ++++ include/dm/acpi.h | 4 ++++ scripts/Makefile.lib | 4 ++-- 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/include/acpi_table.h b/include/acpi_table.h index b4404a632c..dd74895813 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -21,6 +21,8 @@ #define ACPI_RSDP_REV_ACPI_1_0 0 #define ACPI_RSDP_REV_ACPI_2_0 2

+#if !defined(__ACPI__) + /* * RSDP (Root System Description Pointer) * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum @@ -389,6 +391,8 @@ struct __packed acpi_spcr { u32 reserved2; };

+#endif /* !__ACPI__*/ + #include <asm/acpi_table.h>

#endif /* __ACPI_TABLE_H__ */ diff --git a/include/dm/acpi.h b/include/dm/acpi.h index 120576adc0..8d6c3fd424 100644 --- a/include/dm/acpi.h +++ b/include/dm/acpi.h @@ -22,6 +22,8 @@ /* Length of an ACPI name string including nul terminator */ #define ACPI_NAME_MAX 5

+#if !defined(__ACPI__) + /** * struct acpi_ops - ACPI operations supported by driver model */ @@ -70,4 +72,6 @@ int acpi_get_name(const struct udevice *dev, char *out_name); */ int acpi_return_name(char *out_name, const char *name);

+#endif /* __ACPI__ */ + #endif diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index c10cd83a0a..d466ef5be7 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -409,8 +409,8 @@ ASL_TMP = $(patsubst %.c,%.asl.tmp,$@)

quiet_cmd_acpi_c_asl= ASL $< cmd_acpi_c_asl= \ - $(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) \ - -o $(ASL_TMP) $< && \ + $(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -D__ACPI__ \ + -P $(UBOOTINCLUDE) -o $(ASL_TMP) $< && \ iasl -p $@ -tc $(ASL_TMP) $(if $(KBUILD_VERBOSE:1=), >/dev/null) && \ mv $(patsubst %.c,%.hex,$@) $@

Each ACPI table has its own version number. Add the version numbers in a single function so we can keep them consistent and easily see what versions are supported.

Start a new acpi_table file in a generic directory to house this function. We can move things over to this file from x86 as needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/sandbox/include/asm/acpi_table.h | 9 ++++ include/acpi_table.h | 53 ++++++++++++++++++++++++ lib/Makefile | 1 + lib/acpi/Makefile | 4 ++ lib/acpi/acpi_table.c | 59 +++++++++++++++++++++++++++ test/dm/acpi.c | 14 +++++++ 6 files changed, 140 insertions(+) create mode 100644 arch/sandbox/include/asm/acpi_table.h create mode 100644 lib/acpi/Makefile create mode 100644 lib/acpi/acpi_table.c

diff --git a/arch/sandbox/include/asm/acpi_table.h b/arch/sandbox/include/asm/acpi_table.h new file mode 100644 index 0000000000..921c7f4201 --- /dev/null +++ b/arch/sandbox/include/asm/acpi_table.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +#endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/include/acpi_table.h b/include/acpi_table.h index dd74895813..91496ac047 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -202,6 +202,18 @@ struct __packed acpi_fadt { struct acpi_gen_regaddr x_gpe1_blk; };

+/* FADT TABLE Revision values */ +#define ACPI_FADT_REV_ACPI_1_0 1 +#define ACPI_FADT_REV_ACPI_2_0 3 +#define ACPI_FADT_REV_ACPI_3_0 4 +#define ACPI_FADT_REV_ACPI_4_0 4 +#define ACPI_FADT_REV_ACPI_5_0 5 +#define ACPI_FADT_REV_ACPI_6_0 6 + +/* IVRS Revision Field */ +#define IVRS_FORMAT_FIXED 0x01 /* Type 10h & 11h only */ +#define IVRS_FORMAT_MIXED 0x02 /* Type 10h, 11h, & 40h */ + /* FACS flags */ #define ACPI_FACS_S4BIOS_F BIT(0) #define ACPI_FACS_64BIT_WAKE_F BIT(1) @@ -391,6 +403,47 @@ struct __packed acpi_spcr { u32 reserved2; };

+/* Tables defined by ACPI and generated by U-Boot */ +enum acpi_tables { + ACPITAB_BERT, + ACPITAB_DBG2, + ACPITAB_DMAR, + ACPITAB_DSDT, + ACPITAB_FACS, + ACPITAB_FADT, + ACPITAB_HEST, + ACPITAB_HPET, + ACPITAB_IVRS, + ACPITAB_MADT, + ACPITAB_MCFG, + ACPITAB_RSDP, + ACPITAB_RSDT, + ACPITAB_SLIT, + ACPITAB_SRAT, + ACPITAB_SSDT, + ACPITAB_TCPA, + ACPITAB_TPM2, + ACPITAB_XSDT, + ACPITAB_ECDT, + + /* Additional proprietary tables */ + ACPITAB_VFCT, + ACPITAB_NHLT, + ACPITAB_SPMI, + + ACPITAB_COUNT, +}; + +/** + * acpi_get_table_revision() - Get the revision number generated for a table + * + * This keeps the version-number information in one place + * + * @table: ACPI table to check + * @return version number that U-Boot generates + */ +int acpi_get_table_revision(enum acpi_tables table); + #endif /* !__ACPI__*/

#include <asm/acpi_table.h> diff --git a/lib/Makefile b/lib/Makefile index e82e32dfe9..46fe03003d 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -5,6 +5,7 @@

ifndef CONFIG_SPL_BUILD

+obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi/ obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_EFI_LOADER) += efi_driver/ obj-$(CONFIG_EFI_LOADER) += efi_loader/ diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile new file mode 100644 index 0000000000..660491ef71 --- /dev/null +++ b/lib/acpi/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += acpi_table.o diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c new file mode 100644 index 0000000000..971191f428 --- /dev/null +++ b/lib/acpi/acpi_table.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for ACPI table generation + * + * Copyright 2019 Google LLC + */ + +#include <common.h> +#include <acpi_table.h> + +int acpi_get_table_revision(enum acpi_tables table) +{ + switch (table) { + case ACPITAB_FADT: + return ACPI_FADT_REV_ACPI_3_0; + case ACPITAB_MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ + return 2; + case ACPITAB_MCFG: + return 1; + case ACPITAB_TCPA: + return 2; + case ACPITAB_TPM2: + return 4; + case ACPITAB_SSDT: /* ACPI 3.0 upto 6.3: 2 */ + return 2; + case ACPITAB_SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ + return 1; /* TODO Should probably be upgraded to 2 */ + case ACPITAB_DMAR: + return 1; + case ACPITAB_SLIT: /* ACPI 2.0 upto 6.3: 1 */ + return 1; + case ACPITAB_SPMI: /* IMPI 2.0 */ + return 5; + case ACPITAB_HPET: /* Currently 1. Table added in ACPI 2.0. */ + return 1; + case ACPITAB_VFCT: /* ACPI 2.0/3.0/4.0: 1 */ + return 1; + case ACPITAB_IVRS: + return IVRS_FORMAT_FIXED; + case ACPITAB_DBG2: + return 0; + case ACPITAB_FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ + return 1; + case ACPITAB_RSDT: /* ACPI 1.0 upto 6.3: 1 */ + return 1; + case ACPITAB_XSDT: /* ACPI 2.0 upto 6.3: 1 */ + return 1; + case ACPITAB_RSDP: /* ACPI 2.0 upto 6.3: 2 */ + return 2; + case ACPITAB_HEST: + return 1; + case ACPITAB_NHLT: + return 5; + case ACPITAB_BERT: + return 1; + default: + return -EINVAL; + } +} diff --git a/test/dm/acpi.c b/test/dm/acpi.c index e3519d4689..e65295b7ca 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -7,6 +7,7 @@ */

#include <common.h> +#include <acpi_table.h> #include <dm.h> #include <dm/acpi.h> #include <dm/test.h> @@ -53,3 +54,16 @@ static int dm_test_acpi_get_name(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_get_name, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test acpi_get_table_revision() */ +static int dm_test_acpi_get_table_revision(struct unit_test_state *uts) +{ + ut_asserteq(1, acpi_get_table_revision(ACPITAB_MCFG)); + ut_asserteq(2, acpi_get_table_revision(ACPITAB_RSDP)); + ut_asserteq(4, acpi_get_table_revision(ACPITAB_TPM2)); + ut_asserteq(-EINVAL, acpi_get_table_revision(ACPITAB_COUNT)); + + return 0; +} +DM_TEST(dm_test_acpi_get_table_revision, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

The DMA Remapping Reporting (DMAR) table contains information about DMA remapping.

Add a version simple version of this table with only the minimum fields filled out. i.e. no entries.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/acpi_table.h | 57 +++++++++++++++++++++++++++++++++++++++++++ lib/acpi/acpi_table.c | 26 ++++++++++++++++++++ test/dm/acpi.c | 14 +++++++++++ 3 files changed, 97 insertions(+)

diff --git a/include/acpi_table.h b/include/acpi_table.h index 91496ac047..d5a9e1c96f 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -21,6 +21,9 @@ #define ACPI_RSDP_REV_ACPI_1_0 0 #define ACPI_RSDP_REV_ACPI_2_0 2

+/* TODO(sjg@chromium.org): Figure out how to get compiler revision */ +#define ASL_REVISION 0 + #if !defined(__ACPI__)

/* @@ -352,6 +355,51 @@ struct acpi_csrt_shared_info { u32 max_block_size; };

+enum dmar_type { + DMAR_DRHD = 0, + DMAR_RMRR = 1, + DMAR_ATSR = 2, + DMAR_RHSA = 3, + DMAR_ANDD = 4 +}; + +enum { + DRHD_INCLUDE_PCI_ALL = 1 +}; + +enum dmar_flags { + DMAR_INTR_REMAP = 1 << 0, + DMAR_X2APIC_OPT_OUT = 1 << 1, + DMA_CTRL_PLATFORM_OPT_IN_FLAG = 1 << 2, +}; + +struct __packed dmar_entry { + u16 type; + u16 length; + u8 flags; + u8 reserved; + u16 segment; + u64 bar; +}; + +struct __packed dmar_rmrr_entry { + u16 type; + u16 length; + u16 reserved; + u16 segment; + u64 bar; + u64 limit; +}; + +/* DMAR (DMA Remapping Reporting Structure) */ +struct acpi_dmar { + struct acpi_table_header header; + u8 host_address_width; + u8 flags; + u8 reserved[10]; + struct dmar_entry structure[0]; +} __packed; + /* DBG2 definitions are partially used for SPCR interface_type */

/* Types for port_type field */ @@ -444,6 +492,15 @@ enum acpi_tables { */ int acpi_get_table_revision(enum acpi_tables table);

+/** + * acpi_create_dmar() - Create a DMA Remapping Reporting (DMAR) table + * + * @dmar: Place to put the table + * @flags: DMAR flags to use + * @return 0 if OK, -ve on error + */ +int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags); + #endif /* !__ACPI__*/

#include <asm/acpi_table.h> diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 971191f428..85147ac61a 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -6,7 +6,33 @@ */

#include <common.h> +#include <dm.h> #include <acpi_table.h> +#include <cpu.h> + +int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) +{ + struct acpi_table_header *header = &dmar->header; + struct cpu_info info; + struct udevice *cpu; + int ret; + + ret = uclass_first_device(UCLASS_CPU, &cpu); + if (ret) + return log_msg_ret("cpu", ret); + ret = cpu_get_info(cpu, &info); + memset((void *)dmar, 0, sizeof(struct acpi_dmar)); + + /* Fill out header fields. */ + acpi_fill_header(&dmar->header, "DMAR"); + header->length = sizeof(struct acpi_dmar); + header->revision = acpi_get_table_revision(ACPITAB_DMAR); + + dmar->host_address_width = info.address_width - 1; + dmar->flags = flags; + + return 0; +}

int acpi_get_table_revision(enum acpi_tables table) { diff --git a/test/dm/acpi.c b/test/dm/acpi.c index e65295b7ca..2737896643 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -67,3 +67,17 @@ static int dm_test_acpi_get_table_revision(struct unit_test_state *uts) } DM_TEST(dm_test_acpi_get_table_revision, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test acpi_create_dmar() */ +static int dm_test_acpi_create_dmar(struct unit_test_state *uts) +{ + struct acpi_dmar dmar; + + ut_assertok(acpi_create_dmar(&dmar, DMAR_INTR_REMAP)); + ut_asserteq(DMAR_INTR_REMAP, dmar.flags); + ut_asserteq(DMAR_INTR_REMAP, dmar.flags); + ut_asserteq(32 - 1, dmar.host_address_width); + + return 0; +} +DM_TEST(dm_test_acpi_create_dmar, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

This function needs to be used by sandbox for tests. Move it into the generic directory.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/acpi_table.h | 10 ++++++++++ lib/acpi/acpi_table.c | 10 ++++++++++ test/dm/acpi.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+)

diff --git a/include/acpi_table.h b/include/acpi_table.h index d5a9e1c96f..9904e421c3 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -501,6 +501,16 @@ int acpi_get_table_revision(enum acpi_tables table); */ int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);

+/** + * acpi_fill_header() - Set up a new table header + * + * This sets all fields except length, revision, checksum and aslc_revision + * + * @header: ACPI header to update + * @signature: Table signature to use (4 characters) + */ +void acpi_fill_header(struct acpi_table_header *header, char *signature); + #endif /* !__ACPI__*/

#include <asm/acpi_table.h> diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 85147ac61a..771a3580ce 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -9,6 +9,7 @@ #include <dm.h> #include <acpi_table.h> #include <cpu.h> +#include <version.h>

int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) { @@ -83,3 +84,12 @@ int acpi_get_table_revision(enum acpi_tables table) return -EINVAL; } } + +void acpi_fill_header(struct acpi_table_header *header, char *signature) +{ + memcpy(header->signature, signature, 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + header->oem_revision = U_BOOT_BUILD_DATE; + memcpy(header->aslc_id, ASLC_ID, 4); +} diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 2737896643..e28ebf4f90 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -9,6 +9,7 @@ #include <common.h> #include <acpi_table.h> #include <dm.h> +#include <version.h> #include <dm/acpi.h> #include <dm/test.h> #include <test/ut.h> @@ -81,3 +82,30 @@ static int dm_test_acpi_create_dmar(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_create_dmar, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test acpi_fill_header() */ +static int dm_test_acpi_fill_header(struct unit_test_state *uts) +{ + struct acpi_table_header hdr; + + /* Make sure these 5 fields are not changed */ + hdr.length = 0x11; + hdr.revision = 0x22; + hdr.checksum = 0x33; + hdr.aslc_revision = 0x44; + acpi_fill_header(&hdr, "ABCD"); + + ut_assertok(memcmp("ABCD", hdr.signature, sizeof(hdr.signature))); + ut_asserteq(0x11, hdr.length); + ut_asserteq(0x22, hdr.revision); + ut_asserteq(0x33, hdr.checksum); + ut_assertok(memcmp(OEM_ID, hdr.oem_id, sizeof(hdr.oem_id))); + ut_assertok(memcmp(OEM_TABLE_ID, hdr.oem_table_id, + sizeof(hdr.oem_table_id))); + ut_asserteq(U_BOOT_BUILD_DATE, hdr.oem_revision); + ut_assertok(memcmp(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id))); + ut_asserteq(0x44, hdr.aslc_revision); + + return 0; +} +DM_TEST(dm_test_acpi_fill_header, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

A device may want to write out ACPI tables to describe itself to Linux. Add a method to permit this.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/sandbox/dts/test.dts | 4 ++++ drivers/core/acpi.c | 33 ++++++++++++++++++++++++++++++ include/acpi_table.h | 1 + include/dm/acpi.h | 30 +++++++++++++++++++++++++++ test/dm/acpi.c | 43 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 111 insertions(+)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 34dc7fda98..82208de5a8 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -210,6 +210,10 @@ compatible = "denx,u-boot-acpi-test"; };

+ acpi-test2 { + compatible = "denx,u-boot-acpi-test"; + }; + clocks { clk_fixed: clk-fixed { compatible = "fixed-clock"; diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 45542199f5..f748aa3f33 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -30,3 +30,36 @@ int acpi_get_name(const struct udevice *dev, char *out_name)

return -ENOSYS; } + +int _acpi_write_dev_tables(struct acpi_ctx *ctx, const struct udevice *parent) +{ + struct acpi_ops *aops; + struct udevice *dev; + int ret; + + aops = device_get_acpi_ops(parent); + if (aops && aops->write_tables) { + log_debug("- %s\n", parent->name); + ret = aops->write_tables(parent, ctx); + if (ret) + return ret; + } + device_foreach_child(dev, parent) { + ret = _acpi_write_dev_tables(ctx, dev); + if (ret) + return ret; + } + + return 0; +} + +int acpi_write_dev_tables(struct acpi_ctx *ctx) +{ + int ret; + + log_debug("Writing device tables\n"); + ret = _acpi_write_dev_tables(ctx, dm_root()); + log_debug("Writing finished, err=%d\n", ret); + + return ret; +} diff --git a/include/acpi_table.h b/include/acpi_table.h index 9904e421c3..20b8904fe7 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -17,6 +17,7 @@ #define OEM_ID "U-BOOT" /* U-Boot */ #define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ #define ASLC_ID "INTL" /* Intel ASL Compiler */ +#define ACPI_TABLE_CREATOR OEM_TABLE_ID

#define ACPI_RSDP_REV_ACPI_1_0 0 #define ACPI_RSDP_REV_ACPI_2_0 2 diff --git a/include/dm/acpi.h b/include/dm/acpi.h index 8d6c3fd424..dcfcf5c347 100644 --- a/include/dm/acpi.h +++ b/include/dm/acpi.h @@ -24,6 +24,17 @@

#if !defined(__ACPI__)

+/** + * struct acpi_ctx - Context used for writing ACPI tables + * + * This contains a few useful pieces of information used when writing + * + * @current: Current address for writing + */ +struct acpi_ctx { + void *current; +}; + /** * struct acpi_ops - ACPI operations supported by driver model */ @@ -38,6 +49,15 @@ struct acpi_ops { * other error */ int (*get_name)(const struct udevice *dev, char *out_name); + + /** + * write_tables() - Write out any tables required by this device + * + * @dev: Device to write + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ + int (*write_tables)(const struct udevice *dev, struct acpi_ctx *ctx); };

#define device_get_acpi_ops(dev) ((dev)->driver->acpi_ops) @@ -72,6 +92,16 @@ int acpi_get_name(const struct udevice *dev, char *out_name); */ int acpi_return_name(char *out_name, const char *name);

+/** + * acpi_write_dev_tables() - Write ACPI tables required by devices + * + * This scans through all devices and tells them to write any tables they want + * to write. + * + * @return 0 if OK, -ve if any device returned an error + */ +int acpi_write_dev_tables(struct acpi_ctx *ctx); + #endif /* __ACPI__ */

#endif diff --git a/test/dm/acpi.c b/test/dm/acpi.c index e28ebf4f90..b87fbd16b0 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -15,6 +15,19 @@ #include <test/ut.h>

#define ACPI_TEST_DEV_NAME "ABCD" +#define BUF_SIZE 4096 + +static int testacpi_write_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct acpi_dmar *dmar; + + dmar = (struct acpi_dmar *)ctx->current; + acpi_create_dmar(dmar, DMAR_INTR_REMAP); + ctx->current += sizeof(struct acpi_dmar); + + return 0; +}

static int testacpi_get_name(const struct udevice *dev, char *out_name) { @@ -23,6 +36,7 @@ static int testacpi_get_name(const struct udevice *dev, char *out_name)

struct acpi_ops testacpi_ops = { .get_name = testacpi_get_name, + .write_tables = testacpi_write_tables, };

static const struct udevice_id testacpi_ids[] = { @@ -109,3 +123,32 @@ static int dm_test_acpi_fill_header(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_fill_header, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test ACPI write_tables() */ +static int dm_test_acpi_write_tables(struct unit_test_state *uts) +{ + struct acpi_dmar *dmar; + struct acpi_ctx ctx; + void *buf; + + buf = malloc(BUF_SIZE); + ut_assertnonnull(buf); + + ctx.current = buf; + ut_assertok(acpi_write_dev_tables(&ctx)); + dmar = buf; + + /* + * We should have two dmar tables, one for each "denx,u-boot-acpi-test" + * device + */ + ut_asserteq_ptr(dmar + 2, ctx.current); + ut_asserteq(DMAR_INTR_REMAP, dmar->flags); + ut_asserteq(32 - 1, dmar->host_address_width); + + ut_asserteq(DMAR_INTR_REMAP, dmar[1].flags); + ut_asserteq(32 - 1, dmar[1].host_address_width); + + return 0; +} +DM_TEST(dm_test_acpi_write_tables, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

The current code uses an address but a pointer would result in fewer casts. Also it repeats the alignment code in a lot of places so this would be better done in a helper function.

Update write_acpi_tables() to make use of the new acpi_ctx structure, adding a few helpers to clean things up.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 88 +++++++++++++++++++-------------------- include/acpi_table.h | 36 ++++++++++++++++ lib/acpi/acpi_table.c | 22 ++++++++++ test/dm/acpi.c | 28 +++++++++++++ 4 files changed, 129 insertions(+), 45 deletions(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 71913b6f65..4bd331f20f 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -10,6 +10,7 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <mapmem.h> #include <serial.h> #include <version.h> #include <asm/acpi/global_nvs.h> @@ -19,6 +20,7 @@ #include <asm/mpspec.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> +#include <dm/acpi.h>

/* * IASL compiles the dsdt entries and writes the hex values @@ -477,9 +479,9 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) /* * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ -ulong write_acpi_tables(ulong start) +ulong write_acpi_tables(ulong start_addr) { - u32 current; + struct acpi_ctx sctx, *ctx = &sctx; struct acpi_rsdp *rsdp; struct acpi_rsdt *rsdt; struct acpi_xsdt *xsdt; @@ -490,60 +492,61 @@ ulong write_acpi_tables(ulong start) struct acpi_madt *madt; struct acpi_csrt *csrt; struct acpi_spcr *spcr; + void *start; + ulong addr; int i;

- current = start; + start = map_sysmem(start_addr, 0); + ctx->current = start;

/* Align ACPI tables to 16 byte */ - current = ALIGN(current, 16); + acpi_align(ctx);

- debug("ACPI: Writing ACPI tables at %lx\n", start); + debug("ACPI: Writing ACPI tables at %lx\n", start_addr);

/* We need at least an RSDP and an RSDT Table */ - rsdp = (struct acpi_rsdp *)current; - current += sizeof(struct acpi_rsdp); - current = ALIGN(current, 16); - rsdt = (struct acpi_rsdt *)current; - current += sizeof(struct acpi_rsdt); - current = ALIGN(current, 16); - xsdt = (struct acpi_xsdt *)current; - current += sizeof(struct acpi_xsdt); + rsdp = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_rsdp)); + rsdt = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_rsdt)); + xsdt = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_xsdt)); /* * Per ACPI spec, the FACS table address must be aligned to a 64 byte * boundary (Windows checks this, but Linux does not). */ - current = ALIGN(current, 64); + acpi_align_large(ctx);

/* clear all table memory */ - memset((void *)start, 0, current - start); + memset((void *)start, 0, ctx->current - start);

acpi_write_rsdp(rsdp, rsdt, xsdt); acpi_write_rsdt(rsdt); acpi_write_xsdt(xsdt);

debug("ACPI: * FACS\n"); - facs = (struct acpi_facs *)current; - current += sizeof(struct acpi_facs); - current = ALIGN(current, 16); + facs = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_facs));

acpi_create_facs(facs);

debug("ACPI: * DSDT\n"); - dsdt = (struct acpi_table_header *)current; + dsdt = ctx->current; memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header)); - current += sizeof(struct acpi_table_header); - memcpy((char *)current, + acpi_inc(ctx, sizeof(struct acpi_table_header)); + memcpy(ctx->current, (char *)&AmlCode + sizeof(struct acpi_table_header), dsdt->length - sizeof(struct acpi_table_header)); - current += dsdt->length - sizeof(struct acpi_table_header); - current = ALIGN(current, 16); + acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header));

/* Pack GNVS into the ACPI table area */ for (i = 0; i < dsdt->length; i++) { u32 *gnvs = (u32 *)((u32)dsdt + i); if (*gnvs == ACPI_GNVS_ADDR) { - debug("Fix up global NVS in DSDT to 0x%08x\n", current); - *gnvs = current; + ulong addr = (ulong)map_to_sysmem(ctx->current); + + debug("Fix up global NVS in DSDT to %#08lx\n", addr); + *gnvs = addr; break; } } @@ -553,51 +556,46 @@ ulong write_acpi_tables(ulong start) dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);

/* Fill in platform-specific global NVS variables */ - acpi_create_gnvs((struct acpi_global_nvs *)current); - current += sizeof(struct acpi_global_nvs); - current = ALIGN(current, 16); + acpi_create_gnvs(ctx->current); + acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));

debug("ACPI: * FADT\n"); - fadt = (struct acpi_fadt *)current; - current += sizeof(struct acpi_fadt); - current = ALIGN(current, 16); + fadt = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_fadt)); acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(rsdp, fadt);

debug("ACPI: * MADT\n"); - madt = (struct acpi_madt *)current; + madt = ctx->current; acpi_create_madt(madt); - current += madt->header.length; + acpi_inc_align(ctx, madt->header.length); acpi_add_table(rsdp, madt); - current = ALIGN(current, 16);

debug("ACPI: * MCFG\n"); - mcfg = (struct acpi_mcfg *)current; + mcfg = ctx->current; acpi_create_mcfg(mcfg); - current += mcfg->header.length; + acpi_inc_align(ctx, mcfg->header.length); acpi_add_table(rsdp, mcfg); - current = ALIGN(current, 16);

debug("ACPI: * CSRT\n"); - csrt = (struct acpi_csrt *)current; + csrt = ctx->current; acpi_create_csrt(csrt); - current += csrt->header.length; + acpi_inc_align(ctx, csrt->header.length); acpi_add_table(rsdp, csrt); - current = ALIGN(current, 16);

debug("ACPI: * SPCR\n"); - spcr = (struct acpi_spcr *)current; + spcr = ctx->current; acpi_create_spcr(spcr); - current += spcr->header.length; + acpi_inc_align(ctx, spcr->header.length); acpi_add_table(rsdp, spcr); - current = ALIGN(current, 16);

- debug("current = %x\n", current); + addr = map_to_sysmem(ctx->current); + debug("current = %lx\n", addr);

acpi_rsdp_addr = (unsigned long)rsdp; debug("ACPI: done\n");

- return current; + return addr; }

ulong acpi_get_rsdp_addr(void) diff --git a/include/acpi_table.h b/include/acpi_table.h index 20b8904fe7..6b6b4c671b 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -27,6 +27,8 @@

#if !defined(__ACPI__)

+struct acpi_ctx; + /* * RSDP (Root System Description Pointer) * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum @@ -512,6 +514,40 @@ int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags); */ void acpi_fill_header(struct acpi_table_header *header, char *signature);

+/** + * acpi_align() - Align the ACPI output pointer to a 16-byte boundary + * + * @ctx: ACPI context + */ +void acpi_align(struct acpi_ctx *ctx); + +/** + * acpi_align_large() - Align the ACPI output pointer to a 64-byte boundary + * + * @ctx: ACPI context + */ +void acpi_align_large(struct acpi_ctx *ctx); + +/** + * acpi_inc() - Increment the ACPI output pointer by a bit + * + * The pointer is NOT aligned afterwards. + * + * @ctx: ACPI context + * @amount: Amount to increment by + */ +void acpi_inc(struct acpi_ctx *ctx, uint amount); + +/** + * acpi_inc_align() - Increment the ACPI output pointer by a bit and align + * + * The pointer is aligned afterwards. + * + * @ctx: ACPI context + * @amount: Amount to increment by + */ +void acpi_inc_align(struct acpi_ctx *ctx, uint amount); + #endif /* !__ACPI__*/

#include <asm/acpi_table.h> diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 771a3580ce..87187fef3c 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -10,6 +10,7 @@ #include <acpi_table.h> #include <cpu.h> #include <version.h> +#include <dm/acpi.h>

int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) { @@ -93,3 +94,24 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature) header->oem_revision = U_BOOT_BUILD_DATE; memcpy(header->aslc_id, ASLC_ID, 4); } + +void acpi_align(struct acpi_ctx *ctx) +{ + ctx->current = (void *)ALIGN((ulong)ctx->current, 16); +} + +void acpi_align_large(struct acpi_ctx *ctx) +{ + ctx->current = (void *)ALIGN((ulong)ctx->current, 64); +} + +void acpi_inc(struct acpi_ctx *ctx, uint amount) +{ + ctx->current += amount; +} + +void acpi_inc_align(struct acpi_ctx *ctx, uint amount) +{ + ctx->current += amount; + acpi_align(ctx); +} diff --git a/test/dm/acpi.c b/test/dm/acpi.c index b87fbd16b0..0bd7e51ac9 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -152,3 +152,31 @@ static int dm_test_acpi_write_tables(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_write_tables, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test basic ACPI functions */ +static int dm_test_acpi_basic(struct unit_test_state *uts) +{ + struct acpi_ctx ctx; + + /* Check align works */ + ctx.current = (void *)5; + acpi_align(&ctx); + ut_asserteq_ptr((void *)16, ctx.current); + + /* Check that align does nothing if already aligned */ + acpi_align(&ctx); + ut_asserteq_ptr((void *)16, ctx.current); + acpi_align_large(&ctx); + ut_asserteq_ptr((void *)64, ctx.current); + acpi_align_large(&ctx); + ut_asserteq_ptr((void *)64, ctx.current); + + /* Check incrementing */ + acpi_inc(&ctx, 3); + ut_asserteq_ptr((void *)67, ctx.current); + acpi_inc_align(&ctx, 3); + ut_asserteq_ptr((void *)80, ctx.current); + + return 0; +} +DM_TEST(dm_test_acpi_basic, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

We don't actually support tables without an XSDT so we can drop this dead code.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index b7bdd86e91..bc6d19ea2e 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -42,19 +42,8 @@ static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, rsdp->length = sizeof(struct acpi_rsdp); rsdp->rsdt_address = (u32)rsdt;

- /* - * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2 - * - * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2. - * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR - * revision 0) - */ - if (xsdt == NULL) { - rsdp->revision = ACPI_RSDP_REV_ACPI_1_0; - } else { - rsdp->xsdt_address = (u64)(u32)xsdt; - rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; - } + rsdp->xsdt_address = (u64)(u32)xsdt; + rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;

/* Calculate checksums */ rsdp->checksum = table_compute_checksum((void *)rsdp, 20);

We always write three basic tables to ACPI at the start. Move this into its own function, along with acpi_fill_header(), so we can write a test for this code.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 86 +-------------------------------------- include/acpi_table.h | 10 +++++ lib/acpi/acpi_table.c | 86 ++++++++++++++++++++++++++++++++++++++- test/dm/acpi.c | 55 ++++++++++++++++++++++++- 4 files changed, 148 insertions(+), 89 deletions(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 920b6bd847..83b92e2a4c 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -31,67 +31,6 @@ extern const unsigned char AmlCode[]; /* ACPI RSDP address to be used in boot parameters */ static ulong acpi_rsdp_addr;

-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, - struct acpi_xsdt *xsdt) -{ - memset(rsdp, 0, sizeof(struct acpi_rsdp)); - - memcpy(rsdp->signature, RSDP_SIG, 8); - memcpy(rsdp->oem_id, OEM_ID, 6); - - rsdp->length = sizeof(struct acpi_rsdp); - rsdp->rsdt_address = (u32)rsdt; - - rsdp->xsdt_address = (u64)(u32)xsdt; - rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; - - /* Calculate checksums */ - rsdp->checksum = table_compute_checksum((void *)rsdp, 20); - rsdp->ext_checksum = table_compute_checksum((void *)rsdp, - sizeof(struct acpi_rsdp)); -} - -void acpi_fill_header(struct acpi_table_header *header, char *signature) -{ - memcpy(header->signature, signature, 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, OEM_TABLE_ID, 8); - header->oem_revision = U_BOOT_BUILD_DATE; - memcpy(header->aslc_id, ASLC_ID, 4); -} - -static void acpi_write_rsdt(struct acpi_rsdt *rsdt) -{ - struct acpi_table_header *header = &(rsdt->header); - - /* Fill out header fields */ - acpi_fill_header(header, "RSDT"); - header->length = sizeof(struct acpi_rsdt); - header->revision = 1; - - /* Entries are filled in later, we come with an empty set */ - - /* Fix checksum */ - header->checksum = table_compute_checksum((void *)rsdt, - sizeof(struct acpi_rsdt)); -} - -static void acpi_write_xsdt(struct acpi_xsdt *xsdt) -{ - struct acpi_table_header *header = &(xsdt->header); - - /* Fill out header fields */ - acpi_fill_header(header, "XSDT"); - header->length = sizeof(struct acpi_xsdt); - header->revision = 1; - - /* Entries are filled in later, we come with an empty set */ - - /* Fix checksum */ - header->checksum = table_compute_checksum((void *)xsdt, - sizeof(struct acpi_xsdt)); -} - static void acpi_create_facs(struct acpi_facs *facs) { memset((void *)facs, 0, sizeof(struct acpi_facs)); @@ -411,7 +350,6 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) ulong write_acpi_tables(ulong start_addr) { struct acpi_ctx sctx, *ctx = &sctx; - struct acpi_xsdt *xsdt; struct acpi_facs *facs; struct acpi_table_header *dsdt; struct acpi_fadt *fadt; @@ -424,32 +362,10 @@ ulong write_acpi_tables(ulong start_addr) int i;

start = map_sysmem(start_addr, 0); - ctx->current = start; - - /* Align ACPI tables to 16 byte */ - acpi_align(ctx);

debug("ACPI: Writing ACPI tables at %lx\n", start_addr);

- /* We need at least an RSDP and an RSDT Table */ - ctx->rsdp = ctx->current; - acpi_inc_align(ctx, sizeof(struct acpi_rsdp)); - ctx->rsdt = ctx->current; - acpi_inc_align(ctx, sizeof(struct acpi_rsdt)); - xsdt = ctx->current; - acpi_inc_align(ctx, sizeof(struct acpi_xsdt)); - /* - * Per ACPI spec, the FACS table address must be aligned to a 64 byte - * boundary (Windows checks this, but Linux does not). - */ - acpi_align_large(ctx); - - /* clear all table memory */ - memset((void *)start, 0, ctx->current - start); - - acpi_write_rsdp(ctx->rsdp, ctx->rsdt, xsdt); - acpi_write_rsdt(ctx->rsdt); - acpi_write_xsdt(xsdt); + acpi_setup_base_tables(ctx, start);

debug("ACPI: * FACS\n"); facs = ctx->current; diff --git a/include/acpi_table.h b/include/acpi_table.h index 29b7bb73c4..373c193f4a 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -557,6 +557,16 @@ void acpi_inc_align(struct acpi_ctx *ctx, uint amount); */ int acpi_add_table(struct acpi_ctx *ctx, void *table);

+/** + * acpi_setup_base_tables() - Set up context along with RSDP, RSDT and XDST + * + * Set up the context with the given start position. Some basic tables are + * always needed, so set them up as well. + * + * @ctx: Context to set up + */ +void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start); + #endif /* !__ACPI__*/

#include <asm/acpi_table.h> diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index dd66895815..92df07ac99 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -156,7 +156,7 @@ int acpi_add_table(struct acpi_ctx *ctx, void *table)

/* Re-calculate checksum */ rsdt->header.checksum = 0; - rsdt->header.checksum = table_compute_checksum((u8 *)rsdt, + rsdt->header.checksum = table_compute_checksum(rsdt, rsdt->header.length);

/* @@ -174,8 +174,90 @@ int acpi_add_table(struct acpi_ctx *ctx, void *table) /* Re-calculate checksum */ xsdt->header.checksum = 0; xsdt->header.checksum = - table_compute_checksum((u8 *)xsdt, xsdt->header.length); + table_compute_checksum((xsdt, xsdt->header.length); }

return 0; } + +static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, + struct acpi_xsdt *xsdt) +{ + memset(rsdp, 0, sizeof(struct acpi_rsdp)); + + memcpy(rsdp->signature, RSDP_SIG, 8); + memcpy(rsdp->oem_id, OEM_ID, 6); + + rsdp->length = sizeof(struct acpi_rsdp); + rsdp->rsdt_address = map_to_sysmem(rsdt); + + rsdp->xsdt_address = map_to_sysmem(xsdt); + rsdp->revision = ACPI_RSDP_REV_ACPI_2_0; + + /* Calculate checksums */ + rsdp->checksum = table_compute_checksum(rsdp, 20); + rsdp->ext_checksum = table_compute_checksum(rsdp, + sizeof(struct acpi_rsdp)); +} + +static void acpi_write_rsdt(struct acpi_rsdt *rsdt) +{ + struct acpi_table_header *header = &rsdt->header; + + /* Fill out header fields */ + acpi_fill_header(header, "RSDT"); + header->length = sizeof(struct acpi_rsdt); + header->revision = 1; + + /* Entries are filled in later, we come with an empty set */ + + /* Fix checksum */ + header->checksum = table_compute_checksum(rsdt, + sizeof(struct acpi_rsdt)); +} + +static void acpi_write_xsdt(struct acpi_xsdt *xsdt) +{ + struct acpi_table_header *header = &xsdt->header; + + /* Fill out header fields */ + acpi_fill_header(header, "XSDT"); + header->length = sizeof(struct acpi_xsdt); + header->revision = 1; + + /* Entries are filled in later, we come with an empty set */ + + /* Fix checksum */ + header->checksum = table_compute_checksum(xsdt, + sizeof(struct acpi_xsdt)); +} + +void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start) +{ + struct acpi_xsdt *xsdt; + + ctx->current = start; + + /* Align ACPI tables to 16 byte */ + acpi_align(ctx); + + /* We need at least an RSDP and an RSDT Table */ + ctx->rsdp = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_rsdp)); + ctx->rsdt = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_rsdt)); + xsdt = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_xsdt)); + /* + * Per ACPI spec, the FACS table address must be aligned to a 64 byte + * boundary (Windows checks this, but Linux does not). + */ + acpi_align_large(ctx); + + /* clear all table memory */ + memset((void *)start, '\0', ctx->current - start); + + acpi_write_rsdp(ctx->rsdp, ctx->rsdt, xsdt); + acpi_write_rsdt(ctx->rsdt); + acpi_write_xsdt(xsdt); +} diff --git a/test/dm/acpi.c b/test/dm/acpi.c index a2a57a29a6..bb66c7229c 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -9,6 +9,9 @@ #include <common.h> #include <acpi_table.h> #include <dm.h> +#include <malloc.h> +#include <mapmem.h> +#include <tables_csum.h> #include <version.h> #include <dm/acpi.h> #include <dm/test.h> @@ -138,9 +141,9 @@ static int dm_test_acpi_write_tables(struct unit_test_state *uts) buf = malloc(BUF_SIZE); ut_assertnonnull(buf);

- ctx.current = buf; + acpi_setup_base_tables(&ctx, buf); + dmar = ctx.current; ut_assertok(acpi_write_dev_tables(&ctx)); - dmar = buf;

/* * We should have two dmar tables, one for each "denx,u-boot-acpi-test" @@ -153,6 +156,11 @@ static int dm_test_acpi_write_tables(struct unit_test_state *uts) ut_asserteq(DMAR_INTR_REMAP, dmar[1].flags); ut_asserteq(32 - 1, dmar[1].host_address_width);

+ /* Check that the pointers were added correctly */ + ut_asserteq(map_to_sysmem(dmar), ctx.rsdt->entry[0]); + ut_asserteq(map_to_sysmem(dmar + 1), ctx.rsdt->entry[1]); + ut_asserteq(0, ctx.rsdt->entry[2]); + return 0; } DM_TEST(dm_test_acpi_write_tables, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); @@ -184,3 +192,46 @@ static int dm_test_acpi_basic(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_basic, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test acpi_setup_base_tables */ +static int dm_test_acpi_setup_base_tables(struct unit_test_state *uts) +{ + struct acpi_rsdp *rsdp; + struct acpi_rsdt *rsdt; + struct acpi_xsdt *xsdt; + struct acpi_ctx ctx; + void *buf, *end; + + /* Use an unaligned address deliberately */ + buf = memalign(64, BUF_SIZE); + ut_assertnonnull(buf); + acpi_setup_base_tables(&ctx, buf + 4); + + rsdp = buf + 16; + ut_asserteq_ptr(rsdp, ctx.rsdp); + ut_assertok(memcmp(RSDP_SIG, rsdp->signature, sizeof(rsdp->signature))); + ut_asserteq(sizeof(*rsdp), rsdp->length); + ut_assertok(table_compute_checksum(rsdp, 20)); + ut_assertok(table_compute_checksum(rsdp, sizeof(*rsdp))); + + rsdt = PTR_ALIGN((void *)rsdp + sizeof(*rsdp), 16); + ut_asserteq_ptr(rsdt, ctx.rsdt); + ut_assertok(memcmp("RSDT", rsdt->header.signature, ACPI_NAME_LEN)); + ut_asserteq(sizeof(*rsdt), rsdt->header.length); + ut_assertok(table_compute_checksum(rsdt, sizeof(*rsdt))); + + xsdt = PTR_ALIGN((void *)rsdt + sizeof(*rsdt), 16); + ut_assertok(memcmp("XSDT", xsdt->header.signature, ACPI_NAME_LEN)); + ut_asserteq(sizeof(*xsdt), xsdt->header.length); + ut_assertok(table_compute_checksum(xsdt, sizeof(*xsdt))); + + end = PTR_ALIGN((void *)xsdt + sizeof(*xsdt), 64); + ut_asserteq_ptr(end, ctx.current); + + ut_asserteq(map_to_sysmem(rsdt), rsdp->rsdt_address); + ut_asserteq(map_to_sysmem(xsdt), rsdp->xsdt_address); + + return 0; +} +DM_TEST(dm_test_acpi_setup_base_tables, + DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

It is useful to dump ACPI tables in U-Boot to see what has been generated. Add a command to handle this.

To allow the command to find the tables, add a position into the global data.

Support subcommands to list and dump the tables.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/sandbox/include/asm/global_data.h | 1 + arch/x86/include/asm/global_data.h | 1 + cmd/Kconfig | 14 ++ cmd/Makefile | 1 + cmd/acpi.c | 179 +++++++++++++++++++++++++ lib/acpi/acpi_table.c | 1 + test/dm/acpi.c | 73 ++++++++++ 7 files changed, 270 insertions(+) create mode 100644 cmd/acpi.c

diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index f4ce72d566..f95ddb058a 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -13,6 +13,7 @@ struct arch_global_data { uint8_t *ram_buf; /* emulated RAM buffer */ void *text_base; /* pointer to base of text region */ + ulong acpi_start; /* Start address of ACPI tables */ };

#include <asm-generic/global_data.h> diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index f4c1839104..4aee2f3e8c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -123,6 +123,7 @@ struct arch_global_data { #ifdef CONFIG_FSP_VERSION2 struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ #endif + ulong acpi_start; /* Start address of ACPI tables */ };

#endif diff --git a/cmd/Kconfig b/cmd/Kconfig index 4e29e7b3c5..5c30c0ef3f 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -190,6 +190,20 @@ comment "Commands"

menu "Info commands"

+config CMD_ACPI + bool "acpi" + default y if ACPIGEN + help + List and dump ACPI tables. ACPI (Advanced Configuration and Power + Interface) is used mostly on x86 for providing information to the + Operating System about devices in the system. The tables are set up + by the firmware, typically U-Boot but possibly an earlier firmware + module, if U-Boot is chain-loaded from something else. ACPI tables + can also include code, to perform hardware-specific tasks required + by the Operating Systems. This allows some amount of separation + between the firmware and OS, and is particularly useful when you + want to make hardware changes without the OS needing to be adjusted. + config CMD_BDI bool "bdinfo" default y diff --git a/cmd/Makefile b/cmd/Makefile index 12e898d962..16bec7b05c 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -11,6 +11,7 @@ obj-y += help.o obj-y += version.o

# command +obj-$(CONFIG_CMD_ACPI) += acpi.o obj-$(CONFIG_CMD_AES) += aes.o obj-$(CONFIG_CMD_AB_SELECT) += ab_select.o obj-$(CONFIG_CMD_ADC) += adc.o diff --git a/cmd/acpi.c b/cmd/acpi.c new file mode 100644 index 0000000000..b66c26265b --- /dev/null +++ b/cmd/acpi.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass sjg@chromium.org + */ +#include <common.h> +#include <acpi_table.h> +#include <command.h> +#include <mapmem.h> +#include <asm/acpi_table.h> +#include <dm/acpi.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void dump_hdr(struct acpi_table_header *hdr) +{ + bool has_hdr = memcmp(hdr->signature, "FACS", ACPI_NAME_LEN); + + printf("%.*s %08lx %06x", ACPI_NAME_LEN, hdr->signature, + (ulong)map_to_sysmem(hdr), hdr->length); + if (has_hdr) { + printf(" (v%02d %.6s %.8s %u %.4s %d)\n", hdr->revision, + hdr->oem_id, hdr->oem_table_id, hdr->oem_revision, + hdr->aslc_id, hdr->aslc_revision); + } else { + printf("\n"); + } +} + +/** + * find_table() - Look up an ACPI table + * + * @sig: Signature of table (4 characters, upper case) + * @return pointer to table header, or NULL if not found + */ +struct acpi_table_header *find_table(const char *sig) +{ + struct acpi_rsdp *rsdp; + struct acpi_rsdt *rsdt; + int len, i, count; + + rsdp = map_sysmem(gd->arch.acpi_start, 0); + if (!rsdp) + return NULL; + rsdt = map_sysmem(rsdp->rsdt_address, 0); + len = rsdt->header.length - sizeof(rsdt->header); + count = len / sizeof(u32); + for (i = 0; i < count; i++) { + struct acpi_table_header *hdr; + + hdr = map_sysmem(rsdt->entry[i], 0); + if (!memcmp(hdr->signature, sig, ACPI_NAME_LEN)) + return hdr; + if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) { + struct acpi_fadt *fadt = (struct acpi_fadt *)hdr; + + if (!memcmp(sig, "DSDT", ACPI_NAME_LEN) && fadt->dsdt) + return map_sysmem(fadt->dsdt, 0); + if (!memcmp(sig, "FACS", ACPI_NAME_LEN) && + fadt->firmware_ctrl) + return map_sysmem(fadt->firmware_ctrl, 0); + } + } + + return NULL; +} + +static int dump_table_name(const char *sig) +{ + struct acpi_table_header *hdr; + + hdr = find_table(sig); + if (!hdr) + return -ENOENT; + printf("%.*s @ %08lx\n", ACPI_NAME_LEN, hdr->signature, + (ulong)map_to_sysmem(hdr)); + print_buffer(0, hdr, 1, hdr->length, 0); + + return 0; +} + +static void list_fact(struct acpi_fadt *fadt) +{ + if (fadt->dsdt) + dump_hdr(map_sysmem(fadt->dsdt, 0)); + if (fadt->firmware_ctrl) + dump_hdr(map_sysmem(fadt->firmware_ctrl, 0)); +} + +static int list_rsdt(struct acpi_rsdt *rsdt, struct acpi_xsdt *xsdt) +{ + int len, i, count; + + dump_hdr(&rsdt->header); + if (xsdt) + dump_hdr(&xsdt->header); + len = rsdt->header.length - sizeof(rsdt->header); + count = len / sizeof(u32); + for (i = 0; i < count; i++) { + struct acpi_table_header *hdr; + + if (!rsdt->entry[i]) + break; + hdr = map_sysmem(rsdt->entry[i], 0); + dump_hdr(hdr); + if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN)) + list_fact((struct acpi_fadt *)hdr); + if (xsdt) { + if (xsdt->entry[i] != rsdt->entry[i]) { + printf(" (xsdt mismatch %llx)\n", + xsdt->entry[i]); + } + } + } + + return 0; +} + +static int list_rsdp(struct acpi_rsdp *rsdp) +{ + struct acpi_rsdt *rsdt; + struct acpi_xsdt *xsdt; + + printf("RSDP %08lx %06x (v%02d %.6s)\n", (ulong)map_to_sysmem(rsdp), + rsdp->length, rsdp->revision, rsdp->oem_id); + rsdt = map_sysmem(rsdp->rsdt_address, 0); + xsdt = map_sysmem(rsdp->xsdt_address, 0); + list_rsdt(rsdt, xsdt); + + return 0; +} + +static int do_acpi_list(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct acpi_rsdp *rsdp; + + rsdp = map_sysmem(gd->arch.acpi_start, 0); + if (!rsdp) { + printf("No ACPI tables present\n"); + return 0; + } + printf("ACPI tables start at %lx\n", gd->arch.acpi_start); + list_rsdp(rsdp); + + return 0; +} + +static int do_acpi_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + const char *name; + char sig[ACPI_NAME_LEN]; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + name = argv[1]; + if (strlen(name) != ACPI_NAME_LEN) { + printf("Table name '%s' must be four characters\n", name); + return CMD_RET_FAILURE; + } + str_to_upper(name, sig, -1); + ret = dump_table_name(sig); + if (ret) { + printf("Table '%.*s' not found\n", ACPI_NAME_LEN, sig); + return CMD_RET_FAILURE; + } + + return 0; +} + +static char acpi_help_text[] = + "list - list ACPI tables\n" + "acpi dump <name> - Dump ACPI table"; + +U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text, + U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list), + U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump)); diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 92466276d1..1cefe02ca7 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -234,6 +234,7 @@ void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start)

/* Align ACPI tables to 16 byte */ acpi_align(ctx); + gd->arch.acpi_start = map_to_sysmem(ctx->current);

/* We need at least an RSDP and an RSDT Table */ ctx->rsdp = ctx->current; diff --git a/test/dm/acpi.c b/test/dm/acpi.c index a60f67e73d..feb380b26c 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -8,9 +8,11 @@

#include <common.h> #include <acpi_table.h> +#include <console.h> #include <dm.h> #include <malloc.h> #include <mapmem.h> +#include <version.h> #include <tables_csum.h> #include <version.h> #include <dm/acpi.h> @@ -210,6 +212,7 @@ static int dm_test_acpi_setup_base_tables(struct unit_test_state *uts) buf = memalign(64, BUF_SIZE); ut_assertnonnull(buf); acpi_setup_base_tables(&ctx, buf + 4); + ut_asserteq(map_to_sysmem(PTR_ALIGN(buf + 4, 16)), gd->arch.acpi_start);

rsdp = buf + 16; ut_asserteq_ptr(rsdp, ctx.rsdp); @@ -240,3 +243,73 @@ static int dm_test_acpi_setup_base_tables(struct unit_test_state *uts) } DM_TEST(dm_test_acpi_setup_base_tables, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test 'acpi list' command */ +static int dm_test_acpi_cmd_list(struct unit_test_state *uts) +{ + struct acpi_ctx ctx; + ulong addr; + void *buf; + + buf = memalign(16, BUF_SIZE); + ut_assertnonnull(buf); + acpi_setup_base_tables(&ctx, buf); + + ut_assertok(acpi_write_dev_tables(&ctx)); + + console_record_reset(); + run_command("acpi list", 0); + addr = (ulong)map_to_sysmem(buf); + ut_assert_nextline("ACPI tables start at %lx", addr); + ut_assert_nextline("RSDP %08lx %06lx (v02 U-BOOT)", addr, + sizeof(struct acpi_rsdp)); + addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16); + ut_assert_nextline("RSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + addr, sizeof(struct acpi_table_header) + + 2 * sizeof(u32), U_BOOT_BUILD_DATE); + addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16); + ut_assert_nextline("XSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + addr, sizeof(struct acpi_table_header) + + 2 * sizeof(u64), U_BOOT_BUILD_DATE); + addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64); + ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); + ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_acpi_cmd_list, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test 'acpi dump' command */ +static int dm_test_acpi_cmd_dump(struct unit_test_state *uts) +{ + struct acpi_ctx ctx; + ulong addr; + void *buf; + + buf = memalign(16, BUF_SIZE); + ut_assertnonnull(buf); + acpi_setup_base_tables(&ctx, buf); + + ut_assertok(acpi_write_dev_tables(&ctx)); + + /* First search for a non-existent table */ + console_record_reset(); + run_command("acpi dump rdst", 0); + ut_assert_nextline("Table 'RDST' not found"); + ut_assert_console_end(); + + /* Now a real table */ + console_record_reset(); + run_command("acpi dump dmar", 0); + addr = ALIGN(map_to_sysmem(ctx.xsdt) + sizeof(struct acpi_xsdt), 64); + ut_assert_nextline("DMAR @ %08lx", addr); + ut_assert_nextlines_are_dump(0x30); + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_acpi_cmd_dump, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

Some devices need to create ACPI tables to communcate their parameters to Linux. Add support for this.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/acpi_device.h | 707 ++++++++++++++++++++++++++ lib/acpi/acpi_device.c | 1093 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 1800 insertions(+) create mode 100644 include/acpi_device.h create mode 100644 lib/acpi/acpi_device.c

diff --git a/include/acpi_device.h b/include/acpi_device.h new file mode 100644 index 0000000000..919e6bcdaa --- /dev/null +++ b/include/acpi_device.h @@ -0,0 +1,707 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Generation of tables for particular device types + * + * Copyright 2019 Google LLC + * Mostly taken from coreboot file of the same name + */ + +#ifndef __ACPI_DEVICE_H +#define __ACPI_DEVICE_H + +#include <i2c.h> +#include <irq.h> +#include <spi.h> +#include <asm-generic/gpio.h> + +struct acpi_ctx; +struct irq; +struct gpio_desc; +struct udevice; + +/** + * enum acpi_dp_type - types of device property objects + * + * These refer to the types defined by struct acpi_dp below + * + * @ACPI_DP_TYPE_UNKNOWN: Unknown / do not use + * @ACPI_DP_TYPE_INTEGER: Integer value (u64) in @integer + * @ACPI_DP_TYPE_STRING: String value in @string + * @ACPI_DP_TYPE_REFERENCE: Reference to another object, with value in @string + * @ACPI_DP_TYPE_TABLE: Type for a top-level table which may have children + * @ACPI_DP_TYPE_ARRAY: Array of items with first item in @array and following + * items linked from that item's @next + * @ACPI_DP_TYPE_CHILD: Child object, with siblings in that child's @next + */ +enum acpi_dp_type { + ACPI_DP_TYPE_UNKNOWN, + ACPI_DP_TYPE_INTEGER, + ACPI_DP_TYPE_STRING, + ACPI_DP_TYPE_REFERENCE, + ACPI_DP_TYPE_TABLE, + ACPI_DP_TYPE_ARRAY, + ACPI_DP_TYPE_CHILD, +}; + +/* ACPI descriptor values for common descriptors: SERIAL_BUS means I2C */ +#define ACPI_DESCRIPTOR_LARGE BIT(7) +#define ACPI_DESCRIPTOR_INTERRUPT (ACPI_DESCRIPTOR_LARGE | 9) +#define ACPI_DESCRIPTOR_GPIO (ACPI_DESCRIPTOR_LARGE | 12) +#define ACPI_DESCRIPTOR_SERIAL_BUS (ACPI_DESCRIPTOR_LARGE | 14) + +/* + * PRP0001 is a special DT namespace link device ID. It provides a means to use + * existing DT-compatible device identification in ACPI. When this _HID is used + * by an ACPI device, the ACPI subsystem in OS looks up "compatible" property in + * the device object's _DSD and will use the value of that property to identify + * the corresponding device in analogy with the original DT device + * identification algorithm. + * More details can be found in Linux kernel documentation: + * Documentation/acpi/enumeration.txt + */ +#define ACPI_DT_NAMESPACE_HID "PRP0001" + +/* Length of a full path to an ACPI device */ +#define ACPI_PATH_MAX 30 + +/** + * acpi_device_name() - Locate and return the ACPI name for this device + * + * @dev: Device to check + * @name: Returns the character name, must be at least ACPI_NAME_MAX long + * @return 0 if OK, -ve on error + */ +int acpi_device_name(const struct udevice *dev, char *name); + +/** + * acpi_device_path() - Get the full path to an ACPI device + * + * This gets the full path in the form XXXX.YYYY.ZZZZ where XXXX is the root + * and ZZZZ is the device. All parent devices are added to the path. + * + * @dev: Device to check + * @buf: Buffer to place the path in (should be ACPI_PATH_MAX long) + * @maxlen: Size of buffer (typically ACPI_PATH_MAX) + * @return 0 if OK, -ve on error + */ +int acpi_device_path(const struct udevice *dev, char *buf, int maxlen); + +/** + * acpi_device_scope() - Get the scope of an ACPI device + * + * This gets the scope which is the full path of the parent device, as per + * acpi_device_path(). + * + * @dev: Device to check + * @buf: Buffer to place the path in (should be ACPI_PATH_MAX long) + * @maxlen: Size of buffer (typically ACPI_PATH_MAX) + * @return 0 if OK, -EINVAL if the device has no parent, other -ve on other + * error + */ +int acpi_device_scope(const struct udevice *dev, char *scope, int maxlen); + +/** + * acpi_device_status() - Get the status of a device + * + * This currently just returns ACPI_STATUS_DEVICE_ALL_ON. It does not support + * inactive or hidden devices. + * + * @dev: Device to check + * @return device status, as ACPI_STATUS_DEVICE_... + */ +int acpi_device_status(const struct udevice *dev); + +/** enum acpi_irq_mode - edge/level trigger mode */ +enum acpi_irq_mode { + ACPI_IRQ_EDGE_TRIGGERED, + ACPI_IRQ_LEVEL_TRIGGERED, +}; + +/** + * enum acpi_irq_polarity - polarity of interrupt + * + * @ACPI_IRQ_ACTIVE_LOW - for ACPI_IRQ_EDGE_TRIGGERED this means falling edge + * @ACPI_IRQ_ACTIVE_HIGH - for ACPI_IRQ_EDGE_TRIGGERED this means rising edge + * @ACPI_IRQ_ACTIVE_BOTH - not meaningful for ACPI_IRQ_EDGE_TRIGGERED + */ +enum acpi_irq_polarity { + ACPI_IRQ_ACTIVE_LOW, + ACPI_IRQ_ACTIVE_HIGH, + ACPI_IRQ_ACTIVE_BOTH, +}; + +/** + * enum acpi_irq_shared - whether interrupt is shared or not + * + * @ACPI_IRQ_EXCLUSIVE: only this device uses the interrupt + * @ACPI_IRQ_SHARED: other devices may use this interrupt + */ +enum acpi_irq_shared { + ACPI_IRQ_EXCLUSIVE, + ACPI_IRQ_SHARED, +}; + +/** enum acpi_irq_wake - indicates whether this interrupt can wake the device */ +enum acpi_irq_wake { + ACPI_IRQ_NO_WAKE, + ACPI_IRQ_WAKE, +}; + +/** + * struct acpi_irq - representation of an ACPI interrupt + * + * @pin: ACPI pin that is monitored for the interrupt + * @mode: Edge/level triggering + * @polarity: Interrupt polarity + * @shared: Whether interrupt is shared or not + * @wake: Whether interrupt can wake the device from sleep + */ +struct acpi_irq { + unsigned int pin; + enum acpi_irq_mode mode; + enum acpi_irq_polarity polarity; + enum acpi_irq_shared shared; + enum acpi_irq_wake wake; +}; + +/** + * enum acpi_gpio_type - type of the descriptor + * + * @ACPI_GPIO_TYPE_INTERRUPT: GpioInterrupt + * @ACPI_GPIO_TYPE_IO: GpioIo + */ +enum acpi_gpio_type { + ACPI_GPIO_TYPE_INTERRUPT, + ACPI_GPIO_TYPE_IO, +}; + +/** + * enum acpi_gpio_pull - pull direction + * + * @ACPI_GPIO_PULL_DEFAULT: Use default value for pin + * @ACPI_GPIO_PULL_UP: Pull up + * @ACPI_GPIO_PULL_DOWN: Pull down + * @ACPI_GPIO_PULL_NONE: No pullup/pulldown + */ +enum acpi_gpio_pull { + ACPI_GPIO_PULL_DEFAULT, + ACPI_GPIO_PULL_UP, + ACPI_GPIO_PULL_DOWN, + ACPI_GPIO_PULL_NONE, +}; + +/** + * enum acpi_gpio_io_restrict - controls input/output of pin + * + * @ACPI_GPIO_IO_RESTRICT_NONE: no restrictions + * @ACPI_GPIO_IO_RESTRICT_INPUT: input only (no output) + * @ACPI_GPIO_IO_RESTRICT_OUTPUT: output only (no input) + * @ACPI_GPIO_IO_RESTRICT_PRESERVE: preserve settings when driver not active + */ +enum acpi_gpio_io_restrict { + ACPI_GPIO_IO_RESTRICT_NONE, + ACPI_GPIO_IO_RESTRICT_INPUT, + ACPI_GPIO_IO_RESTRICT_OUTPUT, + ACPI_GPIO_IO_RESTRICT_PRESERVE, +}; + +/** enum acpi_gpio_polarity - controls the GPIO polarity */ +enum acpi_gpio_polarity { + ACPI_GPIO_ACTIVE_HIGH = 0, + ACPI_GPIO_ACTIVE_LOW = 1, +}; + +#define ACPI_GPIO_REVISION_ID 1 +#define ACPI_GPIO_MAX_PINS 2 + +/** + * struct acpi_gpio - representation of an ACPI GPIO + * + * @pin_count: Number of pins represented + * @pins: List of pins + * @type: GPIO type + * @pull: Pullup/pulldown setting + * @resource: Resource name for this GPIO controller + * For GpioInt: + * @interrupt_debounce_timeout: Debounce timeout in units of 10us + * @irq: Interrupt + * + * For GpioIo: + * @output_drive_strength: Drive strength in units of 10uA + * @io_shared; true if GPIO is shared + * @io_restrict: I/O restriction setting + * @polarity: GPIO polarity + */ +struct acpi_gpio { + int pin_count; + u16 pins[ACPI_GPIO_MAX_PINS]; + + enum acpi_gpio_type type; + enum acpi_gpio_pull pull; + char resource[ACPI_PATH_MAX]; + + /* GpioInt */ + u16 interrupt_debounce_timeout; + struct acpi_irq irq; + + /* GpioIo */ + u16 output_drive_strength; + bool io_shared; + enum acpi_gpio_io_restrict io_restrict; + enum acpi_gpio_polarity polarity; +}; + +/* ACPI Descriptors for Serial Bus interfaces */ +#define ACPI_SERIAL_BUS_TYPE_I2C 1 +#define ACPI_SERIAL_BUS_TYPE_SPI 2 +#define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */ +#define ACPI_I2C_TYPE_SPECIFIC_REVISION_ID 1 +#define ACPI_SPI_SERIAL_BUS_REVISION_ID 1 +#define ACPI_SPI_TYPE_SPECIFIC_REVISION_ID 1 + +/** + * struct acpi_gpio - representation of an ACPI I2C device + * + * @address: 7-bit or 10-bit I2C address + * @mode_10bit: Which address size is used + * @speed: Bus speed in Hz + * @resource: Resource name for the I2C controller + */ +struct acpi_i2c { + u16 address; + enum i2c_address_mode mode_10bit; + enum i2c_speed_rate speed; + const char *resource; +}; + +/** + * struct acpi_spi - representation of an ACPI SPI device + * + * @device_select: Chip select used by this device (typically 0) + * @device_select_polarity: Polarity for the device + * @wire_mode: Number of wires used for SPI + * @speed: Bus speed in Hz + * @data_bit_length: Word length for SPI (typically 8) + * @clock_phase: Clock phase to capture data + * @clock_polarity: Bus polarity + * @resource: Resource name for the SPI controller + */ +struct acpi_spi { + u16 device_select; + enum spi_polarity device_select_polarity; + enum spi_wire_mode wire_mode; + unsigned int speed; + u8 data_bit_length; + enum spi_clock_phase clock_phase; + enum spi_polarity clock_polarity; + const char *resource; +}; + +/** + * struct acpi_power_res_params - power on/off sequence information + * + * This provides GPIOs and timing information for powering a device on and off. + * This can be applied to any device that has power control, so is fairly + * generic. + * + * @reset_gpio: GPIO used to take device out of reset or to put it into reset + * @reset_delay_ms: Delay to be inserted after device is taken out of reset + * (_ON method delay) + * @reset_off_delay_ms: Delay to be inserted after device is put into reset + * (_OFF method delay) + * @enable_gpio: GPIO used to enable device + * @enable_delay_ms: Delay to be inserted after device is enabled + * @enable_off_delay_ms: Delay to be inserted after device is disabled + * (_OFF method delay) + * @stop_gpio: GPIO used to stop operation of device + * @stop_delay_ms: Delay to be inserted after disabling stop (_ON method delay) + * @stop_off_delay_ms: Delay to be inserted after enabling stop. + * (_OFF method delay) + */ +struct acpi_power_res_params { + struct acpi_gpio *reset_gpio; + unsigned int reset_delay_ms; + unsigned int reset_off_delay_ms; + struct acpi_gpio *enable_gpio; + unsigned int enable_delay_ms; + unsigned int enable_off_delay_ms; + struct acpi_gpio *stop_gpio; + unsigned int stop_delay_ms; + unsigned int stop_off_delay_ms; +}; + +/** + * struct acpi_dp - ACPI device properties + * + * Writing Device Properties objects via _DSD + * + * This provides a structure to handle nested device-specific data which ends + * up in a _DSD table. + * + * https://www.kernel.org/doc/html/latest/firmware-guide/acpi/DSD-properties-ru... + * https://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.p... + * https://uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extens... + * + * The Device Property Hierarchy can be multiple levels deep with multiple + * children possible in each level. In order to support this flexibility + * the device property hierarchy must be built up before being written out. + * + * For example: + * + * // Child table with string and integer + * struct acpi_dp *child = acpi_dp_new_table("CHLD"); + * acpi_dp_add_string(child, "childstring", "CHILD"); + * acpi_dp_add_integer(child, "childint", 100); + * + * // _DSD table with integer and gpio and child pointer + * struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + * acpi_dp_add_integer(dsd, "number1", 1); + * acpi_dp_add_gpio(dsd, "gpio", "_SB.PCI0.GPIO", 0, 0, 1); + * acpi_dp_add_child(dsd, "child", child); + * + * // Write entries into SSDT and clean up resources + * acpi_dp_write(dsd); + * + * Name(_DSD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "gpio", Package() { _SB.PCI0.GPIO, 0, 0, 0 } } + * Package() { "number1", 1 } + * } + * ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") + * Package() { + * Package() { "child", CHLD } + * } + * } + * Name(CHLD, Package() { + * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + * Package() { + * Package() { "childstring", "CHILD" } + * Package() { "childint", 100 } + * } + * } + * + * @type: Table type + * @name: Name of object, typically _DSD but could be CHLD for a child object + * @next: Next object in list (next array element or next sibling) + * @child: Pointer to first child, if @type == ACPI_DP_TYPE_CHILD, else NULL + * @array: First array element, if @type == ACPI_DP_TYPE_ARRAY, else NULL + * @integer: Integer value of the property, if @type == ACPI_DP_TYPE_INTEGER + * @string: String value of the property, if @type == ACPI_DP_TYPE_STRING; + * child name if @type == ACPI_DP_TYPE_CHILD; + * reference name if @type == ACPI_DP_TYPE_REFERENCE; + */ +struct acpi_dp { + enum acpi_dp_type type; + const char *name; + struct acpi_dp *next; + union { + struct acpi_dp *child; + struct acpi_dp *array; + }; + union { + u64 integer; + const char *string; + }; +}; + +/** + * acpi_dp_new_table() - Start a new Device Property table + * + * @ref: ACPI reference (e.g. "_DSD") + * @return pointer to table, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_new_table(const char *ref); + +/** + * acpi_dp_add_integer() - Add integer Device Property + * + * A new node is added to the end of the property list of @dp + * + * @dp: Table to add this property to + * @name: Name of property + * @value: Integer value + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, + u64 value); + +/** + * acpi_dp_add_string() - Add string Device Property + * + * A new node is added to the end of the property list of @dp + * + * @dp: Table to add this property to + * @name: Name of property + * @string: String value + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, + const char *string); + +/** + * acpi_dp_add_reference() - Add reference Device Property + * + * A new node is added to the end of the property list of @dp + * + * @dp: Table to add this property to + * @name: Name of property + * @reference: Reference value + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, + const char *reference); + +/** + * acpi_dp_add_array() - Add array Device Property + * + * A new node is added to the end of the property list of @dp, with the array + * attached to that. + * + * @dp: Table to add this property to + * @name: Name of property + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array); + +/** + * acpi_dp_add_integer_array() - Add an array of integers + * + * A new node is added to the end of the property list of @dp, with the array + * attached to that. Each element of the array becomes a new node. + * + * @dp: Table to add this property to + * @name: Name of property + * @return pointer to new array node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, + u64 *array, int len); + +/** + * acpi_dp_add_gpio() - Add a GPIO binding Device Property + * + * A new node is added to the end of the property list of @dp, with the + * GPIO properties added to the the new node + * + * @dp: Table to add this property to + * @name: Name of property + * @ref: Reference of the device that has _CRS containing GpioIO()/GpioInt() + * @index: Index of the GPIO resource in _CRS starting from zero + * @pin: Pin in the GPIO resource, typically zero + * @active_low: true if pin is active low + * @return pointer to new node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + bool active_low); + +/** + * acpi_dp_add_child() - Add a child table of Device Properties + * + * A new node is added as a child of @dp + * + * @dp: Table to add this child to + * @name: Name of child + * @child: Child node to add + * @return pointer to new array node, or NULL if out of memory + */ +struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, + struct acpi_dp *child); + +/** + * acpi_dp_add_property_list() - Add a list of of Device Properties + * + * This adds a list of properties to @dp. Any properties without a name or of + * type ACPI_DP_TYPE_UNKNOWN are ignored. + * + * @dp: Table to add properties to + * @property_list: List of properties to add + * @property_count: Number of properties in the list + * @return number of properties added + */ +size_t acpi_dp_add_property_list(struct acpi_dp *dp, + const struct acpi_dp *property_list, + size_t property_count); + +/** + * acpi_dp_write() - Write Device Property hierarchy and clean up resources + * + * This writes the table using acpigen and then frees it + * + * @table: Table to write + * @return 0 if OK, -ve on error + */ +int acpi_dp_write(struct acpi_ctx *ctx, struct acpi_dp *table); + +/** + * acpi_device_write_i2c_dev() - Write an I2C device to ACPI, including + * information ACPI needs to use it. + * + * This writes a serial bus descriptor for the I2C device so that ACPI can + */ +int acpi_device_write_i2c_dev(struct acpi_ctx *ctx, const struct udevice *dev); + +/** + * struct acpi_i2c_priv - Information read from device tree + * + * This is used by devices which want to specify various pieces of ACPI + * information, including power control. It allows a generic function to + * generate the information for ACPI, based on device-tree properties. + * + * @disable_gpio_export_in_crs: Don't export GPIOs in the CRS + * @reset_gpio: GPIO used to assert reset to the device + * @enable_gpio: GPIO used to enable the device + * @stop_gpio: GPIO used to stop the device + * @irq_gpio: GPIO used for interrupt (if @irq is not used) + * @irq: IRQ used for interrupt (if @irq_gpio is not used) + * @hid: _HID value for device (required) + * @cid: _CID value for device + * @uid: _UID value for device + * @desc: _DDN value for device + * @wake: Wake event, e.g. GPE0_DW1_15; 0 if none + * @property_count: Number of other DSD properties (currently always 0) + * @probed: true set set 'linux,probed' property + * @compat_string: Device tree compatible string to report through ACPI + * @has_power_resource: true if this device has a power resource + * @reset_delay_ms: Delay after de-asserting reset, in ms + * @reset_off_delay_ms: Delay after asserting reset (during power off) + * @enable_delay_ms: Delay after asserting enable + * @enable_off_delay_ms: Delay after de-asserting enable (during power off) + * @stop_delay_ms: Delay after de-aserting stop + * @stop_off_delay_ms: Delay after asserting stop (during power off) + * @hid_desc_reg_offset: HID register offset (for Human Interface Devices) + */ +struct acpi_i2c_priv { + bool disable_gpio_export_in_crs; + struct gpio_desc reset_gpio; + struct gpio_desc enable_gpio; + struct gpio_desc irq_gpio; + struct gpio_desc stop_gpio; + struct irq irq; + const char *hid; + const char *cid; + u32 uid; + const char *desc; + u32 wake; + u32 property_count; + bool probed; + const char *compat_string; + bool has_power_resource; + u32 reset_delay_ms; + u32 reset_off_delay_ms; + u32 enable_delay_ms; + u32 enable_off_delay_ms; + u32 stop_delay_ms; + u32 stop_off_delay_ms; + u32 hid_desc_reg_offset; +}; + +/** + * I2C Human-Interface Devices configuration + * + * @hid_desc_reg_offset: HID register offset + */ +struct dsm_i2c_hid_config { + u8 hid_desc_reg_offset; +}; + +/** + * acpi_device_write_gpio() - Write GpioIo() or GpioInt() descriptor + * + * @gpio: GPIO information to write + * @return 0 if OK, -ve on error + */ +int acpi_device_write_gpio(struct acpi_ctx *ctx, const struct acpi_gpio *gpio); + +/* + * acpi_device_add_power_res() - Add a basic PowerResource block for a device + * + * This includes GPIOs to control enable, reset and stop operation of the + * device. Each GPIO is optional, but at least one must be provided. + * + * Reset - Put the device into / take the device out of reset. + * Enable - Enable / disable power to device. + * Stop - Stop / start operation of device. + * + * @return 0 if OK, -ve if at least one GPIO is not provided + */ +int acpi_device_add_power_res(struct acpi_ctx *ctx, + const struct acpi_power_res_params *params); + +/** + * gpio_get_acpi() - Convert a GPIO description into an ACPI GPIO + * + * At present this is fairly limited. It only supports ACPI_GPIO_TYPE_IO and + * has hard-coded settings for type, pull, IO restrict and polarity. These + * could come from pinctrl potentially. + * + * @desc: GPIO description to convert + * @gpio: Place to put ACPI GPIO information + * @return 0 if OK, -ENOENT if @desc is invalid + */ +int gpio_get_acpi(const struct gpio_desc *desc, struct acpi_gpio *gpio); + +/** + * acpi_device_write_dsm_i2c_hid() - Write a device-specific method for HID + * + * This writes a DSM for an I2C Human-Interface Device based on the config + * provided + * + * @config: Config information to write + */ +void acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx, + struct dsm_i2c_hid_config *config); + +/** + * acpi_dp_ofnode_copy_int() - Copy a property from device tree to DP + * + * This copies an integer property from the device tree to the ACPI DP table. + * + * @dev: Device to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_ofnode_copy_int(ofnode node, struct acpi_dp *dp, const char *prop); + +/** + * acpi_dp_dev_copy_str() - Copy a property from device tree to DP + * + * This copies a string property from the device tree to the ACPI DP table. + * + * @dev: Device to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_ofnode_copy_str(ofnode node, struct acpi_dp *dp, const char *prop); + +/** + * acpi_dp_dev_copy_int() - Copy a property from device tree to DP + * + * This copies an integer property from the device tree to the ACPI DP table. + * + * @dev: Device to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_dev_copy_int(const struct udevice *dev, struct acpi_dp *dp, + const char *prop); + +/** + * acpi_dp_dev_copy_str() - Copy a property from device tree to DP + * + * This copies a string property from the device tree to the ACPI DP table. + * + * @dev: Device to copy from + * @dp: DP to copy to + * @prop: Property name to copy + * @return 0 if OK, -ve on error + */ +int acpi_dp_dev_copy_str(const struct udevice *dev, struct acpi_dp *dp, + const char *prop); + +int acpi_device_get_name(const struct udevice *dev, char *out_name); + +#endif diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c new file mode 100644 index 0000000000..2d03639714 --- /dev/null +++ b/lib/acpi/acpi_device.c @@ -0,0 +1,1093 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Generation of tables for particular device types + * + * Copyright 2019 Google LLC + * Mostly taken from coreboot file of the same name + */ + +#include <common.h> +#include <acpi_device.h> +#include <acpigen.h> +#include <dm.h> +#include <irq.h> +#include <usb.h> +#include <asm-generic/gpio.h> +#include <dm/acpi.h> + +#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301" +#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b" +#define ACPI_DSM_I2C_HID_UUID "3cdff6f7-4267-4555-ad05-b30a3d8938de" + +/** + * acpi_device_write_zero_len() - Write a placeholder word value + * + * @return pointer to the zero word (for fixing up later) + */ +static void *acpi_device_write_zero_len(struct acpi_ctx *ctx) +{ + char *p = acpigen_get_current(ctx); + + acpigen_emit_word(ctx, 0); + + return p; +} + +/** + * acpi_device_fill_from_len() - Fill in a length value + * + * This calculated the number of bytes since the provided @start and writes it + * to @ptr, which was previous returned by acpi_device_write_zero_len(). + * + * @ptr: Word to update + * @start: Start address to count from to calculated the length + */ +static void acpi_device_fill_from_len(struct acpi_ctx *ctx, char *ptr, + char *start) +{ + u16 len = acpigen_get_current(ctx) - start; + + ptr[0] = len & 0xff; + ptr[1] = (len >> 8) & 0xff; +} + +/** + * acpi_device_fill_len() - Fill in a length value, excluding the length itself + * + * Fill in the length field with the value calculated from after the 16bit + * field to acpigen current. This is useful since the length value does not + * include the length field itself. + * + * This calls acpi_device_fill_from_len() passing @ptr + 2 as @start + * + * @ptr: Word to update. + */ +static void acpi_device_fill_len(struct acpi_ctx *ctx, void *ptr) +{ + acpi_device_fill_from_len(ctx, ptr, ptr + sizeof(u16)); +} + +int acpi_device_name(const struct udevice *dev, char *name) +{ + int ret; + + ret = acpi_get_name(dev, name); + if (ret) + return log_msg_ret("name", ret); + + return 0; +} + +/** + * acpi_device_path_fill() - Find the root device and build a path from there + * + * This recursively reaches back to the root device and progressively adds path + * elements until the device is reached. + * + * @dev: Device to return path of + * @buf: Buffer to hold the path + * @buf_len: Length of buffer + * @cur: Current position in the buffer + * @return new position in buffer after adding @dev, or -ve on error + */ +static int acpi_device_path_fill(const struct udevice *dev, char *buf, + size_t buf_len, int cur) +{ + char name[ACPI_NAME_MAX]; + int next = 0; + int ret; + + ret = acpi_device_name(dev, name); + if (ret) + return ret; + + /* + * Make sure this name segment will fit, including the path segment + * separator and possible NUL terminator if this is the last segment. + */ + if (!dev || (cur + strlen(name) + 2) > buf_len) + return cur; + + /* Walk up the tree to the root device */ + if (dev_get_parent(dev)) { + next = acpi_device_path_fill(dev_get_parent(dev), buf, buf_len, + cur); + if (next < 0) + return next; + } + + /* Fill in the path from the root device */ + next += snprintf(buf + next, buf_len - next, "%s%s", + dev_get_parent(dev) && *name ? "." : "", name); + + return next; +} + +int acpi_device_path(const struct udevice *dev, char *buf, int maxlen) +{ + int ret; + + ret = acpi_device_path_fill(dev, buf, maxlen, 0); + if (ret < 0) + return ret; + + return 0; +} + +int acpi_device_scope(const struct udevice *dev, char *scope, int maxlen) +{ + int ret; + + if (!dev_get_parent(dev)) + return log_msg_ret("noparent", -EINVAL); + + ret = acpi_device_path_fill(dev_get_parent(dev), scope, maxlen, 0); + if (ret < 0) + return log_msg_ret("fill", ret); + + return 0; +} + +int acpi_device_status(const struct udevice *dev) +{ + return ACPI_STATUS_DEVICE_ALL_ON; +} + +/* ACPI 6.1 section 6.4.3.8.1 - GPIO Interrupt or I/O */ +int acpi_device_write_gpio(struct acpi_ctx *ctx, const struct acpi_gpio *gpio) +{ + void *start, *desc_length; + void *pin_table_offset, *vendor_data_offset, *resource_offset; + u16 flags = 0; + int pin; + + if (!gpio || gpio->type > ACPI_GPIO_TYPE_IO) + return -EINVAL; + + start = acpigen_get_current(ctx); + + /* Byte 0: Descriptor Type */ + acpigen_emit_byte(ctx, ACPI_DESCRIPTOR_GPIO); + + /* Byte 1-2: Length (fill in later) */ + desc_length = acpi_device_write_zero_len(ctx); + + /* Byte 3: Revision ID */ + acpigen_emit_byte(ctx, ACPI_GPIO_REVISION_ID); + + /* Byte 4: GpioIo or GpioInt */ + acpigen_emit_byte(ctx, gpio->type); + + /* + * Byte 5-6: General Flags + * [15:1]: 0 => Reserved + * [0]: 1 => ResourceConsumer + */ + acpigen_emit_word(ctx, 1 << 0); + + switch (gpio->type) { + case ACPI_GPIO_TYPE_INTERRUPT: + /* + * Byte 7-8: GPIO Interrupt Flags + * [15:5]: 0 => Reserved + * [4]: Wake (0=NO_WAKE 1=WAKE) + * [3]: Sharing (0=EXCLUSIVE 1=SHARED) + * [2:1]: Polarity (0=HIGH 1=LOW 2=BOTH) + * [0]: Mode (0=LEVEL 1=EDGE) + */ + if (gpio->irq.mode == ACPI_IRQ_EDGE_TRIGGERED) + flags |= 1 << 0; + if (gpio->irq.shared == ACPI_IRQ_SHARED) + flags |= 1 << 3; + if (gpio->irq.wake == ACPI_IRQ_WAKE) + flags |= 1 << 4; + + switch (gpio->irq.polarity) { + case ACPI_IRQ_ACTIVE_HIGH: + flags |= 0 << 1; + break; + case ACPI_IRQ_ACTIVE_LOW: + flags |= 1 << 1; + break; + case ACPI_IRQ_ACTIVE_BOTH: + flags |= 2 << 1; + break; + } + break; + + case ACPI_GPIO_TYPE_IO: + /* + * Byte 7-8: GPIO IO Flags + * [15:4]: 0 => Reserved + * [3]: Sharing (0=EXCLUSIVE 1=SHARED) + * [2]: 0 => Reserved + * [1:0]: IO Restriction + * 0 => IoRestrictionNone + * 1 => IoRestrictionInputOnly + * 2 => IoRestrictionOutputOnly + * 3 => IoRestrictionNoneAndPreserve + */ + flags |= gpio->io_restrict & 3; + if (gpio->io_shared) + flags |= 1 << 3; + break; + } + acpigen_emit_word(ctx, flags); + + /* + * Byte 9: Pin Configuration + * 0x01 => Default (no configuration applied) + * 0x02 => Pull-up + * 0x03 => Pull-down + * 0x04-0x7F => Reserved + * 0x80-0xff => Vendor defined + */ + acpigen_emit_byte(ctx, gpio->pull); + + /* Byte 10-11: Output Drive Strength in 1/100 mA */ + acpigen_emit_word(ctx, gpio->output_drive_strength); + + /* Byte 12-13: Debounce Timeout in 1/100 ms */ + acpigen_emit_word(ctx, gpio->interrupt_debounce_timeout); + + /* Byte 14-15: Pin Table Offset, relative to start */ + pin_table_offset = acpi_device_write_zero_len(ctx); + + /* Byte 16: Reserved */ + acpigen_emit_byte(ctx, 0); + + /* Byte 17-18: Resource Source Name Offset, relative to start */ + resource_offset = acpi_device_write_zero_len(ctx); + + /* Byte 19-20: Vendor Data Offset, relative to start */ + vendor_data_offset = acpi_device_write_zero_len(ctx); + + /* Byte 21-22: Vendor Data Length */ + acpigen_emit_word(ctx, 0); + + /* Fill in Pin Table Offset */ + acpi_device_fill_from_len(ctx, pin_table_offset, start); + + /* Pin Table, one word for each pin */ + for (pin = 0; pin < gpio->pin_count; pin++) + acpigen_emit_word(ctx, gpio->pins[pin]); + + /* Fill in Resource Source Name Offset */ + acpi_device_fill_from_len(ctx, resource_offset, start); + + /* Resource Source Name String */ + acpigen_emit_string(ctx, gpio->resource); + + /* Fill in Vendor Data Offset */ + acpi_device_fill_from_len(ctx, vendor_data_offset, start); + + /* Fill in GPIO Descriptor Length (account for len word) */ + acpi_device_fill_len(ctx, desc_length); + + return 0; +} + +/* ACPI 6.1 section 6.4.3.8.2.1 - I2cSerialBus() */ +static void acpi_device_write_i2c(struct acpi_ctx *ctx, + const struct acpi_i2c *i2c) +{ + void *desc_length, *type_length; + + /* Byte 0: Descriptor Type */ + acpigen_emit_byte(ctx, ACPI_DESCRIPTOR_SERIAL_BUS); + + /* Byte 1+2: Length (filled in later) */ + desc_length = acpi_device_write_zero_len(ctx); + + /* Byte 3: Revision ID */ + acpigen_emit_byte(ctx, ACPI_I2C_SERIAL_BUS_REVISION_ID); + + /* Byte 4: Resource Source Index is Reserved */ + acpigen_emit_byte(ctx, 0); + + /* Byte 5: Serial Bus Type is I2C */ + acpigen_emit_byte(ctx, ACPI_SERIAL_BUS_TYPE_I2C); + + /* + * Byte 6: Flags + * [7:2]: 0 => Reserved + * [1]: 1 => ResourceConsumer + * [0]: 0 => ControllerInitiated + */ + acpigen_emit_byte(ctx, 1 << 1); + + /* + * Byte 7-8: Type Specific Flags + * [15:1]: 0 => Reserved + * [0]: 0 => 7bit, 1 => 10bit + */ + acpigen_emit_word(ctx, i2c->mode_10bit); + + /* Byte 9: Type Specific Revision ID */ + acpigen_emit_byte(ctx, ACPI_I2C_TYPE_SPECIFIC_REVISION_ID); + + /* Byte 10-11: I2C Type Data Length */ + type_length = acpi_device_write_zero_len(ctx); + + /* Byte 12-15: I2C Bus Speed */ + acpigen_emit_dword(ctx, i2c->speed); + + /* Byte 16-17: I2C Slave Address */ + acpigen_emit_word(ctx, i2c->address); + + /* Fill in Type Data Length */ + acpi_device_fill_len(ctx, type_length); + + /* Byte 18+: ResourceSource */ + acpigen_emit_string(ctx, i2c->resource); + + /* Fill in I2C Descriptor Length */ + acpi_device_fill_len(ctx, desc_length); +} + +/* ACPI 6.1 section 6.4.3.8.2.2 - SpiSerialBus() */ +void acpi_device_write_spi(struct acpi_ctx *ctx, const struct acpi_spi *spi) +{ + void *desc_length, *type_length; + u16 flags = 0; + + /* Byte 0: Descriptor Type */ + acpigen_emit_byte(ctx, ACPI_DESCRIPTOR_SERIAL_BUS); + + /* Byte 1+2: Length (filled in later) */ + desc_length = acpi_device_write_zero_len(ctx); + + /* Byte 3: Revision ID */ + acpigen_emit_byte(ctx, ACPI_SPI_SERIAL_BUS_REVISION_ID); + + /* Byte 4: Resource Source Index is Reserved */ + acpigen_emit_byte(ctx, 0); + + /* Byte 5: Serial Bus Type is SPI */ + acpigen_emit_byte(ctx, ACPI_SERIAL_BUS_TYPE_SPI); + + /* + * Byte 6: Flags + * [7:2]: 0 => Reserved + * [1]: 1 => ResourceConsumer + * [0]: 0 => ControllerInitiated + */ + acpigen_emit_byte(ctx, 1 << 1); + + /* + * Byte 7-8: Type Specific Flags + * [15:2]: 0 => Reserveda + * [1]: 0 => ActiveLow, 1 => ActiveHigh + * [0]: 0 => FourWire, 1 => ThreeWire + */ + if (spi->wire_mode == SPI_3_WIRE_MODE) + flags |= 1 << 0; + if (spi->device_select_polarity == SPI_POLARITY_HIGH) + flags |= 1 << 1; + acpigen_emit_word(ctx, flags); + + /* Byte 9: Type Specific Revision ID */ + acpigen_emit_byte(ctx, ACPI_SPI_TYPE_SPECIFIC_REVISION_ID); + + /* Byte 10-11: SPI Type Data Length */ + type_length = acpi_device_write_zero_len(ctx); + + /* Byte 12-15: Connection Speed */ + acpigen_emit_dword(ctx, spi->speed); + + /* Byte 16: Data Bit Length */ + acpigen_emit_byte(ctx, spi->data_bit_length); + + /* Byte 17: Clock Phase */ + acpigen_emit_byte(ctx, spi->clock_phase); + + /* Byte 18: Clock Polarity */ + acpigen_emit_byte(ctx, spi->clock_polarity); + + /* Byte 19-20: Device Selection */ + acpigen_emit_word(ctx, spi->device_select); + + /* Fill in Type Data Length */ + acpi_device_fill_len(ctx, type_length); + + /* Byte 21+: ResourceSource String */ + acpigen_emit_string(ctx, spi->resource); + + /* Fill in SPI Descriptor Length */ + acpi_device_fill_len(ctx, desc_length); +} + +/* PowerResource() with Enable and/or Reset control */ +int acpi_device_add_power_res(struct acpi_ctx *ctx, + const struct acpi_power_res_params *params) +{ + static const char *const power_res_dev_states[] = { "_PR0", "_PR3" }; + unsigned int reset_gpio = params->reset_gpio->pins[0]; + unsigned int enable_gpio = params->enable_gpio->pins[0]; + unsigned int stop_gpio = params->stop_gpio->pins[0]; + int ret; + + if (!reset_gpio && !enable_gpio && !stop_gpio) + return -EINVAL; + + /* PowerResource (PRIC, 0, 0) */ + acpigen_write_power_res(ctx, "PRIC", 0, 0, power_res_dev_states, + ARRAY_SIZE(power_res_dev_states)); + + /* Method (_STA, 0, NotSerialized) { Return (0x1) } */ + acpigen_write_sta(ctx, 0x1); + + /* Method (_ON, 0, Serialized) */ + acpigen_write_method_serialized(ctx, "_ON", 0); + if (reset_gpio) { + ret = acpigen_enable_tx_gpio(ctx, params->reset_gpio); + if (ret) + return log_msg_ret("reset1", ret); + } + if (enable_gpio) { + ret = acpigen_enable_tx_gpio(ctx, params->enable_gpio); + if (ret) + return log_msg_ret("enable1", ret); + if (params->enable_delay_ms) + acpigen_write_sleep(ctx, params->enable_delay_ms); + } + if (reset_gpio) { + ret = acpigen_disable_tx_gpio(ctx, params->reset_gpio); + if (ret) + return log_msg_ret("reset2", ret); + if (params->reset_delay_ms) + acpigen_write_sleep(ctx, params->reset_delay_ms); + } + if (stop_gpio) { + ret = acpigen_disable_tx_gpio(ctx, params->stop_gpio); + if (ret) + return log_msg_ret("stop1", ret); + if (params->stop_delay_ms) + acpigen_write_sleep(ctx, params->stop_delay_ms); + } + acpigen_pop_len(ctx); /* _ON method */ + + /* Method (_OFF, 0, Serialized) */ + acpigen_write_method_serialized(ctx, "_OFF", 0); + if (stop_gpio) { + ret = acpigen_enable_tx_gpio(ctx, params->stop_gpio); + if (ret) + return log_msg_ret("stop2", ret); + if (params->stop_off_delay_ms) + acpigen_write_sleep(ctx, params->stop_off_delay_ms); + } + if (reset_gpio) { + ret = acpigen_enable_tx_gpio(ctx, params->reset_gpio); + if (ret) + return log_msg_ret("reset3", ret); + if (params->reset_off_delay_ms) + acpigen_write_sleep(ctx, params->reset_off_delay_ms); + } + if (enable_gpio) { + ret = acpigen_disable_tx_gpio(ctx, params->enable_gpio); + if (ret) + return log_msg_ret("enable2", ret); + if (params->enable_off_delay_ms) + acpigen_write_sleep(ctx, params->enable_off_delay_ms); + } + acpigen_pop_len(ctx); /* _OFF method */ + + acpigen_pop_len(ctx); /* PowerResource PRIC */ + + return 0; +} + +static void acpi_dp_write_array(struct acpi_ctx *ctx, + const struct acpi_dp *array); + +static void acpi_dp_write_value(struct acpi_ctx *ctx, + const struct acpi_dp *prop) +{ + switch (prop->type) { + case ACPI_DP_TYPE_INTEGER: + acpigen_write_integer(ctx, prop->integer); + break; + case ACPI_DP_TYPE_STRING: + case ACPI_DP_TYPE_CHILD: + acpigen_write_string(ctx, prop->string); + break; + case ACPI_DP_TYPE_REFERENCE: + acpigen_emit_namestring(ctx, prop->string); + break; + case ACPI_DP_TYPE_ARRAY: + acpi_dp_write_array(ctx, prop->array); + break; + default: + break; + } +} + +/* Package (2) { "prop->name", VALUE } */ +static void acpi_dp_write_property(struct acpi_ctx *ctx, + const struct acpi_dp *prop) +{ + acpigen_write_package(ctx, 2); + acpigen_write_string(ctx, prop->name); + acpi_dp_write_value(ctx, prop); + acpigen_pop_len(ctx); +} + +/* Write array of Device Properties */ +static void acpi_dp_write_array(struct acpi_ctx *ctx, + const struct acpi_dp *array) +{ + const struct acpi_dp *dp; + char *pkg_count; + + /* Package element count determined as it is populated */ + pkg_count = acpigen_write_package(ctx, 0); + + /* + * Only acpi_dp of type DP_TYPE_TABLE is allowed to be an array. + * DP_TYPE_TABLE does not have a value to be written. Thus, start + * the loop from next type in the array. + */ + for (dp = array->next; dp; dp = dp->next) { + acpi_dp_write_value(ctx, dp); + (*pkg_count)++; + } + + acpigen_pop_len(ctx); +} + +static void acpi_dp_free(struct acpi_dp *dp) +{ + while (dp) { + struct acpi_dp *p = dp->next; + + switch (dp->type) { + case ACPI_DP_TYPE_CHILD: + acpi_dp_free(dp->child); + break; + case ACPI_DP_TYPE_ARRAY: + acpi_dp_free(dp->array); + break; + default: + break; + } + + free(dp); + dp = p; + } +} + +int acpi_dp_write(struct acpi_ctx *ctx, struct acpi_dp *table) +{ + struct acpi_dp *dp, *prop; + char *dp_count, *prop_count = NULL; + int child_count = 0; + int ret; + + if (!table || table->type != ACPI_DP_TYPE_TABLE) + return 0; + + /* Name (name) */ + acpigen_write_name(ctx, table->name); + + /* Device Property list starts with the next entry */ + prop = table->next; + + /* Package (DP), default to assuming no properties or children */ + dp_count = acpigen_write_package(ctx, 0); + + /* Print base properties */ + for (dp = prop; dp; dp = dp->next) { + if (dp->type == ACPI_DP_TYPE_CHILD) { + child_count++; + } else { + /* + * The UUID and package is only added when + * we come across the first property. This + * is to avoid creating a zero-length package + * in situations where there are only children. + */ + if (!prop_count) { + *dp_count += 2; + /* ToUUID (ACPI_DP_UUID) */ + ret = acpigen_write_uuid(ctx, ACPI_DP_UUID); + if (ret) + return log_msg_ret("touuid", ret); + /* + * Package (PROP), element count determined as + * it is populated + */ + prop_count = acpigen_write_package(ctx, 0); + } + (*prop_count)++; + acpi_dp_write_property(ctx, dp); + } + } + + if (prop_count) { + /* Package (PROP) length, if a package was written */ + acpigen_pop_len(ctx); + } + + if (child_count) { + /* Update DP package count to 2 or 4 */ + *dp_count += 2; + /* ToUUID (ACPI_DP_CHILD_UUID) */ + ret = acpigen_write_uuid(ctx, ACPI_DP_CHILD_UUID); + if (ret) + return log_msg_ret("child uuid", ret); + + /* Print child pointer properties */ + acpigen_write_package(ctx, child_count); + + for (dp = prop; dp; dp = dp->next) + if (dp->type == ACPI_DP_TYPE_CHILD) + acpi_dp_write_property(ctx, dp); + /* Package (CHILD) length */ + acpigen_pop_len(ctx); + } + + /* Package (DP) length */ + acpigen_pop_len(ctx); + + /* Recursively parse children into separate tables */ + for (dp = prop; dp; dp = dp->next) { + if (dp->type == ACPI_DP_TYPE_CHILD) { + ret = acpi_dp_write(ctx, dp->child); + if (ret) + return log_msg_ret("dp child", ret); + } + } + + /* Clean up */ + acpi_dp_free(table); + + return 0; +} + +static struct acpi_dp *acpi_dp_new(struct acpi_dp *dp, enum acpi_dp_type type, + const char *name) +{ + struct acpi_dp *new; + + new = malloc(sizeof(struct acpi_dp)); + if (!new) + return NULL; + + memset(new, '\0', sizeof(*new)); + new->type = type; + new->name = name; + + if (dp) { + /* Add to end of property list */ + while (dp->next) + dp = dp->next; + dp->next = new; + } + + return new; +} + +struct acpi_dp *acpi_dp_new_table(const char *name) +{ + return acpi_dp_new(NULL, ACPI_DP_TYPE_TABLE, name); +} + +size_t acpi_dp_add_property_list(struct acpi_dp *dp, + const struct acpi_dp *property_list, + size_t property_count) +{ + const struct acpi_dp *prop; + size_t i, properties_added = 0; + + if (!dp || !property_list) + return 0; + + for (i = 0; i < property_count; i++) { + prop = &property_list[i]; + + if (prop->type == ACPI_DP_TYPE_UNKNOWN || !prop->name) + continue; + + switch (prop->type) { + case ACPI_DP_TYPE_INTEGER: + acpi_dp_add_integer(dp, prop->name, prop->integer); + break; + case ACPI_DP_TYPE_STRING: + acpi_dp_add_string(dp, prop->name, prop->string); + break; + case ACPI_DP_TYPE_REFERENCE: + acpi_dp_add_reference(dp, prop->name, prop->string); + break; + case ACPI_DP_TYPE_ARRAY: + acpi_dp_add_array(dp, prop->array); + break; + case ACPI_DP_TYPE_CHILD: + acpi_dp_add_child(dp, prop->name, prop->child); + break; + default: + continue; + } + + ++properties_added; + } + + return properties_added; +} + +struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, + u64 value) +{ + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_INTEGER, name); + + if (new) + new->integer = value; + + return new; +} + +struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, + const char *string) +{ + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_STRING, name); + + if (new) + new->string = string; + + return new; +} + +struct acpi_dp *acpi_dp_add_reference(struct acpi_dp *dp, const char *name, + const char *reference) +{ + if (!dp) + return NULL; + + struct acpi_dp *new = acpi_dp_new(dp, ACPI_DP_TYPE_REFERENCE, name); + + if (new) + new->string = reference; + + return new; +} + +struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, + struct acpi_dp *child) +{ + struct acpi_dp *new; + + if (!dp || !child || child->type != ACPI_DP_TYPE_TABLE) + return NULL; + + new = acpi_dp_new(dp, ACPI_DP_TYPE_CHILD, name); + if (new) { + new->child = child; + new->string = child->name; + } + + return new; +} + +struct acpi_dp *acpi_dp_add_array(struct acpi_dp *dp, struct acpi_dp *array) +{ + struct acpi_dp *new; + + if (!dp || !array || array->type != ACPI_DP_TYPE_TABLE) + return NULL; + + new = acpi_dp_new(dp, ACPI_DP_TYPE_ARRAY, array->name); + if (new) + new->array = array; + + return new; +} + +struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, + u64 *array, int len) +{ + struct acpi_dp *dp_array; + int i; + + if (!dp || len <= 0) + return NULL; + + dp_array = acpi_dp_new_table(name); + if (!dp_array) + return NULL; + + for (i = 0; i < len; i++) + if (!acpi_dp_add_integer(dp_array, NULL, array[i])) + break; + + acpi_dp_add_array(dp, dp_array); + + return dp_array; +} + +struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, + const char *ref, int index, int pin, + bool active_low) +{ + if (!dp) + return NULL; + + struct acpi_dp *gpio = acpi_dp_new_table(name); + + if (!gpio) + return NULL; + + /* The device that has _CRS containing GpioIO()/GpioInt() */ + acpi_dp_add_reference(gpio, NULL, ref); + + /* Index of the GPIO resource in _CRS starting from zero */ + acpi_dp_add_integer(gpio, NULL, index); + + /* Pin in the GPIO resource, typically zero */ + acpi_dp_add_integer(gpio, NULL, pin); + + /* Set if pin is active low */ + acpi_dp_add_integer(gpio, NULL, active_low); + + acpi_dp_add_array(dp, gpio); + + return gpio; +} + +/** + * acpi_device_set_i2c() - Set up an ACPI I2C struct from a device + * + * @dev: I2C device to convert + * @i2c: Place to put the new structure + * @scope: Scope of the I2C device (this is the controller path) + * @return 0 (always) + */ +static int acpi_device_set_i2c(const struct udevice *dev, struct acpi_i2c *i2c, + const char *scope) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + + memset(i2c, '\0', sizeof(i2c)); + i2c->address = chip->chip_addr; + i2c->mode_10bit = 0; + + /* + * i2c_bus->speed_hz is set if this device is probed, but if not we + * must use the device tree + */ + i2c->speed = dev_read_u32_default(bus, "clock-frequency", 100000); + i2c->resource = scope; + + return 0; +} + +int acpi_device_write_i2c_dev(struct acpi_ctx *ctx, const struct udevice *dev) +{ + char scope[ACPI_PATH_MAX]; + struct acpi_i2c i2c; + int ret; + + ret = acpi_device_scope(dev, scope, sizeof(scope)); + if (ret) + return log_msg_ret("scope", ret); + ret = acpi_device_set_i2c(dev, &i2c, scope); + if (ret) + return log_msg_ret("set", ret); + acpi_device_write_i2c(ctx, &i2c); + + return 0; +} + +static void i2c_hid_func0_cb(struct acpi_ctx *ctx, void *arg) +{ + /* ToInteger (Arg1, Local2) */ + acpigen_write_to_integer(ctx, ARG1_OP, LOCAL2_OP); + /* If (LEqual (Local2, 0x0)) */ + acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x0); + /* Return (Buffer (One) { 0x1f }) */ + acpigen_write_return_singleton_buffer(ctx, 0x1f); + acpigen_pop_len(ctx); /* Pop : If */ + /* Else */ + acpigen_write_else(ctx); + /* If (LEqual (Local2, 0x1)) */ + acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3f }) */ + acpigen_write_return_singleton_buffer(ctx, 0x3f); + acpigen_pop_len(ctx); /* Pop : If */ + /* Else */ + acpigen_write_else(ctx); + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(ctx, 0x0); + acpigen_pop_len(ctx); /* Pop : Else */ + acpigen_pop_len(ctx); /* Pop : Else */ +} + +static void i2c_hid_func1_cb(struct acpi_ctx *ctx, void *arg) +{ + struct dsm_i2c_hid_config *config = arg; + + acpigen_write_return_byte(ctx, config->hid_desc_reg_offset); +} + +static hid_callback_func i2c_hid_callbacks[2] = { + i2c_hid_func0_cb, + i2c_hid_func1_cb, +}; + +void acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx, + struct dsm_i2c_hid_config *config) +{ + acpigen_write_dsm(ctx, ACPI_DSM_I2C_HID_UUID, i2c_hid_callbacks, + ARRAY_SIZE(i2c_hid_callbacks), config); +} + +static const char *acpi_name_from_id(enum uclass_id id) +{ + switch (id) { + case UCLASS_USB_HUB: + /* Root Hub */ + return "RHUB"; + /* DSDT: acpi/northbridge.asl */ + case UCLASS_NORTHBRIDGE: + return "MCHC"; + /* DSDT: acpi/lpc.asl */ + case UCLASS_LPC: + return "LPCB"; + /* DSDT: acpi/xhci.asl */ + case UCLASS_USB: + return "XHCI"; + case UCLASS_PWM: + return "PWM"; + default: + return NULL; + } +} + +static int acpi_check_seq(const struct udevice *dev) +{ + if (dev->req_seq == -1) { + log_warning("Device '%s' has no seq\n", dev->name); + return log_msg_ret("no seq", -ENXIO); + } + + return dev->req_seq; +} + +/* If you change this function, add test cases to dm_test_acpi_get_name() */ +int acpi_device_get_name(const struct udevice *dev, char *out_name) +{ + enum uclass_id parent_id = UCLASS_INVALID; + enum uclass_id id; + const char *name = NULL; + + id = device_get_uclass_id(dev); + if (dev_get_parent(dev)) + parent_id = device_get_uclass_id(dev_get_parent(dev)); + + if (id == UCLASS_SOUND) + name = "HDAS"; + else if (id == UCLASS_PCI) + name = "PCI0"; + else if (device_is_on_pci_bus(dev)) + name = acpi_name_from_id(id); + if (!name) { + switch (parent_id) { + case UCLASS_USB: { + struct usb_device *udev = dev_get_parent_priv(dev); + + sprintf(out_name, udev->speed >= USB_SPEED_SUPER ? + "HS%02d" : "FS%02d", + udev->portnr); + name = out_name; + break; + } + default: + break; + } + } + if (!name) { + int num; + + switch (id) { + /* DSDT: acpi/lpss.asl */ + case UCLASS_SERIAL: + num = acpi_check_seq(dev); + if (num < 0) + return num; + sprintf(out_name, "URT%d", num); + name = out_name; + break; + case UCLASS_I2C: + num = acpi_check_seq(dev); + if (num < 0) + return num; + sprintf(out_name, "I2C%d", num); + name = out_name; + break; + case UCLASS_SPI: + num = acpi_check_seq(dev); + if (num < 0) + return num; + sprintf(out_name, "SPI%d", num); + name = out_name; + break; + default: + break; + } + } + if (!name) { + log_warning("No name for device '%s'\n", dev->name); + return -ENOENT; + } + if (name != out_name) + memcpy(out_name, name, ACPI_NAME_MAX); + + return 0; +} + +int acpi_dp_ofnode_copy_int(ofnode node, struct acpi_dp *dp, const char *prop) +{ + int ret; + u32 val = 0; + + ret = ofnode_read_u32(node, prop, &val); + acpi_dp_add_integer(dp, prop, val); + + return ret; +} + +int acpi_dp_ofnode_copy_str(ofnode node, struct acpi_dp *dp, const char *prop) +{ + const char *val; + + val = ofnode_read_string(node, prop); + if (!val) + return -ENOENT; + acpi_dp_add_string(dp, prop, val); + + return 0; +} + +int acpi_dp_dev_copy_int(const struct udevice *dev, struct acpi_dp *dp, + const char *prop) +{ + int ret; + u32 val = 0; + + ret = dev_read_u32(dev, prop, &val); + acpi_dp_add_integer(dp, prop, val); + + return ret; +} + +int acpi_dp_dev_copy_str(const struct udevice *dev, struct acpi_dp *dp, + const char *prop) +{ + const char *val; + + val = dev_read_string(dev, prop); + if (!val) + return -ENOENT; + acpi_dp_add_string(dp, prop, val); + + return 0; +}

When generating ACPI tables we need to convert GPIOs in U-Boot to the ACPI structures required by ACPI. This is a SoC-specific conversion and cannot be handled by generic code, so add a new GPIO method to do the conversion.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/gpio/gpio-uclass.c | 21 +++++++++++++++++++++ include/acpi_device.h | 12 ++++++++++++ include/asm-generic/gpio.h | 27 +++++++++++++++++++++++++++ lib/acpi/acpi_device.c | 16 ++++++++++++++++ 4 files changed, 76 insertions(+)

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index c3c60a73eb..b49f64d90d 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -4,6 +4,7 @@ */

#include <common.h> +#include <acpi_device.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> @@ -697,6 +698,26 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize) return 0; }

+#if CONFIG_IS_ENABLED(ACPIGEN) +int gpio_get_acpi(const struct gpio_desc *desc, struct acpi_gpio *gpio) +{ + struct dm_gpio_ops *ops; + + if (!dm_gpio_is_valid(desc)) { + /* Indicate that the GPIO is not valid */ + gpio->pin_count = 0; + gpio->pins[0] = 0; + return -EINVAL; + } + + ops = gpio_get_ops(desc->dev); + if (!ops->get_acpi) + return -ENOSYS; + + return ops->get_acpi(desc, gpio); +} +#endif + int gpio_claim_vector(const int *gpio_num_array, const char *fmt) { int i, ret; diff --git a/include/acpi_device.h b/include/acpi_device.h index 919e6bcdaa..fd047f3944 100644 --- a/include/acpi_device.h +++ b/include/acpi_device.h @@ -533,6 +533,18 @@ size_t acpi_dp_add_property_list(struct acpi_dp *dp, */ int acpi_dp_write(struct acpi_ctx *ctx, struct acpi_dp *table);

+/** + * acpi_device_write_gpio_desc() - Write a GPIO to ACPI + * + * This creates a GPIO descriptor for a GPIO, including information ACPI needs + * to use it. The type is always ACPI_GPIO_TYPE_IO. + * + * @desc: GPIO to write + * @return 0 if OK, -ve on error + */ +int acpi_device_write_gpio_desc(struct acpi_ctx *ctx, + const struct gpio_desc *desc); + /** * acpi_device_write_i2c_dev() - Write an I2C device to ACPI, including * information ACPI needs to use it. diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index d6cf18744f..42e112ee66 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -9,6 +9,7 @@

#include <dm/ofnode.h>

+struct acpi_gpio; struct ofnode_phandle_args;

/* @@ -290,6 +291,20 @@ struct dm_gpio_ops { */ int (*xlate)(struct udevice *dev, struct gpio_desc *desc, struct ofnode_phandle_args *args); + +#if CONFIG_IS_ENABLED(ACPIGEN) + /** + * get_acpi() - Get the ACPI info for a GPIO + * + * This converts a GPIO to an ACPI structure for adding to the ACPI + * tables. + * + * @desc: GPIO description to convert + * @gpio: Output ACPI GPIO information + * @return ACPI pin number or -ve on error + */ + int (*get_acpi)(const struct gpio_desc *desc, struct acpi_gpio *gpio); +#endif };

/** @@ -657,4 +672,16 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); */ int gpio_get_number(const struct gpio_desc *desc);

+/** + * gpio_get_acpi() - Get the ACPI pin for a GPIO + * + * This converts a GPIO to an ACPI pin number for adding to the ACPI + * tables. If the GPIO is invalid, the pin_count and pins[0] are set to 0 + * + * @desc: GPIO description to convert + * @gpio: Output ACPI GPIO information + * @return ACPI pin number or -ve on error + */ +int gpio_get_acpi(const struct gpio_desc *desc, struct acpi_gpio *gpio); + #endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c index 2d03639714..d94a403aa1 100644 --- a/lib/acpi/acpi_device.c +++ b/lib/acpi/acpi_device.c @@ -287,6 +287,22 @@ int acpi_device_write_gpio(struct acpi_ctx *ctx, const struct acpi_gpio *gpio) return 0; }

+int acpi_device_write_gpio_desc(struct acpi_ctx *ctx, + const struct gpio_desc *desc) +{ + struct acpi_gpio gpio; + int ret; + + ret = gpio_get_acpi(desc, &gpio); + if (ret) + return log_msg_ret("desc", ret); + ret = acpi_device_write_gpio(ctx, &gpio); + if (ret) + return log_msg_ret("gpio", ret); + + return 0; +} + /* ACPI 6.1 section 6.4.3.8.2.1 - I2cSerialBus() */ static void acpi_device_write_i2c(struct acpi_ctx *ctx, const struct acpi_i2c *i2c)

Some devices need to generate code for the Secondary System Descriptor Table (SSDT). Add a method to handle this.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/sandbox/dts/test.dts | 2 ++ drivers/core/acpi.c | 38 ++++++++++++++++++++++++++++++++++++ include/dm/acpi.h | 23 ++++++++++++++++++++++ test/dm/acpi.c | 41 ++++++++++++++++++++++++++++++++++++++- 4 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 82208de5a8..3351f92165 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -208,10 +208,12 @@

acpi-test { compatible = "denx,u-boot-acpi-test"; + acpi-ssdt-test-data = "ab"; };

acpi-test2 { compatible = "denx,u-boot-acpi-test"; + acpi-ssdt-test-data = "cd"; };

clocks { diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index f748aa3f33..18567682f2 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -11,6 +11,7 @@ #include <common.h> #include <dm.h> #include <dm/acpi.h> +#include <dm/device-internal.h> #include <dm/root.h>

int acpi_return_name(char *out_name, const char *name) @@ -31,6 +32,43 @@ int acpi_get_name(const struct udevice *dev, char *out_name) return -ENOSYS; }

+int _acpi_fill_ssdt(struct acpi_ctx *ctx, struct udevice *parent) +{ + struct acpi_ops *aops; + struct udevice *dev; + int ret; + + aops = device_get_acpi_ops(parent); + if (aops && aops->fill_ssdt) { + log_debug("\n- %s %p\n", parent->name, + aops->fill_ssdt); + ret = device_ofdata_to_platdata(parent); + if (ret) + return log_msg_ret("ofdata", ret); + ret = aops->fill_ssdt(parent, ctx); + if (ret) + return log_msg_ret("ssdt", ret); + } + device_foreach_child(dev, parent) { + ret = _acpi_fill_ssdt(ctx, dev); + if (ret) + return log_msg_ret("recurse", ret); + } + + return 0; +} + +int acpi_fill_ssdt(struct acpi_ctx *ctx) +{ + int ret; + + log_debug("Writing SSDT tables\n"); + ret = _acpi_fill_ssdt(ctx, dm_root()); + log_debug("Writing SSDT finished, err=%d\n", ret); + + return ret; +} + int _acpi_write_dev_tables(struct acpi_ctx *ctx, const struct udevice *parent) { struct acpi_ops *aops; diff --git a/include/dm/acpi.h b/include/dm/acpi.h index 0f78a506da..c340c21685 100644 --- a/include/dm/acpi.h +++ b/include/dm/acpi.h @@ -72,6 +72,19 @@ struct acpi_ops { * @return 0 if OK, -ve on error */ int (*write_tables)(const struct udevice *dev, struct acpi_ctx *ctx); + + /** + * fill_ssdt() - Generate SSDT code for a device + * + * This is called to create the SSDT code. THe method should write out + * whatever ACPI code is needed by this device. It will end up in the + * SSDT table. + * + * @dev: Device to write + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ + int (*fill_ssdt)(const struct udevice *dev, struct acpi_ctx *ctx); };

#define device_get_acpi_ops(dev) ((dev)->driver->acpi_ops) @@ -116,6 +129,16 @@ int acpi_return_name(char *out_name, const char *name); */ int acpi_write_dev_tables(struct acpi_ctx *ctx);

+/** + * acpi_fill_ssdt() - Generate ACPI tables for SSDT + * + * This is called to create the SSDT code for all devices. + * + * @ctx: ACPI context to use + * @return 0 if OK, -ve on error + */ +int acpi_fill_ssdt(struct acpi_ctx *ctx); + #endif /* __ACPI__ */

#endif diff --git a/test/dm/acpi.c b/test/dm/acpi.c index feb380b26c..50d6ec91f7 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -7,6 +7,7 @@ */

#include <common.h> +#include <acpigen.h> #include <acpi_table.h> #include <console.h> #include <dm.h> @@ -14,7 +15,6 @@ #include <mapmem.h> #include <version.h> #include <tables_csum.h> -#include <version.h> #include <dm/acpi.h> #include <dm/test.h> #include <test/ut.h> @@ -43,9 +43,21 @@ static int testacpi_get_name(const struct udevice *dev, char *out_name) return acpi_return_name(out_name, ACPI_TEST_DEV_NAME); }

+static int testacpi_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) +{ + const char *data; + + data = dev_read_string(dev, "acpi-ssdt-test-data"); + while (*data) + acpigen_emit_byte(ctx, *data++); + + return 0; +} + struct acpi_ops testacpi_ops = { .get_name = testacpi_get_name, .write_tables = testacpi_write_tables, + .fill_ssdt = testacpi_fill_ssdt, };

static const struct udevice_id testacpi_ids[] = { @@ -313,3 +325,30 @@ static int dm_test_acpi_cmd_dump(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_cmd_dump, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test acpi_fill_ssdt() */ +static int dm_test_acpi_fill_ssdt(struct unit_test_state *uts) +{ + struct acpi_ctx ctx; + u8 *buf; + + buf = malloc(BUF_SIZE); + ut_assertnonnull(buf); + + ctx.current = buf; + buf[4] = 'z'; /* sentinal */ + ut_assertok(acpi_fill_ssdt(&ctx)); + + /* These values come from acpi-test's acpi-ssdt-test-data property */ + ut_asserteq('a', buf[0]); + ut_asserteq('b', buf[1]); + + /* These values come from acpi-test2's acpi-ssdt-test-data property */ + ut_asserteq('c', buf[2]); + ut_asserteq('d', buf[3]); + + ut_asserteq('z', buf[4]); + + return 0; +} +`DM_TEST(dm_test_acpi_fill_ssdt, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

It is useful to be able to control the order of data written to the SSDT so that we can compare the output against known-good kernel dumps.

Add code to record each item that is added along with the device that added it. That allows us to reorder things later if needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/core/acpi.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+)

diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 18567682f2..d7ab906757 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -14,6 +14,32 @@ #include <dm/device-internal.h> #include <dm/root.h>

+#define MAX_ITEMS 100 + +/* Type of table that we collected */ +enum gen_type_t { + TYPE_SSDT, +}; + +/** + * struct acpi_item - Holds info about ACPI data generated by a driver method + * + * @dev: Device that generated this data + * @type: Table type it refers to + * @buf: Buffer containing the data + * @size: Size of the data in bytes + */ +struct acpi_item { + struct udevice *dev; + enum gen_type_t type; + char *buf; + int size; +}; + +/* List of ACPI items collected */ +static struct acpi_item acpi_item[MAX_ITEMS]; +static int item_count; + int acpi_return_name(char *out_name, const char *name) { strcpy(out_name, name); @@ -32,6 +58,43 @@ int acpi_get_name(const struct udevice *dev, char *out_name) return -ENOSYS; }

+/** + * acpi_add_item() - Add a new item to the list of data collected + * + * @ctx: ACPI context + * @dev: Device that generated the data + * @type: Table type it refers to + * @start: The start of the data (the end is obtained from ctx->current) + * @return 0 if OK, -ENOSPC if too many items, -ENOMEM if out of memory + */ +static int acpi_add_item(struct acpi_ctx *ctx, struct udevice *dev, + enum gen_type_t type, void *start) +{ + struct acpi_item *item; + void *end = ctx->current; + + if (item_count == MAX_ITEMS) { + log_err("Too many items\n"); + return log_msg_ret("mem", -ENOSPC); + } + + item = &acpi_item[item_count]; + item->dev = dev; + item->type = type; + item->size = end - start; + if (!item->size) + return 0; + item->buf = malloc(item->size); + if (!item->buf) + return log_msg_ret("mem", -ENOMEM); + memcpy(item->buf, start, item->size); + item_count++; + log_debug("* %s: Added type %d, %p, size %x\n", dev->name, type, start, + item->size); + + return 0; +} + int _acpi_fill_ssdt(struct acpi_ctx *ctx, struct udevice *parent) { struct acpi_ops *aops; @@ -40,6 +103,8 @@ int _acpi_fill_ssdt(struct acpi_ctx *ctx, struct udevice *parent)

aops = device_get_acpi_ops(parent); if (aops && aops->fill_ssdt) { + void *start = ctx->current; + log_debug("\n- %s %p\n", parent->name, aops->fill_ssdt); ret = device_ofdata_to_platdata(parent); @@ -48,6 +113,11 @@ int _acpi_fill_ssdt(struct acpi_ctx *ctx, struct udevice *parent) ret = aops->fill_ssdt(parent, ctx); if (ret) return log_msg_ret("ssdt", ret); + + /* Add the item to the internal list */ + ret = acpi_add_item(ctx, parent, TYPE_SSDT, start); + if (ret) + return log_msg_ret("add", ret); } device_foreach_child(dev, parent) { ret = _acpi_fill_ssdt(ctx, dev);

Call the new core function to write the SSDT. This is made up of fragments generated by devices that have the fill_ssdt() method.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 50 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 694e92c158..3b97fe162c 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -7,6 +7,7 @@ */

#include <common.h> +#include <acpigen.h> #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> @@ -344,6 +345,46 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) header->checksum = table_compute_checksum((void *)spcr, header->length); }

+static void acpi_ssdt_write_cbtable(struct acpi_ctx *ctx) +{ + uintptr_t base; + u32 size; + + base = 0; + size = 0; + + acpigen_write_device(ctx, "CTBL"); + acpigen_write_coreboot_hid(ctx, COREBOOT_ACPI_ID_CBTABLE); + acpigen_write_name_integer(ctx, "_UID", 0); + acpigen_write_sta(ctx, ACPI_STATUS_DEVICE_HIDDEN_ON); + acpigen_write_name(ctx, "_CRS"); + acpigen_write_resourcetemplate_header(ctx); + acpigen_write_mem32fixed(ctx, 0, base, size); + acpigen_write_resourcetemplate_footer(ctx); + acpigen_pop_len(ctx); +} + +void acpi_create_ssdt(struct acpi_ctx *ctx, struct acpi_table_header *ssdt, + const char *oem_table_id) +{ + memset((void *)ssdt, '\0', sizeof(struct acpi_table_header)); + + acpi_fill_header(ssdt, "SSDT"); + ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT); + ssdt->aslc_revision = 1; + ssdt->length = sizeof(struct acpi_table_header); + + acpi_inc(ctx, sizeof(struct acpi_table_header)); + + /* Write object to declare coreboot tables */ + acpi_ssdt_write_cbtable(ctx); + acpi_fill_ssdt(ctx); + + /* (Re)calculate length and checksum. */ + ssdt->length = ctx->current - (void *)ssdt; + ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length); +} + /* * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ @@ -353,6 +394,7 @@ ulong write_acpi_tables(ulong start_addr) struct acpi_facs *facs; struct acpi_table_header *dsdt; struct acpi_fadt *fadt; + struct acpi_table_header *ssdt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; struct acpi_csrt *csrt; @@ -408,6 +450,14 @@ ulong write_acpi_tables(ulong start_addr) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(ctx, fadt);

+ debug("ACPI: * SSDT\n"); + ssdt = (struct acpi_table_header *)ctx->current; + acpi_create_ssdt(ctx, ssdt, ACPI_TABLE_CREATOR); + if (ssdt->length > sizeof(struct acpi_table_header)) { + acpi_inc_align(ctx, ssdt->length); + acpi_add_table(ctx, ssdt); + } + debug("ACPI: * MCFG\n"); mcfg = ctx->current; acpi_create_mcfg(mcfg);

Call the new core function to inject ASL programmatically into the DSDT. This is made up of fragments generated by devices that have the inject_dsdt() method. The normal, compiled ASL file is added after this.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 3b97fe162c..5e14149923 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -422,7 +422,20 @@ ulong write_acpi_tables(ulong start_addr) memcpy(ctx->current, (char *)&AmlCode + sizeof(struct acpi_table_header), dsdt->length - sizeof(struct acpi_table_header)); - acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header)); + + if (dsdt->length >= sizeof(struct acpi_table_header)) { + acpi_inject_dsdt(ctx); + memcpy(ctx->current, + (char *)AmlCode + sizeof(struct acpi_table_header), + dsdt->length - sizeof(struct acpi_table_header)); + acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header)); + + /* (Re)calculate length and checksum. */ + dsdt->length = ctx->current - (void *)dsdt; + dsdt->checksum = 0; + dsdt->checksum = table_compute_checksum(dsdt, dsdt->length); + } + acpi_align(ctx);

/* Pack GNVS into the ACPI table area */ for (i = 0; i < dsdt->length; i++) {

For many device types it is possible to figure out the name just by looking at its uclass or parent. Add a function to handle this, since it allows us to cover the vast majority of cases automatically.

However it is sometimes impossible to figure out an ACPI name for a device just by looking at its uclass. For example a touch device may have a vendor-specific name. Add a new "acpi,name" property to allow a custom name to be created.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/sandbox/dts/test.dts | 1 + doc/device-tree-bindings/device.txt | 13 +++++++++ drivers/core/acpi.c | 11 +++++++- include/dm/device.h | 2 +- test/dm/acpi.c | 42 ++++++++++++++++++++++++++++- 5 files changed, 66 insertions(+), 3 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index f60f0adc05..410235fae3 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -94,6 +94,7 @@ int-value = <1234>; uint-value = <(-1234)>; interrupts-extended = <&irq 3 0>; + acpi,name = "GHIJ"; };

junk { diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt index e625e67f43..61ebd7a942 100644 --- a/doc/device-tree-bindings/device.txt +++ b/doc/device-tree-bindings/device.txt @@ -18,6 +18,8 @@ U-Boot provides for some optional properties which are documented here. - acpi,hid-desc-reg-offset : HID register offset (for Human Interface Devices) - acpi,probed : Tells U-Boot to add 'linux,probed' to the ACPI tables so that Linux will not re-init the device + - acpi,name : Provides the ACPI name for a device, which is a string consisting + of four alphanumeric character (upper case) - acpi,uid : _UID value for device

@@ -35,3 +37,14 @@ synaptics_touchpad: synaptics-touchpad@2c { acpi,probed; acpi,hid-desc-reg-offset = <0x20>; }; + +pcie-a0@14,0 { + reg = <0x0000a000 0 0 0 0>; + acpi,name = "RP01"; + wifi: wifi { + compatible = "intel,generic-wifi"; + acpi,desc = "Intel WiFi"; + acpi,name = "WF00"; + interrupts-extended = <&acpi_gpe 0x3c 0>; + }; +}; diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 657753ebb3..ba02b04636 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -9,6 +9,7 @@ #define LOG_CATEOGRY LOGC_ACPI

#include <common.h> +#include <acpi_device.h> #include <dm.h> #include <dm/acpi.h> #include <dm/device-internal.h> @@ -51,12 +52,20 @@ int acpi_return_name(char *out_name, const char *name) int acpi_get_name(const struct udevice *dev, char *out_name) { struct acpi_ops *aops; + const char *name; + int ret;

aops = device_get_acpi_ops(dev); if (aops && aops->get_name) return aops->get_name(dev, out_name); + name = dev_read_string(dev, "acpi,name"); + if (name) + return acpi_return_name(out_name, name); + ret = acpi_device_get_name(dev, out_name); + if (ret) + return log_msg_ret("dev", ret);

- return -ENOSYS; + return 0; }

/** diff --git a/include/dm/device.h b/include/dm/device.h index c2e12cd151..03d7ef1bb3 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -713,7 +713,7 @@ int dev_enable_by_path(const char *path); */ static inline bool device_is_on_pci_bus(const struct udevice *dev) { - return device_get_uclass_id(dev->parent) == UCLASS_PCI; + return dev->parent && device_get_uclass_id(dev->parent) == UCLASS_PCI; }

/** diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 16dc0955be..c87bd8569d 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -93,12 +93,52 @@ UCLASS_DRIVER(testacpi) = { static int dm_test_acpi_get_name(struct unit_test_state *uts) { char name[ACPI_NAME_MAX]; - struct udevice *dev; + struct udevice *dev, *dev2, *i2c, *spi, *serial, *timer, *sound; + struct udevice *pci, *root;

+ /* Test getting the name from the driver */ ut_assertok(uclass_first_device_err(UCLASS_TEST_ACPI, &dev)); ut_assertok(acpi_get_name(dev, name)); ut_asserteq_str(ACPI_TEST_DEV_NAME, name);

+ /* Test getting the name from the device tree */ + ut_assertok(uclass_get_device_by_name(UCLASS_TEST_FDT, "a-test", + &dev2)); + ut_assertok(acpi_get_name(dev2, name)); + ut_asserteq_str("GHIJ", name); + + /* Test getting the name from acpi_device_get_name() */ + ut_assertok(uclass_first_device(UCLASS_I2C, &i2c)); + ut_assertok(acpi_get_name(i2c, name)); + ut_asserteq_str("I2C0", name); + + ut_assertok(uclass_first_device(UCLASS_SPI, &spi)); + ut_assertok(acpi_get_name(spi, name)); + ut_asserteq_str("SPI0", name); + + /* The uart has no sequence number, so this should fail */ + ut_assertok(uclass_first_device(UCLASS_SERIAL, &serial)); + ut_asserteq(-ENXIO, acpi_get_name(serial, name)); + + /* ACPI doesn't know about the timer */ + ut_assertok(uclass_first_device(UCLASS_TIMER, &timer)); + ut_asserteq(-ENOENT, acpi_get_name(timer, name)); + + /* May as well test the rest of the cases */ + ut_assertok(uclass_first_device(UCLASS_SOUND, &sound)); + ut_assertok(acpi_get_name(sound, name)); + ut_asserteq_str("HDAS", name); + + ut_assertok(uclass_first_device(UCLASS_PCI, &pci)); + ut_assertok(acpi_get_name(pci, name)); + ut_asserteq_str("PCI0", name); + + ut_assertok(uclass_first_device(UCLASS_ROOT, &root)); + ut_assertok(acpi_get_name(root, name)); + ut_asserteq_str("\_SB", name); + + /* Note that we don't have tests for acpi_name_from_id() */ + return 0; } DM_TEST(dm_test_acpi_get_name, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

In some cases an internal error may prevent this from working. Update the function return value and report the error. At present the API for writing tables does not easily support reporting errors, but once it is fully updated to use a context pointer, this will be easier.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/baytrail/acpi.c | 4 +++- arch/x86/cpu/quark/acpi.c | 4 +++- arch/x86/cpu/tangier/acpi.c | 4 +++- arch/x86/include/asm/acpi_table.h | 10 +++++++++- arch/x86/lib/acpi_table.c | 10 ++++++++-- 5 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 856af95556..38cf832817 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -138,7 +138,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); }

-void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev; int ret; @@ -158,6 +158,8 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) gnvs->iuart_en = 1; else gnvs->iuart_en = 0; + + return 0; }

#ifdef CONFIG_HAVE_ACPI_RESUME diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index dd562a6e2f..fcc93a7c59 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -133,8 +133,10 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); }

-void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { /* quark is a uni-processor */ gnvs->pcnt = 1; + + return 0; } diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 768c4dcbc8..760e3eda84 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -107,7 +107,7 @@ u32 acpi_fill_csrt(u32 current) return current; }

-void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev; int ret; @@ -122,4 +122,6 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) if (ret > 0) gnvs->pcnt = ret; } + + return 0; } diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 22d54057f1..7b5217893f 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -26,7 +26,15 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); u32 acpi_fill_mcfg(u32 current); u32 acpi_fill_csrt(u32 current); -void acpi_create_gnvs(struct acpi_global_nvs *gnvs); + +/** + * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table + * + * @gnvs: Table to fill in + * @return 0 if OK, -ve on error + */ +int acpi_create_gnvs(struct acpi_global_nvs *gnvs); + ulong write_acpi_tables(ulong start);

/** diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 5e14149923..68e0779357 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -453,8 +453,14 @@ ulong write_acpi_tables(ulong start_addr) dsdt->checksum = 0; dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);

- /* Fill in platform-specific global NVS variables */ - acpi_create_gnvs(ctx->current); + /* + * Fill in platform-specific global NVS variables. If this fails we + * cannot return the error but this should only happen while debugging. + */ + addr = acpi_create_gnvs(ctx->current); + if (IS_ERR_VALUE(addr)) + printf("Error: Gailed to create GNVS\n"); + acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));

debug("ACPI: * FADT\n");

Write required information into the SSDT to describe the SD card card-detect pin. Since the required GPIO properties are not present in the device-tree binding, set them manually for now.

Signed-off-by: Simon Glass sjg@chromium.org ---

configs/sandbox_defconfig | 2 ++ drivers/mmc/pci_mmc.c | 76 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 77 insertions(+), 1 deletion(-)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 858ad04b10..83a42cfddf 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -137,7 +137,9 @@ CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y CONFIG_I2C_EEPROM=y +CONFIG_MMC_PCI=y CONFIG_MMC_SANDBOX=y +CONFIG_MMC_SDHCI=y CONFIG_MTD=y CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 404264a697..b4705e45a1 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -5,12 +5,15 @@ */

#include <common.h> +#include <acpigen.h> +#include <acpi_device.h> #include <dm.h> #include <errno.h> #include <malloc.h> #include <mapmem.h> #include <sdhci.h> -#include <asm/pci.h> +#include <asm-generic/gpio.h> +#include <dm/acpi.h>

struct pci_mmc_plat { struct mmc_config cfg; @@ -20,6 +23,7 @@ struct pci_mmc_plat { struct pci_mmc_priv { struct sdhci_host host; void *base; + struct gpio_desc cd_gpio; };

static int pci_mmc_probe(struct udevice *dev) @@ -44,6 +48,15 @@ static int pci_mmc_probe(struct udevice *dev) return sdhci_probe(dev); }

+static int pci_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct pci_mmc_priv *priv = dev_get_priv(dev); + + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); + + return 0; +} + static int pci_mmc_bind(struct udevice *dev) { struct pci_mmc_plat *plat = dev_get_platdata(dev); @@ -51,14 +64,75 @@ static int pci_mmc_bind(struct udevice *dev) return sdhci_bind(dev, &plat->mmc, &plat->cfg); }

+static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct pci_mmc_priv *priv = dev_get_priv(dev); + char path[ACPI_PATH_MAX]; + struct acpi_gpio gpio; + struct acpi_dp *dp; + int ret; + + if (!dev_of_valid(dev)) + return 0; + + ret = gpio_get_acpi(&priv->cd_gpio, &gpio); + if (ret) + return log_msg_ret("gpio", ret); + gpio.type = ACPI_GPIO_TYPE_INTERRUPT; + gpio.pull = ACPI_GPIO_PULL_NONE; + gpio.irq.mode = ACPI_IRQ_EDGE_TRIGGERED; + gpio.irq.polarity = ACPI_IRQ_ACTIVE_BOTH; + gpio.irq.shared = ACPI_IRQ_SHARED; + gpio.irq.wake = ACPI_IRQ_WAKE; + gpio.interrupt_debounce_timeout = 10000; /* 100ms */ + + /* Use device path as the Scope for the SSDT */ + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + acpigen_write_scope(ctx, path); + acpigen_write_name(ctx, "_CRS"); + + /* Write GpioInt() as default (if set) or custom from devicetree */ + acpigen_write_resourcetemplate_header(ctx); + acpi_device_write_gpio(ctx, &gpio); + acpigen_write_resourcetemplate_footer(ctx); + + /* Bind the cd-gpio name to the GpioInt() resource */ + dp = acpi_dp_new_table("_DSD"); + if (!dp) + return -ENOMEM; + acpi_dp_add_gpio(dp, "cd-gpio", path, 0, 0, 1); + ret = acpi_dp_write(ctx, dp); + if (ret) + return log_msg_ret("cd", ret); + + acpigen_pop_len(ctx); + + return 0; +} + +struct acpi_ops pci_mmc_acpi_ops = { + .fill_ssdt = pci_mmc_acpi_fill_ssdt, +}; + +static const struct udevice_id pci_mmc_match[] = { + { .compatible = "intel,apl-sd" }, + { } +}; + U_BOOT_DRIVER(pci_mmc) = { .name = "pci_mmc", .id = UCLASS_MMC, + .of_match = pci_mmc_match, .bind = pci_mmc_bind, + .ofdata_to_platdata = pci_mmc_ofdata_to_platdata, .probe = pci_mmc_probe, .ops = &sdhci_ops, .priv_auto_alloc_size = sizeof(struct pci_mmc_priv), .platdata_auto_alloc_size = sizeof(struct pci_mmc_plat), + acpi_ops_ptr(&pci_mmc_acpi_ops) };

static struct pci_device_id mmc_supported[] = {

This chip is used on coral and we need to generate ACPI tables for sound to make it work. Add a driver that does just this (i.e. at present does not actually support playing sound).

Signed-off-by: Simon Glass sjg@chromium.org ---

configs/sandbox_defconfig | 1 + doc/device-tree-bindings/sound/max98357a.txt | 22 ++++ drivers/sound/Kconfig | 9 ++ drivers/sound/Makefile | 1 + drivers/sound/max98357a.c | 109 +++++++++++++++++++ 5 files changed, 142 insertions(+) create mode 100644 doc/device-tree-bindings/sound/max98357a.txt create mode 100644 drivers/sound/max98357a.c

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index cf1037f9a3..cbd9eea77a 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -197,6 +197,7 @@ CONFIG_SMEM=y CONFIG_SANDBOX_SMEM=y CONFIG_SOUND=y CONFIG_SOUND_DA7219=y +CONFIG_SOUND_MAX98357A=y CONFIG_SOUND_SANDBOX=y CONFIG_SANDBOX_SPI=y CONFIG_SPMI=y diff --git a/doc/device-tree-bindings/sound/max98357a.txt b/doc/device-tree-bindings/sound/max98357a.txt new file mode 100644 index 0000000000..4bce14ce80 --- /dev/null +++ b/doc/device-tree-bindings/sound/max98357a.txt @@ -0,0 +1,22 @@ +Maxim MAX98357A audio DAC + +This node models the Maxim MAX98357A DAC. + +Required properties: +- compatible : "maxim,max98357a" + +Optional properties: +- sdmode-gpios : GPIO specifier for the chip's SD_MODE pin. + If this option is not specified then driver does not manage + the pin state (e.g. chip is always on). +- sdmode-delay : specify delay time for SD_MODE pin. + If this option is specified, which means it's required i2s clocks + ready before SD_MODE is unmuted in order to avoid the speaker pop noise. + It's observed that 5ms is sufficient. + +Example: + +max98357a { + compatible = "maxim,max98357a"; + sdmode-gpios = <&qcom_pinmux 25 0>; +}; diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 7f214b97be..0948d8caab 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -113,6 +113,15 @@ config SOUND_MAX98095 audio data and I2C for codec control. At present it only works with the Samsung I2S driver.

+config SOUND_MAX98357A + bool "Support Maxim max98357a audio codec" + depends on PCI + help + Enable the max98357a audio codec. This is connected on PCI for + audio data codec control. This is currently only capable of providing + ACPI information. A full driver (with sound in U-Boot) is currently + not available. + config SOUND_RT5677 bool "Support Realtek RT5677 audio codec" depends on SOUND diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 8c3933ad15..9b40c8012f 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_SOUND_WM8994) += wm8994.o obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98095) += max98095.o maxim_codec.o +obj-$(CONFIG_SOUND_MAX98357A) += max98357a.o obj-$(CONFIG_SOUND_INTEL_HDA) += hda_codec.o obj-$(CONFIG_SOUND_I8254) += i8254_beep.o obj-$(CONFIG_SOUND_RT5677) += rt5677.o diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c new file mode 100644 index 0000000000..63c336c27b --- /dev/null +++ b/drivers/sound/max98357a.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * max98357a.c -- MAX98357A Audio driver + * + * Copyright 2019 Google LLC + * Parts taken from coreboot + */ + +#include <common.h> +#include <acpigen.h> +#include <acpi_device.h> +#include <audio_codec.h> +#include <dm.h> +#include <sound.h> +#include <asm-generic/gpio.h> +#include <dm/acpi.h> + +struct max97357a_priv { + struct gpio_desc sdmode_gpio; +}; + +static int max97357a_ofdata_to_platdata(struct udevice *dev) +{ + struct max97357a_priv *priv = dev_get_priv(dev); + + gpio_request_by_name(dev, "sdmode-gpios", 0, &priv->sdmode_gpio, + GPIOD_IS_IN); + + return 0; +} + +static int max97357a_acpi_fill_ssdt(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct max97357a_priv *priv = dev_get_priv(dev); + char scope[ACPI_PATH_MAX]; + char name[ACPI_NAME_MAX]; + char path[ACPI_PATH_MAX]; + struct acpi_dp *dp; + int ret; + + ret = acpi_device_scope(dev, scope, sizeof(scope)); + if (ret) + return log_msg_ret("scope", ret); + ret = acpi_device_name(dev, name); + if (ret) + return log_msg_ret("name", ret); + + /* Device */ + acpigen_write_scope(ctx, scope); + acpigen_write_device(ctx, name); + acpigen_write_name_string(ctx, "_HID", + dev_read_string(dev, "acpi,hid")); + acpigen_write_name_integer(ctx, "_UID", 0); + acpigen_write_name_string(ctx, "_DDN", + dev_read_string(dev, "acpi,desc")); + acpigen_write_sta(ctx, acpi_device_status(dev)); + + ret = acpi_device_write_gpio_desc(ctx, &priv->sdmode_gpio); + if (ret) + return log_msg_ret("gpio", ret); + + /* Resources */ + acpigen_write_name(ctx, "_CRS"); + acpigen_write_resourcetemplate_header(ctx); + ret = acpi_device_write_gpio_desc(ctx, &priv->sdmode_gpio); + if (ret) + return log_msg_ret("gpio", ret); + acpigen_write_resourcetemplate_footer(ctx); + + /* _DSD for devicetree properties */ + /* This points to the first pin in the first gpio entry in _CRS */ + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + dp = acpi_dp_new_table("_DSD"); + acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, + priv->sdmode_gpio.flags & GPIOD_ACTIVE_LOW ? + ACPI_GPIO_ACTIVE_LOW : ACPI_GPIO_ACTIVE_HIGH); + acpi_dp_add_integer(dp, "sdmode-delay", + dev_read_u32_default(dev, "sdmode-delay", 0)); + acpi_dp_write(ctx, dp); + + acpigen_pop_len(ctx); /* Device */ + acpigen_pop_len(ctx); /* Scope */ + + return 0; +} + +struct acpi_ops max97357a_acpi_ops = { + .fill_ssdt = max97357a_acpi_fill_ssdt, +}; + +static const struct audio_codec_ops max98357a_ops = { +}; + +static const struct udevice_id max98357a_ids[] = { + { .compatible = "maxim,max98357a" }, + { } +}; + +U_BOOT_DRIVER(max98357a) = { + .name = "max98357a", + .id = UCLASS_AUDIO_CODEC, + .of_match = max98357a_ids, + .ofdata_to_platdata = max97357a_ofdata_to_platdata, + .ops = &max98357a_ops, + acpi_ops_ptr(&max97357a_acpi_ops) +};

Add information about what is returned on error.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/intel_pinctrl.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h index ebdaa39265..26fbd4c377 100644 --- a/arch/x86/include/asm/intel_pinctrl.h +++ b/arch/x86/include/asm/intel_pinctrl.h @@ -299,6 +299,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset); * @pad: Pad to check * @devp: Returns pinctrl device containing that pad * @offsetp: Returns offset of pad within that pinctrl device + * @return 0 if OK, -ENOTBLK if pad number is invalid */ int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);

At present the itss is probed in the ofdata_to_platdata() method. This is incorrect since itss is a child of p2sb which itself needs to probe the pinctrl device. This means that p2sb is effectively not probed when the itss is probed, so we get the wrong register address from p2sb.

Fix this by moving the itss probe to the correct place.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/pinctrl/intel/pinctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c index 8204add295..adc080c0b1 100644 --- a/drivers/pinctrl/intel/pinctrl.c +++ b/drivers/pinctrl/intel/pinctrl.c @@ -616,15 +616,11 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, { struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); struct intel_pinctrl_priv *priv = dev_get_priv(dev); - int ret;

if (!comm) { log_err("Cannot find community for pid %d\n", pplat->pid); return -EDOM; } - ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss); - if (ret) - return log_msg_ret("Cannot find ITSS", ret); priv->comm = comm; priv->num_cfgs = num_cfgs;

@@ -634,8 +630,12 @@ int intel_pinctrl_ofdata_to_platdata(struct udevice *dev, int intel_pinctrl_probe(struct udevice *dev) { struct intel_pinctrl_priv *priv = dev_get_priv(dev); + int ret;

priv->itss_pol_cfg = true; + ret = irq_first_device_type(X86_IRQT_ITSS, &priv->itss); + if (ret) + return log_msg_ret("Cannot find ITSS", ret);

return 0; }

Some devices such as GPIO need to override the normal path that would be generated by driver model. Add a device-tree property for this.

Signed-off-by: Simon Glass sjg@chromium.org ---

doc/device-tree-bindings/device.txt | 23 +++++++++++++++++++++++ drivers/core/acpi.c | 19 +++++++++++++++++++ include/dm/acpi.h | 13 +++++++++++++ 3 files changed, 55 insertions(+)

diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt index 61ebd7a942..107b17589c 100644 --- a/doc/device-tree-bindings/device.txt +++ b/doc/device-tree-bindings/device.txt @@ -16,6 +16,8 @@ U-Boot provides for some optional properties which are documented here. - acpi,hid : Contains the string to use as the HID (Human Interface Device) identifier _HID - acpi,hid-desc-reg-offset : HID register offset (for Human Interface Devices) + - acpi,path : Specifies the full ACPI path for a device. This overrides the + normal path built from the driver-model hierarchy - acpi,probed : Tells U-Boot to add 'linux,probed' to the ACPI tables so that Linux will not re-init the device - acpi,name : Provides the ACPI name for a device, which is a string consisting @@ -48,3 +50,24 @@ pcie-a0@14,0 { interrupts-extended = <&acpi_gpe 0x3c 0>; }; }; + +p2sb: p2sb@d,0 { + u-boot,dm-pre-reloc; + reg = <0x02006810 0 0 0 0>; + compatible = "intel,apl-p2sb"; + early-regs = <IOMAP_P2SB_BAR 0x100000>; + pci,no-autoconfig; + + n { + compatible = "intel,apl-pinctrl"; + u-boot,dm-pre-reloc; + intel,p2sb-port-id = <PID_GPIO_N>; + acpi,path = "\_SB.GPO0"; + gpio_n: gpio-n { + compatible = "intel,gpio"; + u-boot,dm-pre-reloc; + gpio-controller; + #gpio-cells = <2>; + linux-name = "INT3452:00"; + }; + }; diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 762cc40511..65c1fed132 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -68,6 +68,25 @@ int acpi_get_name(const struct udevice *dev, char *out_name) return 0; }

+int acpi_get_path(const struct udevice *dev, char *out_path, int maxlen) +{ + const char *path; + int ret; + + path = dev_read_string(dev, "acpi,path"); + if (path) { + if (strlen(path) >= maxlen) + return -E2BIG; + strcpy(out_path, path); + return 0; + } + ret = acpi_device_path(dev, out_path, maxlen); + if (ret) + return log_msg_ret("dev", ret); + + return 0; +} + /** * acpi_add_item() - Add a new item to the list of data collected * diff --git a/include/dm/acpi.h b/include/dm/acpi.h index ea3a615f60..2b4e8d7e87 100644 --- a/include/dm/acpi.h +++ b/include/dm/acpi.h @@ -172,6 +172,19 @@ int acpi_inject_dsdt(struct acpi_ctx *ctx); */ void acpi_dump_items(bool dump_contents);

+/** + * acpi_get_path() - Get the full ACPI path for a device + * + * This checks for any override in the device tree and calls acpi_device_path() + * if not + * + * @dev: Device to check + * @out_path: Buffer to place the path in (should be ACPI_PATH_MAX long) + * @maxlen: Size of buffer (typically ACPI_PATH_MAX) + * @return 0 if OK, -ve on error + */ +int acpi_get_path(const struct udevice *dev, char *out_path, int maxlen); + #endif /* __ACPI__ */

#endif

Update the PCI driver to generate ACPI information so that Linux has the full information about each I2C bus.

Signed-off-by: Simon Glass sjg@chromium.org

---

drivers/i2c/designware_i2c.c | 25 ++++++++ drivers/i2c/designware_i2c.h | 15 +++++ drivers/i2c/designware_i2c_pci.c | 104 ++++++++++++++++++++++++++++++- 3 files changed, 143 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 9933391bdb..af9ad124d3 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -298,6 +298,31 @@ static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base, /* Restore back i2c now speed set */ if (ena == IC_ENABLE_0B) dw_i2c_enable(i2c_base, true); + if (priv) + priv->config = config; + return 0; +} + +int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz, + struct dw_i2c_speed_config *config) +{ + struct dw_i2c *priv = dev_get_priv(dev); + ulong rate; + int ret; + + if (CONFIG_IS_ENABLED(CLK)) { + rate = clk_get_rate(&priv->clk); + if (IS_ERR_VALUE(rate)) + return log_msg_ret("clk", -EINVAL); + } else { + rate = IC_CLK; + } + + ret = calc_bus_speed(priv, speed_hz, rate, config); + if (ret) + printf("%s: ret=%d\n", __func__, ret); + if (ret) + return log_msg_ret("calc_bus_speed", ret);

return 0; } diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index be17f00140..03657ea3ab 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -198,6 +198,7 @@ struct dw_i2c { #if CONFIG_IS_ENABLED(CLK) struct clk clk; #endif + struct dw_i2c_speed_config config; };

extern const struct dm_i2c_ops designware_i2c_ops; @@ -206,4 +207,18 @@ int designware_i2c_probe(struct udevice *bus); int designware_i2c_remove(struct udevice *dev); int designware_i2c_ofdata_to_platdata(struct udevice *bus);

+/** + * dw_i2c_gen_speed_config() - Calculate config info from requested speed1 + * + * Calculate the speed config from the given @speed_hz and return it so that + * it can be incorporated in ACPI tables + * + * @dev: I2C bus to check + * @speed_hz: Requested speed in Hz + * @config: Returns config to use for that speed + * @return 0 if OK, -ve on error + */ +int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz, + struct dw_i2c_speed_config *config); + #endif /* __DW_I2C_H_ */ diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 50f03e3d90..4fc918c955 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -6,9 +6,14 @@ */

#include <common.h> +#include <acpigen.h> +#include <acpi_device.h> #include <dm.h> #include <spl.h> #include <asm/lpss.h> +#include <dm/acpi.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> #include "designware_i2c.h"

enum { @@ -86,6 +91,8 @@ static int designware_i2c_pci_bind(struct udevice *dev) { char name[20];

+ if (dev_of_valid(dev)) + return 0; /* * Create a unique device name for PCI type devices * ToDo: @@ -99,13 +106,107 @@ static int designware_i2c_pci_bind(struct udevice *dev) * be possible. We cannot use static data in drivers since they may be * used in SPL or before relocation. */ - dev->req_seq = gd->arch.dw_i2c_num_cards++; + dev->req_seq = uclass_find_next_free_req_seq(UCLASS_I2C); sprintf(name, "i2c_designware#%u", dev->req_seq); device_set_name(dev, name);

return 0; }

+/* + * Write ACPI object to describe speed configuration. + * + * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold } + * + * SSCN: I2C_SPEED_STANDARD + * FMCN: I2C_SPEED_FAST + * FPCN: I2C_SPEED_FAST_PLUS + * HSCN: I2C_SPEED_HIGH + */ +static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx, + struct dw_i2c_speed_config *config) +{ + switch (config->speed_mode) { + case IC_SPEED_MODE_HIGH: + acpigen_write_name(ctx, "HSCN"); + break; + case IC_SPEED_MODE_FAST_PLUS: + acpigen_write_name(ctx, "FPCN"); + break; + case IC_SPEED_MODE_FAST: + acpigen_write_name(ctx, "FMCN"); + break; + case IC_SPEED_MODE_STANDARD: + default: + acpigen_write_name(ctx, "SSCN"); + } + + /* Package () { scl_lcnt, scl_hcnt, sda_hold } */ + acpigen_write_package(ctx, 3); + acpigen_write_word(ctx, config->scl_hcnt); + acpigen_write_word(ctx, config->scl_lcnt); + acpigen_write_dword(ctx, config->sda_hold); + acpigen_pop_len(ctx); +} + +/* + * Generate I2C timing information into the SSDT for the OS driver to consume, + * optionally applying override values provided by the caller. + */ +static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct dw_i2c_speed_config config; + char path[ACPI_PATH_MAX]; + u32 speeds[4]; + int size, i; + int ret; + + /* If no device-tree node, ignore this since we assume it isn't used */ + if (!dev_of_valid(dev)) + return 0; + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + + size = dev_read_size(dev, "i2c,speeds"); + if (size < 0) + return log_msg_ret("i2c,speeds", -EINVAL); + size /= sizeof(u32); + if (size > ARRAY_SIZE(speeds)) + return log_msg_ret("array", -E2BIG); + + ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size); + if (ret) + return log_msg_ret("read", -E2BIG); + + if (0) { + acpigen_write_scope(ctx, path); + for (i = 0; i < size; i++) { + ret = dw_i2c_gen_speed_config(dev, speeds[i], &config); + if (ret) + return log_msg_ret("config", ret); + dw_i2c_acpi_write_speed_config(ctx, &config); + } + } else { + uint speed; + + speed = dev_read_u32_default(dev, "clock-frequency", 100000); + acpigen_write_scope(ctx, path); + ret = dw_i2c_gen_speed_config(dev, speed, &config); + if (ret) + return log_msg_ret("config", ret); + dw_i2c_acpi_write_speed_config(ctx, &config); + } + acpigen_pop_len(ctx); + + return 0; +} + +struct acpi_ops dw_i2c_acpi_ops = { + .fill_ssdt = dw_i2c_acpi_fill_ssdt, +}; + static const struct udevice_id designware_i2c_pci_ids[] = { { .compatible = "snps,designware-i2c-pci" }, { .compatible = "intel,apl-i2c", .data = INTEL_APL }, @@ -123,6 +224,7 @@ U_BOOT_DRIVER(i2c_designware_pci) = { .remove = designware_i2c_remove, .flags = DM_FLAG_OS_PREPARE, .ops = &designware_i2c_ops, + acpi_ops_ptr(&dw_i2c_acpi_ops) };

static struct pci_device_id designware_pci_supported[] = {

The P2SB bus needs to be hidden in some cases so that it does not get auto-configured by Linux. Add a method for this.

Signed-off-by: Simon Glass sjg@chromium.org ---

drivers/misc/p2sb-uclass.c | 10 ++++++++++ include/p2sb.h | 25 ++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index 1d00a73f2f..aa6d7aeef7 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -16,6 +16,16 @@

#define PCR_COMMON_IOSF_1_0 1

+int p2sb_set_hide(struct udevice *dev, bool hide) +{ + struct p2sb_ops *ops = p2sb_get_ops(dev); + + if (!ops->set_hide) + return -ENOSYS; + + return ops->set_hide(dev, hide); +} + void *pcr_reg_address(struct udevice *dev, uint offset) { struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev); diff --git a/include/p2sb.h b/include/p2sb.h index 74eb08b7ff..93e1155dca 100644 --- a/include/p2sb.h +++ b/include/p2sb.h @@ -31,13 +31,36 @@ struct p2sb_uc_priv { };

/** - * struct p2sb_ops - Operations for the P2SB (none at present) + * struct p2sb_ops - Operations for the P2SB */ struct p2sb_ops { + /** + * set_hide() - Set/clear the 'hide' bit on the p2sb + * + * This device can be hidden from the PCI bus if needed. This method + * can be called before the p2sb is probed. + * + * @dev: P2SB device + * @hide: true to hide the device, false to show it + * @return 0 if OK, -ve on error + */ + int (*set_hide)(struct udevice *dev, bool hide); };

#define p2sb_get_ops(dev) ((struct p2sb_ops *)(dev)->driver->ops)

+/** + * p2sb_set_hide() - Set/clear the 'hide' bit on the p2sb + * + * This device can be hidden from the PCI bus if needed. This method + * can be called before the p2sb is probed. + * + * @dev: P2SB device + * @hide: true to hide the device, false to show it + * @return 0 if OK, -ve on error + */ +int p2sb_set_hide(struct udevice *dev, bool hide); + /** * pcr_read32/16/8() - Read from a PCR device *

This confuses Linux's PCI probing so needs to be hidden when booting Linux. Add a remove() method to handle this.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/apollolake/p2sb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)

diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c index 92bf31333c..9f4b1a0d92 100644 --- a/arch/x86/cpu/apollolake/p2sb.c +++ b/arch/x86/cpu/apollolake/p2sb.c @@ -151,6 +151,17 @@ static int apl_p2sb_set_hide(struct udevice *dev, bool hide) return 0; }

+static int apl_p2sb_remove(struct udevice *dev) +{ + int ret; + + ret = apl_p2sb_set_hide(dev, true); + if (ret) + return log_msg_ret("hide", ret); + + return 0; +} + static int p2sb_child_post_bind(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) @@ -181,9 +192,12 @@ U_BOOT_DRIVER(apl_p2sb_drv) = { .id = UCLASS_P2SB, .of_match = apl_p2sb_ids, .probe = apl_p2sb_probe, + .remove = apl_p2sb_remove, + .ops = &apl_p2sb_ops, .ofdata_to_platdata = apl_p2sb_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct p2sb_platdata), .per_child_platdata_auto_alloc_size = sizeof(struct p2sb_child_platdata), .child_post_bind = p2sb_child_post_bind, + .flags = DM_FLAG_OS_PREPARE, };

This binding currently has a flags cell but it is not used. Make use of it to create ACPI tables for interrupts.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/acpi_gpe.c | 22 +++++++++++++++++++ .../interrupt-controller/x86-irq.h | 14 ++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/x86-irq.h

diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c index ccc2622b23..239d8319e9 100644 --- a/arch/x86/cpu/acpi_gpe.c +++ b/arch/x86/cpu/acpi_gpe.c @@ -5,9 +5,12 @@ */

#include <common.h> +#include <acpi_device.h> #include <dm.h> #include <irq.h> #include <asm/io.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/x86-irq.h>

struct acpi_gpe_priv { ulong acpi_base; @@ -56,6 +59,24 @@ static int acpi_gpe_ofdata_to_platdata(struct udevice *dev) static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args) { irq->id = args->args[0]; + irq->flags = args->args[1]; + + return 0; +} + +static int acpi_gpe_get_acpi(const struct irq *irq, struct acpi_irq *acpi_irq) +{ + memset(acpi_irq, '\0', sizeof(*acpi_irq)); + acpi_irq->pin = irq->id; + acpi_irq->mode = irq->flags & IRQ_TYPE_EDGE_BOTH ? + ACPI_IRQ_EDGE_TRIGGERED : ACPI_IRQ_LEVEL_TRIGGERED; + acpi_irq->polarity = irq->flags & + (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW) ? + ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH; + acpi_irq->shared = irq->flags & X86_IRQ_TYPE_SHARED ? + ACPI_IRQ_SHARED : ACPI_IRQ_EXCLUSIVE; + acpi_irq->wake = irq->flags & X86_IRQ_TYPE_WAKE ? ACPI_IRQ_WAKE : + ACPI_IRQ_NO_WAKE;

return 0; } @@ -63,6 +84,7 @@ static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args) static const struct irq_ops acpi_gpe_ops = { .read_and_clear = acpi_gpe_read_and_clear, .of_xlate = acpi_gpe_of_xlate, + .get_acpi = acpi_gpe_get_acpi, };

static const struct udevice_id acpi_gpe_ids[] = { diff --git a/include/dt-bindings/interrupt-controller/x86-irq.h b/include/dt-bindings/interrupt-controller/x86-irq.h new file mode 100644 index 0000000000..9e0b4612e1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/x86-irq.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + * + * This provides additional flags used by x86. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_X86_IRQ_H + +#define X86_IRQ_TYPE_SHARED (1 << 4) +#define X86_IRQ_TYPE_WAKE (1 << 5) + +#endif

This function sounds like something that is called when U-Boot is about to jump to Linux. In fact it is an init function.

Rename it to reduce confusion.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/coreboot/coreboot.c | 4 ++-- arch/x86/cpu/cpu.c | 8 ++++---- arch/x86/cpu/efi/app.c | 2 +- arch/x86/cpu/quark/quark.c | 2 +- arch/x86/lib/fsp/fsp_common.c | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 0c4c6348d1..874fdfc17e 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -40,7 +40,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); }

-static void board_final_cleanup(void) +static void board_final_init(void) { /* * Un-cache the ROM so the kernel has one @@ -78,7 +78,7 @@ int last_stage_init(void) if (CONFIG_IS_ENABLED(USB_KEYBOARD)) usb_init();

- board_final_cleanup(); + board_final_init();

return 0; } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 3891de088f..a2df92cec9 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -175,10 +175,10 @@ void show_boot_progress(int val)

#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) /* - * Implement a weak default function for boards that optionally - * need to clean up the system before jumping to the kernel. + * Implement a weak default function for boards that need to do some final init + * before the system is ready. */ -__weak void board_final_cleanup(void) +__weak void board_final_init(void) { }

@@ -186,7 +186,7 @@ int last_stage_init(void) { struct acpi_fadt __maybe_unused *fadt;

- board_final_cleanup(); + board_final_init();

#ifdef CONFIG_HAVE_ACPI_RESUME fadt = acpi_find_fadt(); diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index 13077411dc..d92153d922 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -23,7 +23,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); }

-void board_final_cleanup(void) +void board_final_init(void) { }

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index d6611eea5d..912eca9299 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -360,7 +360,7 @@ int arch_misc_init(void) return 0; }

-void board_final_cleanup(void) +void board_final_init(void) { struct quark_rcba *rcba; u32 base, val; diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 5eff0f99aa..8a6108fb32 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -45,7 +45,7 @@ int fsp_init_phase_pci(void) return status ? -EPERM : 0; }

-void board_final_cleanup(void) +void board_final_init(void) { u32 status;

Add ASL files for the Chrome OS EC, taken from coreboot.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/acpi/cros_ec/ac.asl | 22 + arch/x86/include/asm/acpi/cros_ec/als.asl | 56 ++ arch/x86/include/asm/acpi/cros_ec/battery.asl | 411 +++++++++++++ arch/x86/include/asm/acpi/cros_ec/cros_ec.asl | 57 ++ arch/x86/include/asm/acpi/cros_ec/ec.asl | 557 ++++++++++++++++++ arch/x86/include/asm/acpi/cros_ec/emem.asl | 53 ++ .../asm/acpi/cros_ec/keyboard_backlight.asl | 52 ++ arch/x86/include/asm/acpi/cros_ec/pd.asl | 15 + arch/x86/include/asm/acpi/cros_ec/superio.asl | 159 +++++ arch/x86/include/asm/acpi/cros_ec/tbmc.asl | 23 + 10 files changed, 1405 insertions(+) create mode 100644 arch/x86/include/asm/acpi/cros_ec/ac.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/als.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/battery.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/cros_ec.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/ec.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/emem.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/pd.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/superio.asl create mode 100644 arch/x86/include/asm/acpi/cros_ec/tbmc.asl

diff --git a/arch/x86/include/asm/acpi/cros_ec/ac.asl b/arch/x86/include/asm/acpi/cros_ec/ac.asl new file mode 100644 index 0000000000..80e0ebd3ad --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/ac.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { _SB }) + + Method (_PSR) + { + Return (ACEX) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/als.asl b/arch/x86/include/asm/acpi/cros_ec/als.asl new file mode 100644 index 0000000000..f3d40f889c --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/als.asl @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + */ + +Device (ALS) +{ + Name (_HID, "ACPI0008") + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } + + /* + * Returns the current ambient light illuminance reading in lux + * + * 0: Reading is below the range of sensitivity of the sensor + * -1: Reading is above the range or sensitivity of the sensor + */ + Method (_ALI, 0, NotSerialized) + { + Return (^^ALS0) + } + + /* + * Returns a recommended polling frequency in tenths of seconds + * + * 0: No need to poll, async notifications will indicate changes + */ + Name (_ALP, 10) + + /* + * Returns a package of packages where each tuple consists of a pair + * of integers mapping ambient light illuminance to display brightness. + * + * {<display luminance adjustment>, <ambient light illuminance>} + * + * Ambient light illuminance values are specified in lux. + * + * Display luminance adjustment values are relative percentages where + * 100 is no (0%) display brightness adjustment. Values <100 indicate + * negative adjustment (dimming) and values >100 indicate positive + * adjustment (brightening). + * + * This is currently unused by the Linux kernel ACPI ALS driver but + * is required by the ACPI specification so just define a basic two + * point response curve. + */ + Name (_ALR, Package () + { + Package () { 70, 30 }, // Min { -30% adjust at 30 lux } + Package () { 150, 1000 } // Max { +50% adjust at 1000 lux } + }) +} diff --git a/arch/x86/include/asm/acpi/cros_ec/battery.asl b/arch/x86/include/asm/acpi/cros_ec/battery.asl new file mode 100644 index 0000000000..f106088231 --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/battery.asl @@ -0,0 +1,411 @@ +/*/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + */ + +// Scope (EC0) + +/* Mutex for EC battery index interface */ +Mutex (BATM, 0) + +// Wait for desired battery index to be presented in shared memory +// Arg0 = battery index +// Returns Zero on success, One on error. +Method (BTSW, 1) +{ +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + If (LEqual (BTIX, Arg0)) { + Return (Zero) + } + If (LGreaterEqual (Arg0, BTCN)) { + Return (One) + } + Store (Arg0, _SB.PCI0.LPCB.EC0.BTID) + Store (5, Local0) // Timeout 5 msec + While (LNotEqual (BTIX, Arg0)) + { + Sleep (1) + Decrement (Local0) + If (LEqual (Local0, Zero)) + { + Return (One) + } + } +#else + If (LNotEqual (0, Arg0)) { + Return (One) + } +#endif + Return (Zero) +} + +// _STA implementation. +// Arg0 = battery index +Method (BSTA, 1, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Zero) + } + + If (And(Not(BTSW (Arg0)), BTEX)) { + Store (0x1F, Local0) + } Else { + Store (0x0F, Local0) + } + + Release (^BATM) + Return (Local0) +} + +// _BIF implementation. +// Arg0 = battery index +// Arg1 = PBIF +Method (BBIF, 2, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Arg1) + } + + If (BTSW (Arg0)) { + Release (^BATM) + Return (Arg1) + } + // Last Full Charge Capacity + Store (BTDF, Index (Arg1, 2)) + + // Design Voltage + Store (BTDV, Index (Arg1, 4)) + + // Design Capacity + Store (BTDA, Local0) + Store (Local0, Index (Arg1, 1)) + + // Design Capacity of Warning + Divide (Multiply (Local0, DWRN), 100, , Local2) + Store (Local2, Index (Arg1, 5)) + + // Design Capacity of Low + Divide (Multiply (Local0, DLOW), 100, , Local2) + Store (Local2, Index (Arg1, 6)) + + // Get battery info from mainboard + Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 9)) + Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 10)) + Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 12)) + + Release (^BATM) + Return (Arg1) +} + +// _BIX implementation. +// Arg0 = battery index +// Arg1 = PBIX +Method (BBIX, 2, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Arg1) + } + + If (BTSW (Arg0)) { + Release (^BATM) + Return (Arg1) + } + // Last Full Charge Capacity + Store (BTDF, Index (Arg1, 3)) + + // Design Voltage + Store (BTDV, Index (Arg1, 5)) + + // Design Capacity + Store (BTDA, Local0) + Store (Local0, Index (Arg1, 2)) + + // Design Capacity of Warning + Divide (Multiply (Local0, DWRN), 100, , Local2) + Store (Local2, Index (Arg1, 6)) + + // Design Capacity of Low + Divide (Multiply (Local0, DLOW), 100, , Local2) + Store (Local2, Index (Arg1, 7)) + + // Cycle Count + Store (BTCC, Index (Arg1, 8)) + + // Get battery info from mainboard + Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 16)) + Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 17)) + Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 19)) + + Release (^BATM) + Return (Arg1) +} + +// _BST implementation. +// Arg0 = battery index +// Arg1 = PBST +// Arg2 = BSTP +// Arg3 = BFWK +Method (BBST, 4, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Arg1) + } + + If (BTSW (Arg0)) { + Release (^BATM) + Return (Arg1) + } + // + // 0: BATTERY STATE + // + // bit 0 = discharging + // bit 1 = charging + // bit 2 = critical level + // + Store (Zero, Local1) + + // Check if AC is present + If (ACEX) { + If (BFCG) { + Store (0x02, Local1) + } ElseIf (BFDC) { + Store (0x01, Local1) + } + } Else { + // Always discharging when on battery power + Store (0x01, Local1) + } + + // Check for critical battery level + If (BFCR) { + Or (Local1, 0x04, Local1) + } + Store (Local1, Index (Arg1, 0)) + + // Notify if battery state has changed since last time + If (LNotEqual (Local1, DeRefOf (Arg2))) { + Store (Local1, Arg2) + If (LEqual(Arg0, 0)) { + Notify (BAT0, 0x80) + } +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + Else { + Notify (BAT1, 0x80) + } +#endif + } + + // + // 1: BATTERY PRESENT RATE + // + Store (BTPR, Index (Arg1, 1)) + + // + // 2: BATTERY REMAINING CAPACITY + // + Store (BTRA, Local1) + If (LAnd (Arg3, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) { + // On AC power and battery is neither charging + // nor discharging. Linux expects a full battery + // to report same capacity as last full charge. + // https://bugzilla.kernel.org/show_bug.cgi?id=12632 + Store (BTDF, Local2) + + // See if within ~6% of full + ShiftRight (Local2, 4, Local3) + If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), + LLess (Local1, Add (Local2, Local3)))) + { + Store (Local2, Local1) + } + } + Store (Local1, Index (Arg1, 2)) + + // + // 3: BATTERY PRESENT VOLTAGE + // + Store (BTVO, Index (Arg1, 3)) + + Release (^BATM) + Return (Arg1) +} + +Device (BAT0) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { _SB }) + + Name (PBIF, Package () { + 0x00000001, // 0x00: Power Unit: mAh + 0xFFFFFFFF, // 0x01: Design Capacity + 0xFFFFFFFF, // 0x02: Last Full Charge Capacity + 0x00000001, // 0x03: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x04: Design Voltage + 0x00000003, // 0x05: Design Capacity of Warning + 0xFFFFFFFF, // 0x06: Design Capacity of Low + 0x00000001, // 0x07: Capacity Granularity 1 + 0x00000001, // 0x08: Capacity Granularity 2 + "", // 0x09: Model Number + "", // 0x0a: Serial Number + "LION", // 0x0b: Battery Type + "" // 0x0c: OEM Information + }) + + Name (PBIX, Package () { + 0x00000000, // 0x00: Revision + 0x00000001, // 0x01: Power Unit: mAh + 0xFFFFFFFF, // 0x02: Design Capacity + 0xFFFFFFFF, // 0x03: Last Full Charge Capacity + 0x00000001, // 0x04: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x05: Design Voltage + 0x00000003, // 0x06: Design Capacity of Warning + 0xFFFFFFFF, // 0x07: Design Capacity of Low + 0x00000000, // 0x08: Cycle Count + 0x00018000, // 0x09: Measurement Accuracy (98.3%?) + 0x000001F4, // 0x0a: Max Sampling Time (500ms) + 0x0000000a, // 0x0b: Min Sampling Time (10ms) + 0xFFFFFFFF, // 0x0c: Max Averaging Interval + 0xFFFFFFFF, // 0x0d: Min Averaging Interval + 0x00000001, // 0x0e: Capacity Granularity 1 + 0x00000001, // 0x0f: Capacity Granularity 2 + "", // 0x10 Model Number + "", // 0x11: Serial Number + "LION", // 0x12: Battery Type + "" // 0x13: OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // 0x00: Battery State + 0xFFFFFFFF, // 0x01: Battery Present Rate + 0xFFFFFFFF, // 0x02: Battery Remaining Capacity + 0xFFFFFFFF, // 0x03: Battery Present Voltage + }) + Name (BSTP, Zero) + + // Workaround for full battery status, disabled by default + Name (BFWK, Zero) + + // Method to enable full battery workaround + Method (BFWE) + { + Store (One, BFWK) + } + + // Method to disable full battery workaround + Method (BFWD) + { + Store (Zero, BFWK) + } + + Method (_STA, 0, Serialized) + { + Return (BSTA (0)) + } + + Method (_BIF, 0, Serialized) + { + Return (BBIF (0, PBIF)) + } + + Method (_BIX, 0, Serialized) + { + Return (BBIX (0, PBIX)) + } + + Method (_BST, 0, Serialized) + { + Return (BBST (0, PBST, RefOf (BSTP), BFWK)) + } +} + +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE +Device (BAT1) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { _SB }) + + Name (PBIF, Package () { + 0x00000001, // 0x00: Power Unit: mAh + 0xFFFFFFFF, // 0x01: Design Capacity + 0xFFFFFFFF, // 0x02: Last Full Charge Capacity + 0x00000001, // 0x03: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x04: Design Voltage + 0x00000003, // 0x05: Design Capacity of Warning + 0xFFFFFFFF, // 0x06: Design Capacity of Low + 0x00000001, // 0x07: Capacity Granularity 1 + 0x00000001, // 0x08: Capacity Granularity 2 + "", // 0x09: Model Number + "", // 0x0a: Serial Number + "LION", // 0x0b: Battery Type + "" // 0x0c: OEM Information + }) + + Name (PBIX, Package () { + 0x00000000, // 0x00: Revision + 0x00000001, // 0x01: Power Unit: mAh + 0xFFFFFFFF, // 0x02: Design Capacity + 0xFFFFFFFF, // 0x03: Last Full Charge Capacity + 0x00000001, // 0x04: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x05: Design Voltage + 0x00000003, // 0x06: Design Capacity of Warning + 0xFFFFFFFF, // 0x07: Design Capacity of Low + 0x00000000, // 0x08: Cycle Count + 0x00018000, // 0x09: Measurement Accuracy (98.3%?) + 0x000001F4, // 0x0a: Max Sampling Time (500ms) + 0x0000000a, // 0x0b: Min Sampling Time (10ms) + 0xFFFFFFFF, // 0x0c: Max Averaging Interval + 0xFFFFFFFF, // 0x0d: Min Averaging Interval + 0x00000001, // 0x0e: Capacity Granularity 1 + 0x00000001, // 0x0f: Capacity Granularity 2 + "", // 0x10 Model Number + "", // 0x11: Serial Number + "LION", // 0x12: Battery Type + "" // 0x13: OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // 0x00: Battery State + 0xFFFFFFFF, // 0x01: Battery Present Rate + 0xFFFFFFFF, // 0x02: Battery Remaining Capacity + 0xFFFFFFFF, // 0x03: Battery Present Voltage + }) + Name (BSTP, Zero) + + // Workaround for full battery status, disabled by default + Name (BFWK, Zero) + + // Method to enable full battery workaround + Method (BFWE) + { + Store (One, BFWK) + } + + // Method to disable full battery workaround + Method (BFWD) + { + Store (Zero, BFWK) + } + + Method (_STA, 0, Serialized) + { + Return (BSTA (1)) + } + + Method (_BIF, 0, Serialized) + { + Return (BBIF (1, PBIF)) + } + + Method (_BIX, 0, Serialized) + { + Return (BBIX (1, PBIX)) + } + + Method (_BST, 0, Serialized) + { + Return (BBST (1, PBST, RefOf (BSTP), BFWK)) + } +} +#endif diff --git a/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl new file mode 100644 index 0000000000..9f50185b70 --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Google Inc. + */ + +Device (CREC) +{ + Name (_HID, "GOOG0004") + Name (_UID, 1) + Name (_DDN, "EC Command Device") +#ifdef EC_ENABLE_WAKE_PIN + Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) +#endif + +#ifdef EC_ENABLE_SYNC_IRQ + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive) + { + EC_SYNC_IRQ + } + }) +#endif + +#ifdef EC_ENABLE_SYNC_IRQ_GPIO + Name (_CRS, ResourceTemplate () + { + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, + "\_SB.GPIO", 0x00, ResourceConsumer, ,) + { + EC_SYNC_IRQ + } + }) +#endif + +#ifdef EC_ENABLE_MKBP_DEVICE + Device (CKSC) + { + Name (_HID, "GOOG0007") + Name (_UID, 1) + Name (_DDN, "EC MKBP Device") + } +#endif + +#ifdef EC_ENABLE_CBAS_DEVICE + Device (CBAS) + { + Name (_HID, "GOOG000B") + Name (_UID, 1) + Name (_DDN, "EC Base Switch Device") + } +#endif + Method(_STA, 0) + { + Return (0xB) + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/ec.asl b/arch/x86/include/asm/acpi/cros_ec/ec.asl new file mode 100644 index 0000000000..03f57f25a2 --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/ec.asl @@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +// Mainboard specific throttle handler +#ifdef DPTF_ENABLE_CHARGER +External (_SB.DPTF.TCHG, DeviceObj) +#endif + + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, EC_SCI_GPI) + Name (TOFS, EC_TEMP_SENSOR_OFFSET) + Name (TNCA, EC_TEMP_SENSOR_NOT_CALIBRATED) + Name (TNOP, EC_TEMP_SENSOR_NOT_POWERED) + Name (TBAD, EC_TEMP_SENSOR_ERROR) + Name (TNPR, EC_TEMP_SENSOR_NOT_PRESENT) + Name (DWRN, 15) // Battery capacity warning at 15% + Name (DLOW, 10) // Battery capacity low at 10% + + OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x00), + RAMV, 8, // EC RAM Version + TSTB, 8, // Test Byte + TSTC, 8, // Complement of Test Byte + KBLV, 8, // Keyboard Backlight value + FAND, 8, // Set Fan Duty Cycle + PATI, 8, // Programmable Auxiliary Trip Sensor ID + PATT, 8, // Programmable Auxiliary Trip Threshold + PATC, 8, // Programmable Auxiliary Trip Commit + CHGL, 8, // Charger Current Limit + TBMD, 1, // Tablet mode + DDPN, 3, // Device DPTF Profile Number + // DFUD must be 0 for the other 31 values to be valid + Offset (0x0a), + DFUD, 1, // Device Features Undefined + FLSH, 1, // Flash commands present + PFAN, 1, // PWM Fan control present + KBLE, 1, // Keyboard Backlight present + LTBR, 1, // Lightbar present + LEDC, 1, // LED control + MTNS, 1, // Motion sensors present + KEYB, 1, // EC is keyboard controller + PSTR, 1, // Persistent storage + P80P, 1, // EC serves I/O Port 80h + THRM, 1, // EC supports thermal management + SBKL, 1, // Screen backlight switch present + WIFI, 1, // WIFI switch present + HOST, 1, // EC monitors host events (eg SCI, SMI) + GPIO, 1, // EC provides GPIO commands + I2CB, 1, // EC provides I2C controller access + CHRG, 1, // EC provides commands for charger control + BATT, 1, // Simply Battery support + SBAT, 1, // Smart Battery support + HANG, 1, // EC can detect host hang + PMUI, 1, // Power Information + DSEC, 1, // another EC exists downstream + UPDC, 1, // supports USB Power Delivery + UMUX, 1, // supports USB Mux + MSFF, 1, // Motion Sense has FIFO + TVST, 1, // supports temporary secure vstore + TCMV, 1, // USB Type C Muxing is virtual (host assisted) + RTCD, 1, // EC provides an RTC device + FPRD, 1, // EC provides a fingerprint reader device + TPAD, 1, // EC provides a touchpad device + RWSG, 1, // EC has RWSIG task enabled + DEVE, 1, // EC supports device events + // make sure we're within our space envelope + Offset (0x0e), + Offset (0x12), + BTID, 8, // Battery index that host wants to read + USPP, 8, // USB Port Power +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) + OperationRegion (EMEM, EmbeddedControl, + EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE) + Field (EMEM, ByteAcc, Lock, Preserve) +#else + OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE) + Field (EMEM, ByteAcc, NoLock, Preserve) +#endif + { + #include "emem.asl" + } + +#ifdef EC_ENABLE_LID_SWITCH + /* LID Switch */ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Return (^^LIDS) + } + +#ifdef EC_ENABLE_WAKE_PIN + Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) +#endif + } +#endif + + Method (TINS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0) { Return (TIN0) } + Case (1) { Return (TIN1) } + Case (2) { Return (TIN2) } + Case (3) { Return (TIN3) } + Case (4) { Return (TIN4) } + Case (5) { Return (TIN5) } + Case (6) { Return (TIN6) } + Case (7) { Return (TIN7) } + Case (8) { Return (TIN8) } + Case (9) { Return (TIN9) } + Default { Return (TIN0) } + } + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, + EC_LPC_ADDR_ACPI_DATA, + EC_LPC_ADDR_ACPI_DATA, + 0, 1) + IO (Decode16, + EC_LPC_ADDR_ACPI_CMD, + EC_LPC_ADDR_ACPI_CMD, + 0, 1) + }) + Return (ECMD) + } + + Method (_REG, 2, NotSerialized) + { + // Initialize AC power state + Store (ACEX, \PWRS) + + // Initialize LID switch state + Store (LIDS, \LIDS) + } + + /* Read requested temperature and check against EC error values */ + Method (TSRD, 1, Serialized) + { + Store (_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0) + + /* Check for sensor not calibrated */ + If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TNCA)) { + Return (Zero) + } + + /* Check for sensor not present */ + If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TNPR)) { + Return (Zero) + } + + /* Check for sensor not powered */ + If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TNOP)) { + Return (Zero) + } + + /* Check for sensor bad reading */ + If (LEqual (Local0, _SB.PCI0.LPCB.EC0.TBAD)) { + Return (Zero) + } + + /* Adjust by offset to get Kelvin */ + Add (_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + /* Convert to 1/10 Kelvin */ + Multiply (Local0, 10, Local0) + + Return (Local0) + } + + // Lid Closed Event + Method (_Q01, 0, NotSerialized) + { + Store ("EC: LID CLOSE", Debug) + Store (LIDS, \LIDS) +#ifdef EC_ENABLE_LID_SWITCH + Notify (LID0, 0x80) +#endif + } + + // Lid Open Event + Method (_Q02, 0, NotSerialized) + { + Store ("EC: LID OPEN", Debug) + Store (LIDS, \LIDS) + Notify (CREC, 0x2) +#ifdef EC_ENABLE_LID_SWITCH + Notify (LID0, 0x80) +#endif + } + + // Power Button + Method (_Q03, 0, NotSerialized) + { + Store ("EC: POWER BUTTON", Debug) + } + + // AC Connected + Method (_Q04, 0, NotSerialized) + { + Store ("EC: AC CONNECTED", Debug) + Store (ACEX, \PWRS) + Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER + If (CondRefOf (_SB.DPTF.TCHG)) { + Notify (_SB.DPTF.TCHG, 0x80) + } +#endif + \PNOT () + } + + // AC Disconnected + Method (_Q05, 0, NotSerialized) + { + Store ("EC: AC DISCONNECTED", Debug) + Store (ACEX, \PWRS) + Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER + If (CondRefOf (_SB.DPTF.TCHG)) { + Notify (_SB.DPTF.TCHG, 0x80) + } +#endif + \PNOT () + } + + // Battery Low Event + Method (_Q06, 0, NotSerialized) + { + Store ("EC: BATTERY LOW", Debug) + Notify (BAT0, 0x80) + } + + // Battery Critical Event + Method (_Q07, 0, NotSerialized) + { + Store ("EC: BATTERY CRITICAL", Debug) + Notify (BAT0, 0x80) + } + + // Battery Info Event + Method (_Q08, 0, NotSerialized) + { + Store ("EC: BATTERY INFO", Debug) + Notify (BAT0, 0x81) +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + If (CondRefOf (BAT1)) { + Notify (BAT1, 0x81) + } +#endif + } + + // Thermal Overload Event + Method (_Q0A, 0, NotSerialized) + { + Store ("EC: THERMAL OVERLOAD", Debug) + Notify (_TZ, 0x80) + } + + // Thermal Event + Method (_Q0B, 0, NotSerialized) + { + Store ("EC: THERMAL", Debug) + Notify (_TZ, 0x80) + } + + // USB Charger + Method (_Q0C, 0, NotSerialized) + { + Store ("EC: USB CHARGER", Debug) + } + + // Key Pressed + Method (_Q0D, 0, NotSerialized) + { + Store ("EC: KEY PRESSED", Debug) + Notify (CREC, 0x2) + } + + // Thermal Shutdown Imminent + Method (_Q10, 0, NotSerialized) + { + Store ("EC: THERMAL SHUTDOWN", Debug) + Notify (_TZ, 0x80) + } + + // Battery Shutdown Imminent + Method (_Q11, 0, NotSerialized) + { + Store ("EC: BATTERY SHUTDOWN", Debug) + Notify (BAT0, 0x80) + } + + // Throttle Start + Method (_Q12, 0, NotSerialized) + { +#ifdef EC_ENABLE_THROTTLING_HANDLER + Store ("EC: THROTTLE START", Debug) + _TZ.THRT (1) +#endif + } + + // Throttle Stop + Method (_Q13, 0, NotSerialized) + { +#ifdef EC_ENABLE_THROTTLING_HANDLER + Store ("EC: THROTTLE STOP", Debug) + _TZ.THRT (0) +#endif + } + +#ifdef EC_ENABLE_PD_MCU_DEVICE + // PD event + Method (_Q16, 0, NotSerialized) + { + Store ("EC: GOT PD EVENT", Debug) + Notify (ECPD, 0x80) + } +#endif + + // Battery Status + Method (_Q17, 0, NotSerialized) + { + Store ("EC: BATTERY STATUS", Debug) + Notify (BAT0, 0x80) +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + If (CondRefOf (BAT1)) { + Notify (BAT1, 0x80) + } +#endif + } + + // MKBP interrupt. + Method (_Q1B, 0, NotSerialized) + { + Store ("EC: MKBP", Debug) + Notify (CREC, 0x80) + } + + // TABLET mode switch Event + Method (_Q1D, 0, NotSerialized) + { + Store ("EC: TABLET mode switch Event", Debug) + Notify (CREC, 0x2) +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + _SB.DPTF.TPET() +#endif +#ifdef EC_ENABLE_TBMC_DEVICE + Notify (TBMC, 0x80) +#endif + } + + /* + * Dynamic Platform Thermal Framework support + */ + + /* Mutex for EC PAT interface */ + Mutex (PATM, 1) + + /* + * Set Aux Trip Point 0 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT0, 2, Serialized) + { + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + Store (ToInteger (Arg0), ^PATI) + + /* Temperature is passed in 1/10 Kelvin */ + Divide (ToInteger (Arg1), 10, , Local1) + + /* Adjust by EC temperature offset */ + Subtract (Local1, ^TOFS, ^PATT) + + /* Set commit value with SELECT=0 and ENABLE=1 */ + Store (0x02, ^PATC) + + Release (^PATM) + Return (1) + } + + /* + * Set Aux Trip Point 1 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT1, 2, Serialized) + { + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + Store (ToInteger (Arg0), ^PATI) + + /* Temperature is passed in 1/10 Kelvin */ + Divide (ToInteger (Arg1), 10, , Local1) + + /* Adjust by EC temperature offset */ + Subtract (Local1, ^TOFS, ^PATT) + + /* Set commit value with SELECT=1 and ENABLE=1 */ + Store (0x03, ^PATC) + + Release (^PATM) + Return (1) + } + + /* Disable Aux Trip Points + * Arg0 = Temp Sensor ID + */ + Method (PATD, 1, Serialized) + { + If (Acquire (^PATM, 1000)) { + Return (0) + } + + Store (ToInteger (Arg0), ^PATI) + Store (0x00, ^PATT) + + /* Disable PAT0 */ + Store (0x00, ^PATC) + + /* Disable PAT1 */ + Store (0x01, ^PATC) + + Release (^PATM) + Return (1) + } + + /* + * Thermal Threshold Event + */ + Method (_Q09, 0, NotSerialized) + { + If (LNot(Acquire (^PATM, 1000))) { + /* Read sensor ID for event */ + Store (^PATI, Local0) + + /* When sensor ID returns 0xFF then no more events */ + While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT)) + { +#ifdef HAVE_THERM_EVENT_HANDLER + _SB.DPTF.TEVT (Local0) +#endif + + /* Keep reaading sensor ID for event */ + Store (^PATI, Local0) + } + + Release (^PATM) + } + } + + /* + * Set Charger Current Limit + * Arg0 = Current Limit in 64mA steps + */ + Method (CHGS, 1, Serialized) + { + Store (ToInteger (Arg0), ^CHGL) + } + + /* + * Disable Charger Current Limit + */ + Method (CHGD, 0, Serialized) + { + Store (0xFF, ^CHGL) + } + + /* Read current Tablet mode */ + Method (RCTM, 0, NotSerialized) + { + Return (^TBMD) + } + + /* Read current Device DPTF Profile Number */ + Method (RCDP, 0, NotSerialized) + { + /* + * DDPN = 0 is reserved for backwards compatibility. + * If DDPN == 0 use TBMD to load appropriate DPTF table. + */ + If (LEqual (^DDPN, 0)) { + Return (^TBMD) + } Else { + Subtract (^DDPN, 1, Local0) + Return (Local0) + } + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER) + /* + * Enable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPS, 1, Serialized) + { + Or (USPP, ShiftLeft (1, Arg0), USPP) + } + + /* + * Disable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPC, 1, Serialized) + { + And (USPP, Not (ShiftLeft (1, Arg0)), USPP) + } +#endif + + #include "ac.asl" + #include "battery.asl" + #include "cros_ec.asl" + +#ifdef EC_ENABLE_ALS_DEVICE + #include "als.asl" +#endif + +#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT + #include "keyboard_backlight.asl" +#endif + +#ifdef EC_ENABLE_PD_MCU_DEVICE + #include "pd.asl" +#endif + +#ifdef EC_ENABLE_TBMC_DEVICE + #include "tbmc.asl" +#endif +} diff --git a/arch/x86/include/asm/acpi/cros_ec/emem.asl b/arch/x86/include/asm/acpi/cros_ec/emem.asl new file mode 100644 index 0000000000..681ca1c9de --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/emem.asl @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2015 The Chromium OS Authors. All rights reserved. + */ + +/* + * EMEM data may be accessed through port 62/66 or through LPC at 900h. + */ + +Offset (0x00), +TIN0, 8, // Temperature 0 +TIN1, 8, // Temperature 1 +TIN2, 8, // Temperature 2 +TIN3, 8, // Temperature 3 +TIN4, 8, // Temperature 4 +TIN5, 8, // Temperature 5 +TIN6, 8, // Temperature 6 +TIN7, 8, // Temperature 7 +TIN8, 8, // Temperature 8 +TIN9, 8, // Temperature 9 +Offset (0x10), +FAN0, 16, // Fan Speed 0 +Offset (0x24), +BTVR, 8, // Battery structure version +Offset (0x30), +LIDS, 1, // Lid Switch State +PBTN, 1, // Power Button Pressed +WPDI, 1, // Write Protect Disabled +RECK, 1, // Keyboard Initiated Recovery +RECD, 1, // Dedicated Recovery Mode +Offset (0x40), +BTVO, 32, // Battery Present Voltage +BTPR, 32, // Battery Present Rate +BTRA, 32, // Battery Remaining Capacity +ACEX, 1, // AC Present +BTEX, 1, // Battery Present +BFDC, 1, // Battery Discharging +BFCG, 1, // Battery Charging +BFCR, 1, // Battery Level Critical +Offset (0x4d), +BTCN, 8, // Battery Count +BTIX, 8, // Battery index +Offset (0x50), +BTDA, 32, // Battery Design Capacity +BTDV, 32, // Battery Design Voltage +BTDF, 32, // Battery Last Full Charge Capacity +BTCC, 32, // Battery Cycle Count +BMFG, 64, // Battery Manufacturer String +BMOD, 64, // Battery Model String +BSER, 64, // Battery Serial String +BTYP, 64, // Battery Type String +Offset (0x80), +ALS0, 16, // ALS reading 0 in lux diff --git a/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl new file mode 100644 index 0000000000..e6edd9680c --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Google Inc. + */ + +Scope (_SB) +{ + /* + * Chrome EC Keyboard Backlight interface + */ + Device (KBLT) + { + Name (_HID, "GOOG0002") + Name (_UID, 1) + + /* Ask EC if we even have a backlight + * Return 0xf (present, enabled, show in UI, functioning) or 0 + * + * With older EC codebases that don't support the Device + * Features bitfield, this reports the keyboard backlight as + * enabled since reads to undefined addresses in EC address + * space return 0xff and so KBLE will be 1. + */ + Method (_STA, 0, NotSerialized) + { + /* If query is unsupported, but this code is compiled + * in, assume the backlight exists physically. + */ + If (LEqual (1, _SB.PCI0.LPCB.EC0.DFUD)) { + Return (0xf) + } + /* If EC reports that backlight exists, trust it */ + If (LEqual (1, _SB.PCI0.LPCB.EC0.KBLE)) { + Return (0xf) + } + /* Otherwise: no device -> disable */ + Return (0) + } + + /* Read current backlight value */ + Method (KBQC, 0, NotSerialized) + { + Return (_SB.PCI0.LPCB.EC0.KBLV) + } + + /* Write new backlight value */ + Method (KBCM, 1, NotSerialized) + { + Store (Arg0, _SB.PCI0.LPCB.EC0.KBLV) + } + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/pd.asl b/arch/x86/include/asm/acpi/cros_ec/pd.asl new file mode 100644 index 0000000000..e55fde347c --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/pd.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + */ + +Device (ECPD) +{ + Name (_HID, "GOOG0003") + Name (_UID, 1) + Name (_DDN, "EC PD Device") + Method(_STA, 0) + { + Return (0xB) + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/superio.asl b/arch/x86/include/asm/acpi/cros_ec/superio.asl new file mode 100644 index 0000000000..7ddab1e3cf --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/superio.asl @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + */ + +/* + * Chrome OS Embedded Controller interface + * + * Constants that should be defined: + * + * SIO_EC_MEMMAP_ENABLE : Enable EC LPC memory map resources + * EC_LPC_ADDR_MEMMAP : Base address of memory map range + * EC_MEMMAP_SIZE : Size of memory map range + * + * SIO_EC_HOST_ENABLE : Enable EC host command interface resources + * EC_LPC_ADDR_HOST_DATA : EC host command interface data port + * EC_LPC_ADDR_HOST_CMD : EC host command interface command port + * EC_HOST_CMD_REGION0 : EC host command buffer + * EC_HOST_CMD_REGION1 : EC host command buffer + * EC_HOST_CMD_REGION_SIZE : EC host command buffer size + */ + +// Scope is _SB.PCI0.LPCB + +Device (SIO) { + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_MEMMAP_ENABLE + Device (ECMM) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 4) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP, + 0x08, EC_MEMMAP_SIZE) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP, + 0x08, EC_MEMMAP_SIZE) + }) + } +#endif + +#ifdef SIO_EC_HOST_ENABLE + Device (ECUI) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + EC_LPC_ADDR_HOST_DATA, EC_LPC_ADDR_HOST_DATA, + 0x01, 0x01) + IO (Decode16, + EC_LPC_ADDR_HOST_CMD, EC_LPC_ADDR_HOST_CMD, + 0x01, 0x01) + IO (Decode16, + EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, 0x08, + EC_HOST_CMD_REGION_SIZE) + IO (Decode16, + EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, 0x08, + EC_HOST_CMD_REGION_SIZE) + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, EC_LPC_ADDR_HOST_DATA, + EC_LPC_ADDR_HOST_DATA, 0x01, 0x01) + IO (Decode16, EC_LPC_ADDR_HOST_CMD, + EC_LPC_ADDR_HOST_CMD, 0x01, 0x01) + IO (Decode16, + EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, + 0x08, EC_HOST_CMD_REGION_SIZE) + IO (Decode16, + EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, + 0x08, EC_HOST_CMD_REGION_SIZE) + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_EC_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } +#endif +} + +#ifdef SIO_EC_ENABLE_PS2K +Device (PS2K) // Keyboard +{ + Name (_UID, 0) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + } + EndDependentFn () + }) +} +#endif diff --git a/arch/x86/include/asm/acpi/cros_ec/tbmc.asl b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl new file mode 100644 index 0000000000..bfe38d668e --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Google Inc. + */ + +Device (TBMC) +{ + Name (_HID, "GOOG0006") + Name (_UID, 1) + Name (_DDN, "Tablet Motion Control") + Method (TBMC) + { + If (LEqual (^^RCTM, One)) { + Return (0x1) + } Else { + Return (0x0) + } + } + Method(_STA, 0) + { + Return (0xB) + } +}

Add Apollo Lake ASL files, taken from coreboot.

Signed-off-by: Simon Glass sjg@chromium.org ---

.../include/asm/arch-apollolake/acpi/dptf.asl | 35 ++++ .../asm/arch-apollolake/acpi/globalnvs.asl | 41 ++++ .../include/asm/arch-apollolake/acpi/gpio.asl | 191 ++++++++++++++++++ .../asm/arch-apollolake/acpi/gpiolib.asl | 109 ++++++++++ .../include/asm/arch-apollolake/acpi/lpss.asl | 105 ++++++++++ .../asm/arch-apollolake/acpi/northbridge.asl | 120 +++++++++++ .../asm/arch-apollolake/acpi/pch_hda.asl | 77 +++++++ .../asm/arch-apollolake/acpi/pci_irqs.asl | 52 +++++ .../include/asm/arch-apollolake/acpi/pcie.asl | 22 ++ .../asm/arch-apollolake/acpi/pcie_port.asl | 113 +++++++++++ .../asm/arch-apollolake/acpi/platform.asl | 10 + .../asm/arch-apollolake/acpi/pmc_ipc.asl | 49 +++++ .../include/asm/arch-apollolake/acpi/scs.asl | 173 ++++++++++++++++ .../asm/arch-apollolake/acpi/soc_int.asl | 50 +++++ .../asm/arch-apollolake/acpi/southbridge.asl | 34 ++++ .../include/asm/arch-apollolake/acpi/xhci.asl | 33 +++ .../arch-apollolake/acpi/xhci_apl_ports.asl | 23 +++ .../arch-apollolake/acpi/xhci_glk_ports.asl | 24 +++ 18 files changed, 1261 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/dptf.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpio.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/lpss.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/platform.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/scs.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl new file mode 100644 index 0000000000..4c50bb45c0 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +#define DPTF_CPU_DEVICE TCPU +#define DPTF_CPU_ADDR 0x00000001 + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif diff --git a/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl new file mode 100644 index 0000000000..7854f7e1c5 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc alexandrux.gagniuc@intel.com for Intel Corp.) + */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/intel/apollolake/include/soc/nvs.h !!! + * + */ + +External (NVSA) + +OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + PCNT, 8, // 0x00 - Processor Count + PPCM, 8, // 0x01 - Max PPC State + LIDS, 8, // 0x02 - LID State + PWRS, 8, // 0x03 - AC Power State + DPTE, 8, // 0x04 - Enable DPTF + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console + PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index + GPEI, 64, // 0x11 - 0x18 - GPE Wake Source + NHLA, 64, // 0x19 - 0x20 - NHLT Address + NHLL, 32, // 0x21 - 0x24 - NHLT Length + PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SCDP, 8, // 0x29 - SD_CD GPIO portid + SCDO, 8, // 0x2A - GPIO pad offset relative to the community + UIOR, 8, // 0x2B - UART debug controller init on S3 resume + EPCS, 8, // 0x2C - SGX Enabled status + EMNA, 64, // 0x2D - 0x34 EPC base address + ELNG, 64, // 0x35 - 0x3C EPC Length + + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ + Offset (0x100), + #include <asm/acpi/cros_gnvs.asl> +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl new file mode 100644 index 0000000000..b0f892166b --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + */ +#include <asm/arch/gpio.h> +#include <asm/intel_pinctrl_defs.h> +// #include <intelblocks/pcr.h> +// #include <soc/pcr_ids.h> +#include <asm/arch/iomap.h> +#include <p2sb.h> +#include "gpiolib.asl" + +scope (_SB) { + + Device (GPO0) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_0_DESC) + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO1) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_1_DESC) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO2) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_2_DESC) + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO3) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_3_DESC) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Scope(_SB.PCI0) { + /* PERST Assertion + * Note: PERST is Active High + */ + Method (PRAS, 0x1, Serialized) + { + /* + * Assert PERST + * local1 - to toggle Tx pin of Dw0 + * local2 - Address of PERST + */ + Store (Arg0, Local2) + Store (_SB.GPC0 (Local2), Local1) + Or (Local1, PAD_CFG0_TX_STATE, Local1) + _SB.SPC0 (Local2, Local1) + } + + /* PERST DE-Assertion */ + Method (PRDA, 0x1, Serialized) + { + /* + * De-assert PERST + * local1 - to toggle Tx pin of Dw0 + * local2 - Address of PERST + */ + Store (Arg0, Local2) + Store (_SB.GPC0 (Local2), Local1) + And (Local1, Not (PAD_CFG0_TX_STATE), Local1) + _SB.SPC0 (Local2, Local1) + } + } + + /* + * Sleep button device ASL code. We are using this device to + * add the _PRW method for a dummy wake event to kernel so that + * before going to sleep kernel does not clear bit 15 in ACPI + * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit. + */ + Device (SLP) + { + Name (_HID, EisaId ("PNP0C0E")) + + Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 }) + } +} + +Scope(_GPE) +{ + /* + * Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads + * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable + * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI + * GPE0a_EN at 0x430 is reserved. + */ + Method(_L0F, 0) {} +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl new file mode 100644 index 0000000000..0eb808dc19 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +Scope (_SB) +{ + /* Get Pad Configuration DW0 register value */ + Method (GPC0, 0x1, Serialized) + { + /* Arg0 - GPIO DW0 address */ + Store (Arg0, Local0) + OperationRegion (PDW0, SystemMemory, Local0, 4) + Field (PDW0, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + /* Set Pad Configuration DW0 register value */ + Method (SPC0, 0x2, Serialized) + { + /* Arg0 - GPIO DW0 address */ + /* Arg1 - Value for DW0 register */ + Store (Arg0, Local0) + OperationRegion (PDW0, SystemMemory, Local0, 4) + Field (PDW0, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) + } + + /* Get Pad Configuration DW1 register value */ + Method (GPC1, 0x1, Serialized) + { + /* Arg0 - GPIO DW0 address */ + Store (Add (Arg0, 0x4), Local0) + OperationRegion (PDW1, SystemMemory, Local0, 4) + Field (PDW1, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + /* Set Pad Configuration DW1 register value */ + Method (SPC1, 0x2, Serialized) + { + /* Arg0 - GPIO DW0 address */ + /* Arg1 - Value for DW1 register */ + Store (Add (Arg0, 0x4), Local0) + OperationRegion (PDW1, SystemMemory, Local0, 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) + } + + /* Get DW0 address of a given pad */ + Method (GDW0, 0x2, Serialized) + { + /* Arg0 - GPIO portid */ + /* Arg1 - GPIO pad offset relative to the community */ + Store (0, Local1) + Or( Or (ShiftLeft (Arg0, 16), IOMAP_P2SB_BAR), + Local1, Local1) + Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply ( + GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1) + Return (Local1) + } + + /* Calculate HOSTSW_REG address */ + Method (CHSA, 0x1, Serialized) + { + /* Arg0 - GPIO pad offset relative to the community */ + Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1) + Return (Local1) + } + + /* Get Host ownership register of GPIO Community */ + Method (GHO, 0x2, Serialized) + { + /* Arg0 - GPIO portid */ + /* Arg1 - GPIO pad offset relative to the community */ + Store (CHSA (Arg1), Local1) + + OperationRegion (SHO0, SystemMemory, Or ( Or + (IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4) + Field (SHO0, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + /* Set Host ownership register of GPIO Community */ + Method (SHO, 0x3, Serialized) + { + /* Arg0 - GPIO portid */ + /* Arg1 - GPIO pad offset relative to the community */ + /* Arg2 - Value for Host own register */ + Store (CHSA (Arg1), Local1) + + OperationRegion (SHO0, SystemMemory, Or ( Or + (IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4) + Field (SHO0, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Store (Arg2, TEMP) + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl new file mode 100644 index 0000000000..bc3eabba60 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + */ + +scope (_SB.PCI0) { + + /* LPIO1 PWM */ + Device(PWM) { + Name (_ADR, 0x001A0000) + Name (_DDN, "Intel(R) PWM Controller") + } + + /* LPIO1 HS-UART #1 */ + Device(URT1) { + Name (_ADR, 0x00180000) + Name (_DDN, "Intel(R) HS-UART Controller #1") + } + + /* LPIO1 HS-UART #2 */ + Device(URT2) { + Name (_ADR, 0x00180001) + Name (_DDN, "Intel(R) HS-UART Controller #2") + } + + /* LPIO1 HS-UART #3 */ + Device(URT3) { + Name (_ADR, 0x00180002) + Name (_DDN, "Intel(R) HS-UART Controller #3") + } + + /* LPIO1 HS-UART #4 */ + Device(URT4) { + Name (_ADR, 0x00180003) + Name (_DDN, "Intel(R) HS-UART Controller #4") + } + + /* LPIO1 SPI */ + Device(SPI1) { + Name (_ADR, 0x00190000) + Name (_DDN, "Intel(R) SPI Controller #1") + } + + /* LPIO1 SPI #2 */ + Device(SPI2) { + Name (_ADR, 0x00190001) + Name (_DDN, "Intel(R) SPI Controller #2") + } + + /* LPIO1 SPI #3 */ + Device(SPI3) { + Name (_ADR, 0x00190002) + Name (_DDN, "Intel(R) SPI Controller #3") + } + + + /* LPIO2 I2C #0 */ + Device(I2C0) { + Name (_ADR, 0x00160000) + Name (_DDN, "Intel(R) I2C Controller #0") + } + + /* LPIO2 I2C #1 */ + Device(I2C1) { + Name (_ADR, 0x00160001) + Name (_DDN, "Intel(R) I2C Controller #1") + } + + /* LPIO2 I2C #2 */ + Device(I2C2) { + Name (_ADR, 0x00160002) + Name (_DDN, "Intel(R) I2C Controller #2") + } + + /* LPIO2 I2C #3 */ + Device(I2C3) { + Name (_ADR, 0x00160003) + Name (_DDN, "Intel(R) I2C Controller #3") + } + + /* LPIO2 I2C #4 */ + Device(I2C4) { + Name (_ADR, 0x00170000) + Name (_DDN, "Intel(R) I2C Controller #4") + } + + /* LPIO2 I2C #5 */ + Device(I2C5) { + Name (_ADR, 0x00170001) + Name (_DDN, "Intel(R) I2C Controller #5") + } + + /* LPIO2 I2C #6 */ + Device(I2C6) { + Name (_ADR, 0x00170002) + Name (_DDN, "Intel(R) I2C Controller #6") + } + + /* LPIO2 I2C #7 */ + Device(I2C7) { + Name (_ADR, 0x00170003) + Name (_DDN, "Intel(R) I2C Controller #7") + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl new file mode 100644 index 0000000000..ff5657abd0 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + */ + + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + Name(_BBN, 0) + +Device (MCHC) +{ + Name (_ADR, 0x00000000) /*Dev0 Func0 */ + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), + TUUD, 64, /* Top of Upper Used Memory */ + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } +} +Name (MCRS, ResourceTemplate() +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) + + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) + + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, ^STOM._MIN, GMIN) + CreateDwordField(MCRS, ^STOM._MAX, GMAX) + CreateDwordField(MCRS, ^STOM._LEN, GLEN) + + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) + + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, ^PM02._MIN, MMIN) + CreateQwordField (MCRS, ^PM02._MAX, MMAX) + CreateQwordField (MCRS, ^PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, 0x1000000000)) + { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl new file mode 100644 index 0000000000..cc3b7a769d --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016 Google Inc. + * + */ + +/* Audio Controller - Device 14, Function 0 */ + +Device (HDAS) +{ + Name (_ADR, 0x000E0000) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate() { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, Cacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + } + ) + + /* can wake up from S3 state */ + Name (_PRW, Package() { GPE0A_AVS_PME_STS, 3 }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } + Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000000..21a1ca9ff9 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + */ + +#include "soc_int.asl" + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, NPK_INT}, + Package(){0x0000FFFF, 1, 0, PUNIT_INT}, + Package(){0x0002FFFF, 0, 0, GEN_INT}, + Package(){0x0003FFFF, 0, 0, IUNIT_INT}, + Package(){0x000DFFFF, 1, 0, PMC_INT}, + Package(){0x000EFFFF, 0, 0, AUDIO_INT}, + Package(){0x000FFFFF, 0, 0, CSE_INT}, + Package(){0x0011FFFF, 0, 0, ISH_INT}, + Package(){0x0012FFFF, 0, 0, SATA_INT}, + Package(){0x0013FFFF, 0, 0, PIRQA_INT}, + Package(){0x0013FFFF, 1, 0, PIRQB_INT}, + Package(){0x0013FFFF, 2, 0, PIRQC_INT}, + Package(){0x0013FFFF, 3, 0, PIRQD_INT}, + Package(){0x0014FFFF, 0, 0, PIRQB_INT}, + Package(){0x0014FFFF, 1, 0, PIRQC_INT}, + Package(){0x0014FFFF, 2, 0, PIRQD_INT}, + Package(){0x0014FFFF, 3, 0, PIRQA_INT}, + Package(){0x0015FFFF, 0, 0, XHCI_INT}, + Package(){0x0015FFFF, 1, 0, XDCI_INT}, + Package(){0x0016FFFF, 0, 0, I2C0_INT}, + Package(){0x0016FFFF, 1, 0, I2C1_INT}, + Package(){0x0016FFFF, 2, 0, I2C2_INT}, + Package(){0x0016FFFF, 3, 0, I2C3_INT}, + Package(){0x0017FFFF, 0, 0, I2C4_INT}, + Package(){0x0017FFFF, 1, 0, I2C5_INT}, + Package(){0x0017FFFF, 2, 0, I2C6_INT}, + Package(){0x0017FFFF, 3, 0, I2C7_INT}, + Package(){0x0018FFFF, 0, 0, UART0_INT}, + Package(){0x0018FFFF, 1, 0, UART1_INT}, + Package(){0x0018FFFF, 2, 0, UART2_INT}, + Package(){0x0018FFFF, 3, 0, UART3_INT}, + Package(){0x0019FFFF, 0, 0, SPI0_INT}, + Package(){0x0019FFFF, 1, 0, SPI1_INT}, + Package(){0x0019FFFF, 2, 0, SPI2_INT}, + Package(){0x001BFFFF, 0, 0, SDCARD_INT}, + Package(){0x001CFFFF, 0, 0, EMMC_INT}, + Package(){0x001EFFFF, 0, 0, SDIO_INT}, + Package(){0x001FFFFF, 1, 0, SMBUS_INT}, + }) +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl new file mode 100644 index 0000000000..ecff59ab1c --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation + */ + +/* PCIe Ports */ + +Device (RP01) +{ + Name (_ADR, 0x00140000) + Name (_DDN, "PCIe-B 0") + + #include "pcie_port.asl" +} + +Device (RP03) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "PCIe-A 0") + + #include "pcie_port.asl" +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl new file mode 100644 index 0000000000..12a08b4aa8 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation + */ + +/* Include in each PCIe Root Port device */ + +/* lowest D-state supported by + * PCIe root port during S0 state + */ +Name (_S0W, 4) + +Name (PDST, 0) /* present Detect status */ + +/* Dynamic Opregion needed to access registers + * when the controller is in D3 cold + */ +OperationRegion (PX01, PCI_Config, 0x00, 0xFF) +Field (PX01, AnyAcc, NoLock, Preserve) +{ + Offset(0x5A), + , 6, + PDS, 1, /* 6, Presence detect Change */ + Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0xF4), /* BLKPLLEN */ + , 10, + BPLL, 1, +} + +OperationRegion (PX02, PCI_Config, 0x338, 0x4) +Field (PX02, AnyAcc, NoLock, Preserve) +{ + , 26, + BDQA, 1 /* BLKDQDA */ +} + +PowerResource (PXP, 0, 0) +{ + /* Define the PowerResource for PCIe slot */ + Method (_STA, 0, Serialized) + { + Store (PDS, PDST) + If (LEqual (PDS, 1)) { + Return (0xf) + } Else { + Return (0) + } + } + + Method (_ON, 0, Serialized) + { + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* Enter this condition if device + * is connected + */ + + /* De-assert PERST */ + _SB.PCI0.PRDA (\PRT0) + + Store (0, BDQA) /* Set BLKDQDA to 0 */ + Store (0, BPLL) /* Set BLKPLLEN to 0 */ + + /* Set L23_Rdy to Detect Transition + * (L23R2DT) + */ + Store (1, L23R) + Sleep (16) + Store (0, Local0) + + /* Delay for transition Detect + * and link to train + */ + While (L23R) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + } /* End PDS condition check */ + } + + Method (_OFF, 0, Serialized) + { + /* Set L23_Rdy Entry Request (L23ER) */ + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* enter this condition if device + * is connected + */ + Store (1, L23E) + Sleep (16) + Store (0, Local0) + While (L23E) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + Store (1, BDQA) /* Set BLKDQDA to 1 */ + Store (1, BPLL) /* Set BLKPLLEN to 1 */ + + /* Assert PERST */ + _SB.PCI0.PRAS (\PRT0) + } /* End PDS condition check */ + } /* End of Method_OFF */ +} /* End PXP */ + +Name(_PR0, Package() { PXP }) +Name(_PR3, Package() { PXP }) diff --git a/arch/x86/include/asm/arch-apollolake/acpi/platform.asl b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl new file mode 100644 index 0000000000..b631a9fb38 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2016 Intel Corp + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> +#include <soc/intel/common/acpi/platform.asl> diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000000..4a592833cc --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corp. + */ + +#include <asm/arch/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 +#define PMIO_LIMIT 0x480 + +scope (_SB) { + Device (IPC1) + { + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) + Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) + Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) + IO (Decode16, IOMAP_ACPI_BASE, PMIO_LIMIT, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (SRAM_BASE_0, SBAS) + + Return (^RBUF) + } + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/scs.asl b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl new file mode 100644 index 0000000000..7d61861ea1 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +Scope (_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + Or ( Or (IOMAP_P2SB_BAR, + ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + Offset (0x08), + , 5, /* bit[5] represents Force Card Detect SD Card */ + GRR3, 1, /* GPPRVRW3 for SD Card detect Bypass. It's active high */ + } + + /* SCC power gate control method, this method must be serialized as + * multiple device will control the GENR register + * + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + if (LEqual(Arg0, 0x1)) { + Or (^GENR, Arg1, ^GENR) + } ElseIf (LEqual(Arg0, 0x0)){ + And (^GENR, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D")) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 9: Device Readiness Durations + * Returns a package of five integers covering + * various device related delays in PCIe Base Spec. + */ + If (LEqual (Arg2, 9)) { + /* + * Function 9 support for revision 3. + * ECN link for function definitions + * [https://pcisig.com/sites/default/files/ + * specification_documents/ + * ECN_fw_latency_optimization_final.pdf] + */ + If (LEqual (Arg1, 3)) { + /* + * Integer 0: FW reset time. + * Integer 1: FW data link up time. + * Integer 2: FW functional level reset + * time. + * Integer 3: FW D3 hot to D0 time. + * Integer 4: FW VF enable time. + * set ACPI constant Ones for elements + * where overriding the default value + * is not desired. + */ + Return (Package (5) {0, Ones, Ones, + Ones, Ones}) + } + } + } + Return (Buffer() { 0x00 }) + } + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } /* Device (SDHA) */ + + /* SD CARD */ + Device (SDCD) + { + Name (_ADR, 0x001B0000) + Name (_S0W, 4) /* _S0W: S0 Device Wake State */ + Name (SCD0, 0) /* Store SD_CD DW0 address */ + + /* Set the host ownership of sdcard cd during kernel boot */ + Method (_INI, 0) + { + /* Check SDCard CD port is valid */ + If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + { + /* Store DW0 address of SD_CD */ + Store (GDW0 (\SCDP, \SCDO), SCD0) + /* Get the current SD_CD ownership */ + Store (_SB.GHO (\SCDP, \SCDO), Local0) + /* Set host ownership as GPIO in HOSTSW_OWN reg */ + Or (Local0, ShiftLeft (1, Mod (\SCDO, 32)), Local0) + _SB.SHO (\SCDP, \SCDO, Local0) + } + } + + Method (_PS0, 0, NotSerialized) + { + /* Check SDCard CD port is valid */ + If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + { + /* Store DW0 into local0 to get rxstate of GPIO */ + Store (_SB.GPC0 (SCD0), Local0) + /* Extract rxstate [bit 1] of sdcard card detect pin */ + And (Local0, PAD_CFG0_RX_STATE, Local0) + /* If the sdcard is present, rxstate is low. + * If sdcard is not present, rxstate is High. + * Write the inverted value of rxstate to GRR3. + */ + If (LEqual (Local0, 0)) { + Store (1, ^^GRR3) + } Else { + Store (0, ^^GRR3) + } + Sleep (2) + } + } + + Method (_PS3, 0, NotSerialized) + { + /* Clear GRR3 to Power Gate SD Controller */ + Store (0, ^^GRR3) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } + } /* Device (SDCD) */ +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl new file mode 100644 index 0000000000..df2fafb7f6 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + */ + +#ifndef _SOC_INT_DEFINE_ASL_ +#define _SOC_INT_DEFINE_ASL_ + +#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/ +#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/ +#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/ +#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ +#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ +#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define GPIO_BANK_INT 14 +#define NPK_INT 16 +#define PIRQA_INT 16 +#define PIRQB_INT 17 +#define PIRQC_INT 18 +#define SATA_INT 19 +#define GEN_INT 19 +#define PIRQD_INT 19 +#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/ +#define SMBUS_INT 20 /* PIRQE */ +#define CSE_INT 20 /* PIRQE */ +#define IUNIT_INT 21 /* PIRQF */ +#define PIRQF_INT 21 +#define PIRQG_INT 22 +#define PUNIT_INT 24 +#define AUDIO_INT 25 +#define ISH_INT 26 +#define I2C0_INT 27 +#define I2C1_INT 28 +#define I2C2_INT 29 +#define I2C3_INT 30 +#define I2C4_INT 31 +#define I2C5_INT 32 +#define I2C6_INT 33 +#define I2C7_INT 34 +#define SPI0_INT 35 +#define SPI1_INT 36 +#define SPI2_INT 37 +#define UFS_INT 38 +#define EMMC_INT 39 +#define PMC_INT 40 +#define SDIO_INT 42 +#define CNVI_INT 44 + +#endif /* _SOC_INT_DEFINE_ASL_ */ diff --git a/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl new file mode 100644 index 0000000000..08290194f6 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + */ + +#include <p2sb.h> +#include <asm/arch/gpe.h> + +/* PCIE device */ +#include "pcie.asl" + +/* LPSS device */ +#include "lpss.asl" + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* GPIO controller */ +#include "gpio.asl" + +#include "xhci.asl" + +/* LPC */ +#include <asm/acpi/lpc.asl> + +/* eMMC */ +#include "scs.asl" + +/* PMC IPC controller */ +#include "pmc_ipc.asl" + +/* PCI _OSC */ +#include <asm/acpi/pci_osc.asl> diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl new file mode 100644 index 0000000000..6333126c3f --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +/* XHCI Controller 0:15.0 */ +Device (XHCI) { + Name (_ADR, 0x00150000) /* Device 21, Function 0 */ + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + /* Declare XHCI GPE status and enable bits are bit 13 */ + Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) + + Method (_STA, 0) + { + Return (0xF) + } + + Device (RHUB) + { + /* Root Hub */ + Name (_ADR, Zero) + +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#include "xhci_glk_ports.asl" +#else +#include "xhci_apl_ports.asl" +#endif + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl new file mode 100644 index 0000000000..3ab7d18fc8 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC. + * Copyright 2019 Intel Corp. + */ + +/* USB2 */ +Device (HS01) { Name (_ADR, 1) } +Device (HS02) { Name (_ADR, 2) } +Device (HS03) { Name (_ADR, 3) } +Device (HS04) { Name (_ADR, 4) } +Device (HS05) { Name (_ADR, 5) } +Device (HS06) { Name (_ADR, 6) } +Device (HS07) { Name (_ADR, 7) } +Device (HS08) { Name (_ADR, 8) } + +/* USB3 */ +Device (SS01) { Name (_ADR, 9) } +Device (SS02) { Name (_ADR, 10) } +Device (SS03) { Name (_ADR, 11) } +Device (SS04) { Name (_ADR, 12) } +Device (SS05) { Name (_ADR, 13) } +Device (SS06) { Name (_ADR, 14) } diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl new file mode 100644 index 0000000000..192267221f --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC. + * Copyright 2019 Intel Corp. + */ + +/* USB2 */ +Device (HS01) { Name (_ADR, 1) } +Device (HS02) { Name (_ADR, 2) } +Device (HS03) { Name (_ADR, 3) } +Device (HS04) { Name (_ADR, 4) } +Device (HS05) { Name (_ADR, 5) } +Device (HS06) { Name (_ADR, 6) } +Device (HS07) { Name (_ADR, 7) } +Device (HS08) { Name (_ADR, 8) } +Device (HS09) { Name (_ADR, 9) } + +/* USB3 */ +Device (SS01) { Name (_ADR, 10) } +Device (SS02) { Name (_ADR, 11) } +Device (SS03) { Name (_ADR, 12) } +Device (SS04) { Name (_ADR, 13) } +Device (SS05) { Name (_ADR, 14) } +Device (SS06) { Name (_ADR, 15) }

This value is incorrect and causes problems booting Linux. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

board/google/chromebook_coral/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig index 940bee89b0..f744b4c00c 100644 --- a/board/google/chromebook_coral/Kconfig +++ b/board/google/chromebook_coral/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_16384

config PCIE_ECAM_BASE - default 0xf0000000 + default 0xe0000000

config EARLY_POST_CROS_EC bool "Enable early post to Chrome OS EC"

At present U-Boot puts a magic number in the ASL for the GNVS table and searches for later.

Add a Kconfig option to use a different approach, where the ASL files declare the table as an external symbol. U-Boot can then put it wherever it likes, without any magic numbers or searching.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/Kconfig | 7 ++++ arch/x86/cpu/apollolake/Kconfig | 1 + arch/x86/include/asm/acpi/global_nvs.h | 3 ++ arch/x86/lib/acpi_table.c | 47 ++++++++++++++------------ 4 files changed, 36 insertions(+), 22 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c4a9a9f624..af44da1091 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -755,6 +755,13 @@ config GENERATE_ACPI_TABLE by the operating system. It defines platform-independent interfaces for configuration and power management monitoring.

+config ACPI_GNVS_EXTERNAL + bool + help + Put the GNVS (Global Non-Volatile Sleeping) table separate from the + DSDT and add a pointer to the table from the DSDT. This allows + U-Boot to better control the address of the GNVS. + endmenu

config HAVE_ACPI_RESUME diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 2ae6837f75..c66863c52e 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -15,6 +15,7 @@ config INTEL_APOLLOLAKE select TPL_PCH_SUPPORT select PCH_SUPPORT select P2SB + select ACPI_GNVS_EXTERNAL imply ENABLE_MRC_CACHE imply AHCI_PCI imply SCSI diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h index d56d35ca53..a552cf6374 100644 --- a/arch/x86/include/asm/acpi/global_nvs.h +++ b/arch/x86/include/asm/acpi/global_nvs.h @@ -11,6 +11,9 @@ * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file * to declare the GNVS OperationRegion, as well as write_acpi_tables() * for the GNVS address runtime fix up. + * + * If using CONFIG_ACPI_GNVS_EXTERNAL, we don't need to locate the GNVS in + * DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused. */ #define ACPI_GNVS_ADDR 0xdeadbeef #define ACPI_GNVS_SIZE 0x100 diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 68e0779357..4c35111c48 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -437,31 +437,34 @@ ulong write_acpi_tables(ulong start_addr) } acpi_align(ctx);

- /* Pack GNVS into the ACPI table area */ - for (i = 0; i < dsdt->length; i++) { - u32 *gnvs = (u32 *)((u32)dsdt + i); - if (*gnvs == ACPI_GNVS_ADDR) { - ulong addr = (ulong)map_to_sysmem(ctx->current); - - debug("Fix up global NVS in DSDT to %#08lx\n", addr); - *gnvs = addr; - break; + if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) { + /* Pack GNVS into the ACPI table area */ + for (i = 0; i < dsdt->length; i++) { + u32 *gnvs = (u32 *)((u32)dsdt + i); + + if (*gnvs == ACPI_GNVS_ADDR) { + *gnvs = map_to_sysmem(ctx->current); + debug("Fix up global NVS in DSDT to %#08x\n", + *gnvs); + break; + } } - } - - /* Update DSDT checksum since we patched the GNVS address */ - dsdt->checksum = 0; - dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);

- /* - * Fill in platform-specific global NVS variables. If this fails we - * cannot return the error but this should only happen while debugging. - */ - addr = acpi_create_gnvs(ctx->current); - if (IS_ERR_VALUE(addr)) - printf("Error: Gailed to create GNVS\n"); + /* Update DSDT checksum since we patched the GNVS address */ + dsdt->checksum = 0; + dsdt->checksum = table_compute_checksum(dsdt, dsdt->length);

- acpi_inc_align(ctx, sizeof(struct acpi_global_nvs)); + /* + * Fill in platform-specific global NVS variables. If this fails + * we cannot return the error but this should only happen while + * debugging. + */ + addr = acpi_create_gnvs(ctx->current); + if (IS_ERR_VALUE(addr)) + printf("Error: Gailed to create GNVS\n"); + acpi_create_gnvs(ctx->current); + acpi_inc_align(ctx, sizeof(struct acpi_global_nvs)); + }

debug("ACPI: * FADT\n"); fadt = ctx->current;

Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse.

Add a wake to specify this for USB devices and add the settings for Apollo Lake.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/arch-apollolake/gpe.h | 134 ++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/gpio.h | 3 + doc/device-tree-bindings/device.txt | 4 + 3 files changed, 141 insertions(+) create mode 100644 arch/x86/include/asm/arch-apollolake/gpe.h

diff --git a/arch/x86/include/asm/arch-apollolake/gpe.h b/arch/x86/include/asm/arch-apollolake/gpe.h new file mode 100644 index 0000000000..c0b86085b5 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/gpe.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Intel Corporation. + * + * Taken from coreboot apl gpe.h + */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* bit position in GPE0a_STS register */ +#define GPE0A_PCIE_SCI_STS 0 +#define GPE0A_SWGPE_STS 2 +#define GPE0A_PCIE_WAKE0_STS 3 +#define GPE0A_PUNIT_SCI_STS 4 +#define GPE0A_PCIE_WAKE1_STS 6 +#define GPE0A_PCIE_WAKE2_STS 7 +#define GPE0A_PCIE_WAKE3_STS 8 +#define GPE0A_PCIE_GPE_STS 9 +#define GPE0A_BATLOW_STS 10 +#define GPE0A_CSE_PME_STS 11 +#define GPE0A_XDCI_PME_STS 12 +#define GPE0A_XHCI_PME_STS 13 +#define GPE0A_AVS_PME_STS 14 +#define GPE0A_GPIO_TIER1_SCI_STS 15 +#define GPE0A_SMB_WAK_STS 16 +#define GPE0A_SATA_PME_STS 17 +#define GPE0A_CNVI_PME_STS 18 +#define GPE0A_ESPI_SCI_STS 20 /* Present in GLK */ + +/* Group DW0 is reserved in Apollolake */ + +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_127_96 */ +#define GPE0_DW3_00 96 +#define GPE0_DW3_01 97 +#define GPE0_DW3_02 98 +#define GPE0_DW3_03 99 +#define GPE0_DW3_04 100 +#define GPE0_DW3_05 101 +#define GPE0_DW3_06 102 +#define GPE0_DW3_07 103 +#define GPE0_DW3_08 104 +#define GPE0_DW3_09 105 +#define GPE0_DW3_10 106 +#define GPE0_DW3_11 107 +#define GPE0_DW3_12 108 +#define GPE0_DW3_13 109 +#define GPE0_DW3_14 110 +#define GPE0_DW3_15 111 +#define GPE0_DW3_16 112 +#define GPE0_DW3_17 113 +#define GPE0_DW3_18 114 +#define GPE0_DW3_19 115 +#define GPE0_DW3_20 116 +#define GPE0_DW3_21 117 +#define GPE0_DW3_22 118 +#define GPE0_DW3_23 119 +#define GPE0_DW3_24 120 +#define GPE0_DW3_25 121 +#define GPE0_DW3_26 122 +#define GPE0_DW3_27 123 +#define GPE0_DW3_28 124 +#define GPE0_DW3_29 125 +#define GPE0_DW3_30 126 +#define GPE0_DW3_31 127 + +#define GPE_MAX GPE0_DW3_31 +#endif diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h index 10879c168e..ab5860c0fd 100644 --- a/arch/x86/include/asm/arch-apollolake/gpio.h +++ b/arch/x86/include/asm/arch-apollolake/gpio.h @@ -482,4 +482,7 @@ #define GPIO_72_IRQ 0x65 #define GPIO_73_IRQ 0x66

+/* This is needed by ACPI */ +#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ + #endif /* _ASM_ARCH_GPIO_H_ */ diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt index 107b17589c..77aee20031 100644 --- a/doc/device-tree-bindings/device.txt +++ b/doc/device-tree-bindings/device.txt @@ -23,6 +23,8 @@ U-Boot provides for some optional properties which are documented here. - acpi,name : Provides the ACPI name for a device, which is a string consisting of four alphanumeric character (upper case) - acpi,uid : _UID value for device + - acpi,wake : Provides the GPE used to detect a request from a device to wake + from sleep

Example @@ -36,6 +38,7 @@ synaptics_touchpad: synaptics-touchpad@2c { acpi,desc = "Synaptics Touchpad"; interrupts-extended = <&acpi_gpe GPIO_18_IRQ IRQ_TYPE_EDGE_FALLING>; + acpi,wake = <GPE0_DW1_15>; acpi,probed; acpi,hid-desc-reg-offset = <0x20>; }; @@ -47,6 +50,7 @@ pcie-a0@14,0 { compatible = "intel,generic-wifi"; acpi,desc = "Intel WiFi"; acpi,name = "WF00"; + acpi,wake = <GPE0_DW3_00>; interrupts-extended = <&acpi_gpe 0x3c 0>; }; };

This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/Kconfig | 8 + arch/x86/cpu/apollolake/Kconfig | 1 + arch/x86/cpu/intel_common/Makefile | 2 + arch/x86/cpu/intel_common/intel_opregion.c | 168 ++++++++++++++ arch/x86/include/asm/intel_opregion.h | 247 +++++++++++++++++++++ arch/x86/lib/fsp/fsp_graphics.c | 28 +++ include/bloblist.h | 1 + 7 files changed, 455 insertions(+) create mode 100644 arch/x86/cpu/intel_common/intel_opregion.c create mode 100644 arch/x86/include/asm/intel_opregion.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5e3357ccee..23d2e04140 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -968,4 +968,12 @@ config PCIEX_LENGTH_128MB config PCIEX_LENGTH_64MB bool

+config INTEL_GMA_ACPI + bool "Generate ACPI table for Intel GMA graphics" + help + The Intel GMA graphics driver in Linux expects an ACPI table + which describes the layout of the registers and the display + connected to the device. Enable this option to create this + table so that graphics works correctly. + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 7d7b5c3a0e..6c62da04f0 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -45,6 +45,7 @@ config INTEL_APOLLOLAKE imply CMD_CLK imply CLK_INTEL imply ACPI_GPE + imply INTEL_GMA_ACPI

if INTEL_APOLLOLAKE

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index cc4e1c962b..adaf53c35e 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -9,6 +9,8 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif

+obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o + ifdef CONFIG_INTEL_CAR_CQOS obj-$(CONFIG_TPL_BUILD) += car2.o ifndef CONFIG_SPL_BUILD diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c new file mode 100644 index 0000000000..67c381d56d --- /dev/null +++ b/arch/x86/cpu/intel_common/intel_opregion.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Writing IntelGraphicsMem table for ACPI + * + * Copyright 2019 Google LLC + * Modified from coreboot src/soc/intel/gma/opregion.c + */ + +#include <common.h> +#include <binman.h> +#include <bloblist.h> +#include <dm.h> +#include <spi_flash.h> +#include <asm/intel_opregion.h> + +static char vbt_data[8 << 10]; + +static int locate_vbt(char **vbtp, int *sizep) +{ + struct binman_entry vbt; + struct udevice *dev; + u32 vbtsig = 0; + int size; + int ret; + + ret = binman_entry_find("intel-vbt", &vbt); + if (ret) + return log_msg_ret("find VBT", ret); + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("find flash", ret); + size = vbt.size; + if (size > sizeof(vbt_data)) + return log_msg_ret("vbt", -E2BIG); + ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data); + if (ret) + return log_msg_ret("read", ret); + + memcpy(&vbtsig, vbt_data, sizeof(vbtsig)); + if (vbtsig != VBT_SIGNATURE) { + log_err("Missing/invalid signature in VBT data file!\n"); + return -EINVAL; + } + + log_info("Found a VBT of %u bytes\n", size); + *sizep = size; + *vbtp = vbt_data; + + return 0; +} + +/* Write ASLS PCI register and prepare SWSCI register. */ +static int intel_gma_opregion_register(struct udevice *dev, ulong opregion) +{ + int sci_reg; + + if (!device_active(dev)) + return -ENOENT; + + /* + * Intel BIOS Specification + * Chapter 5.3.7 "Initialise Hardware State" + */ + dm_pci_write_config32(dev, ASLS, opregion); + + /* + * Atom-based platforms use a combined SMI/SCI register, + * whereas non-Atom platforms use a separate SCI register + */ + if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI)) + sci_reg = SWSMISCI; + else + sci_reg = SWSCI; + + /* + * Intel's Windows driver relies on this: + * Intel BIOS Specification + * Chapter 5.4 "ASL Software SCI Handler" + */ + dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL); + + return 0; +} + +int intel_gma_init_igd_opregion(struct udevice *dev, + struct igd_opregion *opregion) +{ + struct optionrom_vbt *vbt = NULL; + char *vbt_buf; + int vbt_size; + int ret; + + ret = locate_vbt(&vbt_buf, &vbt_size); + if (ret) { + log_err("GMA: VBT couldn't be found\n"); + return log_msg_ret("find vbt", ret); + } + vbt = (struct optionrom_vbt *)vbt_buf; + + memset(opregion, '\0', sizeof(struct igd_opregion)); + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(opregion->header.signature)); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, + ARRAY_SIZE(vbt->coreblock_biosbuild)); + /* Extended VBT support */ + if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { + struct optionrom_vbt *ext_vbt; + + ret = bloblist_ensure_size(BLOBLISTT_INTEL_VBT, + vbt->hdr_vbt_size, + (void **)&ext_vbt); + if (ret) { + log_err("GMA: Unable to add Ext VBT to bloblist\n"); + return log_msg_ret("blob", ret); + } + + memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); + opregion->mailbox3.rvda = (uintptr_t)ext_vbt; + opregion->mailbox3.rvds = vbt->hdr_vbt_size; + } else { + /* Raw VBT size which can fit in gvd1 */ + printf("copy to %p\n", opregion->vbt.gvd1); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); + } + + /* 8kb */ + opregion->header.size = sizeof(struct igd_opregion) / 1024; + + /* + * Left-shift version field to accommodate Intel Windows driver quirk + * when not using a VBIOS. + * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver. + * + * No adverse effects when using VBIOS or booting Linux. + */ + opregion->header.version = IGD_OPREGION_VERSION << 24; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialise Mailbox 1 */ + opregion->mailbox1.clid = 1; + + /* TODO Initialise Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + /* Write ASLS PCI register and prepare SWSCI register. */ + ret = intel_gma_opregion_register(dev, (ulong)opregion); + if (ret) + return log_msg_ret("write asls", ret); + + return 0; +} diff --git a/arch/x86/include/asm/intel_opregion.h b/arch/x86/include/asm/intel_opregion.h new file mode 100644 index 0000000000..fb3e38617e --- /dev/null +++ b/arch/x86/include/asm/intel_opregion.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Writing IntelGraphicsMem table for ACPI + * + * Copyright 2019 Google LLC + * Modified from coreboot src/soc/intel/gma/opregion.h + */ + +#ifndef _ASM_INTEL_OPREGION_H_ +#define _ASM_INTEL_OPREGION_H_ + +#define VBT_SIGNATURE 0x54425624 + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define SWSMISCI 0xe0 /* SWSMISCI Register */ +#define GSSCIE BIT(0) /* SCI Event trigger */ +#define SMISCISEL BIT(15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +struct __packed opregion_header { + u8 signature[16]; /* Offset 0 OpRegion signature */ + u32 size; /* Offset 16 OpRegion size */ + u32 version; /* Offset 20 OpRegion structure version */ + u8 sbios_version[32]; /* Offset 24 System BIOS build version */ + u8 vbios_version[16]; /* Offset 56 Video BIOS build version */ + u8 driver_version[16]; /* Offset 72 Graphic drvr build version */ + u32 mailboxes; /* Offset 88 Mailboxes supported */ + u32 dmod; /* Offset 92 Driver Model */ + u32 pcon; /* Offset 96 Platform Capabilities */ + u16 dver[16]; /* Offset 100 GOP Version */ + u8 reserved[124]; /* Offset 132 Reserved */ +}; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 BIT(0) +#define IGD_MBOX2 BIT(1) +#define IGD_MBOX3 BIT(2) +#define IGD_MBOX4 BIT(3) +#define IGD_MBOX5 BIT(4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public ACPI methods */ +struct __packed opregion_mailbox1 { + u32 drdy; /* Offset 0 Driver readiness */ + u32 csts; /* Offset 4 Status */ + u32 cevt; /* Offset 8 Current event */ + u8 reserved[20]; /* Offset 12 Reserved */ + u32 didl; /* Offset 32 Supported display device 1 */ + u32 ddl2; /* Offset 36 Supported display device 2 */ + u32 ddl3; /* Offset 40 Supported display device 3 */ + u32 ddl4; /* Offset 44 Supported display device 4 */ + u32 ddl5; /* Offset 48 Supported display device 5 */ + u32 ddl6; /* Offset 52 Supported display device 6 */ + u32 ddl7; /* Offset 56 Supported display device 7 */ + u32 ddl8; /* Offset 60 Supported display device 8 */ + u32 cpdl; /* Offset 64 Currently present display device 1 */ + u32 cpl2; /* Offset 68 Currently present display device 2 */ + u32 cpl3; /* Offset 72 Currently present display device 3 */ + u32 cpl4; /* Offset 76 Currently present display device 4 */ + u32 cpl5; /* Offset 80 Currently present display device 5 */ + u32 cpl6; /* Offset 84 Currently present display device 6 */ + u32 cpl7; /* Offset 88 Currently present display device 7 */ + u32 cpl8; /* Offset 92 Currently present display device 8 */ + u32 cadl; /* Offset 96 Currently active display device 1 */ + u32 cal2; /* Offset 100 Currently active display device 2 */ + u32 cal3; /* Offset 104 Currently active display device 3 */ + u32 cal4; /* Offset 108 Currently active display device 4 */ + u32 cal5; /* Offset 112 Currently active display device 5 */ + u32 cal6; /* Offset 116 Currently active display device 6 */ + u32 cal7; /* Offset 120 Currently active display device 7 */ + u32 cal8; /* Offset 124 Currently active display device 8 */ + u32 nadl; /* Offset 128 Next active device 1 */ + u32 ndl2; /* Offset 132 Next active device 2 */ + u32 ndl3; /* Offset 136 Next active device 3 */ + u32 ndl4; /* Offset 140 Next active device 4 */ + u32 ndl5; /* Offset 144 Next active device 5 */ + u32 ndl6; /* Offset 148 Next active device 6 */ + u32 ndl7; /* Offset 152 Next active device 7 */ + u32 ndl8; /* Offset 156 Next active device 8 */ + u32 aslp; /* Offset 160 ASL sleep timeout */ + u32 tidx; /* Offset 164 Toggle table index */ + u32 chpd; /* Offset 168 Current hot plug enable indicator */ + u32 clid; /* Offset 172 Current lid state indicator */ + u32 cdck; /* Offset 176 Current docking state indicator */ + u32 sxsw; /* Offset 180 Display Switch notification on Sx State + * resume + */ + u32 evts; /* Offset 184 Events supported by ASL */ + u32 cnot; /* Offset 188 Current OS Notification */ + u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */ + u32 ddl9; /* Offset 196 Extended Supported display device 1 */ + u32 dd10; /* Offset 200 Extended Supported display device 2 */ + u32 dd11; /* Offset 204 Extended Supported display device 3 */ + u32 dd12; /* Offset 208 Extended Supported display device 4 */ + u32 dd13; /* Offset 212 Extended Supported display device 5 */ + u32 dd14; /* Offset 216 Extended Supported display device 6 */ + u32 dd15; /* Offset 220 Extended Supported display device 7 */ + u32 cpl9; /* Offset 224 Extended Currently present device 1 */ + u32 cp10; /* Offset 228 Extended Currently present device 2 */ + u32 cp11; /* Offset 232 Extended Currently present device 3 */ + u32 cp12; /* Offset 236 Extended Currently present device 4 */ + u32 cp13; /* Offset 240 Extended Currently present device 5 */ + u32 cp14; /* Offset 244 Extended Currently present device 6 */ + u32 cp15; /* Offset 248 Extended Currently present device 7 */ + u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */ +}; + +/* mailbox 2: software sci interface */ +struct __packed opregion_mailbox2 { + u32 scic; /* Offset 0 Software SCI function number parameters */ + u32 parm; /* Offset 4 Software SCI function number parameters */ + u32 dslp; /* Offset 8 Driver sleep timeout */ + u8 reserved[244]; /* Offset 12 Reserved */ +}; + +/* mailbox 3: power conservation */ +struct __packed opregion_mailbox3 { + u32 ardy; /* Offset 0 Driver readiness */ + u32 aslc; /* Offset 4 ASLE interrupt command / status */ + u32 tche; /* Offset 8 Technology enabled indicator */ + u32 alsi; /* Offset 12 Current ALS illuminance reading */ + u32 bclp; /* Offset 16 Backlight britness to set */ + u32 pfit; /* Offset 20 Panel fitting Request */ + u32 cblv; /* Offset 24 Brightness Current State */ + /* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */ + u16 bclm[20]; + u32 cpfm; /* Offset 68 Panel Fitting Current Mode */ + u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */ + u8 plut[74]; /* Offset 76 Panel Look Up Table */ + /* Offset 150 PWM Frequency and Minimum Brightness */ + u32 pfmb; + u32 ccdv; /* Offset 154 Color Correction Default Values */ + u32 pcft; /* Offset 158 Power Conservation Features */ + u32 srot; /* Offset 162 Supported Rotation angle */ + u32 iuer; /* Offset 166 Intel Ultrabook Event Register */ + u64 fdsp; /* Offset 170 FFS Display Physical address */ + u32 fdss; /* Offset 178 FFS Display Size */ + u32 stat; /* Offset 182 State Indicator */ + /* + * Offset 186 (Igd opregion offset 0x3BAh) + * Physical address of Raw VBT data + */ + u64 rvda; + /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */ + u32 rvds; + u8 reserved[58]; /* Offset 198 Reserved */ +}; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID BIT(31) +#define IGD_WORD_FIELD_VALID BIT(15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +struct __packed opregion_vbt { + u8 gvd1[6 << 10]; +}; + +/* Mailbox 5: BIOS to Driver Notification Extension */ +struct __packed opregion_mailbox5 { + u32 phed; /* Offset 7168 Panel Header */ + u8 bddc[256]; /* Offset 7172 Panel EDID */ + u8 reserved[764]; /* Offset 7428 764 bytes */ +}; + +/* IGD OpRegion */ +struct __packed igd_opregion { + struct opregion_header header; + struct opregion_mailbox1 mailbox1; + struct opregion_mailbox2 mailbox2; + struct opregion_mailbox3 mailbox3; + struct opregion_vbt vbt; + struct opregion_mailbox5 mailbox5; +}; + +/* Intel Video BIOS (Option ROM) */ +struct __packed optionrom_header { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +}; + +#define OPROM_SIGNATURE 0xaa55 + +struct __packed optionrom_pcir { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +}; + +struct __packed optionrom_vbt { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +}; + +/** + * intel_gma_init_igd_opregion() - Initialise IGD OpRegion + * + * This is called from ACPI code and OS drivers + * + * @return 0 if OK, -ve on error + */ +int intel_gma_init_igd_opregion(struct udevice *dev, + struct igd_opregion *opregion); + +#endif /* _ASM_INTEL_OPREGION_H_ */ diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index 98b762209f..3b2f42f166 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -3,12 +3,17 @@ * Copyright (C) 2017, Bin Meng bmeng.cn@gmail.com */

+#define LOG_CATEGORY UCLASS_VIDEO + #include <common.h> +#include <acpi_table.h> #include <dm.h> #include <vbe.h> #include <video.h> #include <asm/fsp/fsp_support.h> +#include <asm/intel_opregion.h> #include <asm/mtrr.h> +#include <dm/acpi.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -114,6 +119,28 @@ err: return ret; }

+static int fsp_video_acpi_write_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct igd_opregion *opregion; + int ret; + + printf("ACPI: * IGD OpRegion\n"); + opregion = (struct igd_opregion *)ctx->current; + + ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion); + if (ret) + return ret; + + acpi_inc_align(ctx, sizeof(struct igd_opregion)); + + return 0; +} + +struct acpi_ops fsp_video_acpi_ops = { + .write_tables = fsp_video_acpi_write_tables, +}; + static const struct udevice_id fsp_video_ids[] = { { .compatible = "fsp-fb" }, { } @@ -124,6 +151,7 @@ U_BOOT_DRIVER(fsp_video) = { .id = UCLASS_VIDEO, .of_match = fsp_video_ids, .probe = fsp_video_probe, + acpi_ops_ptr(&fsp_video_acpi_ops) };

static struct pci_device_id fsp_video_supported[] = { diff --git a/include/bloblist.h b/include/bloblist.h index 609ac421d6..94b05c5a6f 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -27,6 +27,7 @@ enum bloblist_tag_t { BLOBLISTT_SPL_HANDOFF, /* Hand-off info from SPL */ BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */ BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */ + BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */ };

/**

U-Boot does not support SMM (System Management Mode) at present, but needs a few definitions to correctly set up the ACPI table. Add these.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/smm.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 arch/x86/include/asm/smm.h

diff --git a/arch/x86/include/asm/smm.h b/arch/x86/include/asm/smm.h new file mode 100644 index 0000000000..a74e3829b6 --- /dev/null +++ b/arch/x86/include/asm/smm.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SMM definitions (U-Boot does not support SMM itself) + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2019 Google LLC + * + * Modified from coreboot smm.h + */ + +#ifndef CPU_X86_SMM_H +#define CPU_X86_SMM_H + +#define SMM_DEFAULT_BASE 0x30000 +#define SMM_DEFAULT_SIZE 0x10000 + +/* used only by C programs so far */ +#define SMM_BASE 0xa0000 + +#define SMM_ENTRY_OFFSET 0x8000 +#define SMM_SAVE_STATE_BEGIN(x) (SMM_ENTRY_OFFSET + (x)) + +#define APM_CNT 0xb2 +#define APM_CNT_CST_CONTROL 0x85 +#define APM_CNT_PST_CONTROL 0x80 +#define APM_CNT_ACPI_DISABLE 0x1e +#define APM_CNT_ACPI_ENABLE 0xe1 +#define APM_CNT_MBI_UPDATE 0xeb +#define APM_CNT_GNVS_UPDATE 0xea +#define APM_CNT_FINALIZE 0xcb +#define APM_CNT_LEGACY 0xcc +#define APM_CNT_SMMSTORE 0xed +#define APM_CNT_ELOG_GSMI 0xef +#define APM_STS 0xb3 + +#endif /* CPU_X86_SMM_H */

Add the definition of this structure common to Intel devices. It includes some optional Chrome OS pieces which are used when vboot is integrated.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/intel_gnvs.h | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 arch/x86/include/asm/intel_gnvs.h

diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h new file mode 100644 index 0000000000..a4199ce0f3 --- /dev/null +++ b/arch/x86/include/asm/intel_gnvs.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation. + * + * Taken from coreboot intelblocks/nvs.h + * Copyright 2019 Google LLC + */ + +#ifndef _INTEL_GNVS_H_ +#define _INTEL_GNVS_H_ + +struct __packed acpi_global_nvs { + /* Miscellaneous */ + u8 pcnt; /* 0x00 - Processor Count */ + u8 ppcm; /* 0x01 - Max PPC State */ + u8 lids; /* 0x02 - LID State */ + u8 pwrs; /* 0x03 - AC Power State */ + u8 dpte; /* 0x04 - Enable DPTF */ + u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ + u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ + u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ + u64 nhla; /* 0x19 - 0x20 - NHLT Address */ + u32 nhll; /* 0x21 - 0x24 - NHLT Length */ + u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ + u8 scdp; /* 0x29 - SD_CD GPIO portid */ + u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ + u8 uior; /* 0x2b - UART debug controller init on S3 resume */ + u8 ecps; /* 0x2c - SGX Enabled status */ + u64 emna; /* 0x2d - 0x34 EPC base address */ + u64 elng; /* 0x35 - 0x3C EPC Length */ + u8 unused[195]; +#ifdef CONFIG_CHROMEOS + /* ChromeOS specific (0x100 - 0xfff) */ + struct chromeos_acpi chromeos; +#else + u8 unused2[0xf00]; +#endif +}; +#ifdef CONFIG_CHROMEOS +check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +#endif + +#endif /* _INTEL_GNVS_H_ */

Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/arch-apollolake/iomap.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)

diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 4ce1017055..d12268c825 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -11,11 +11,28 @@

/* Put p2sb at 0xd0000000 in TPL */ #define IOMAP_P2SB_BAR 0xd0000000 +#define IOMAP_P2SB_SIZE 0x10000000

#define IOMAP_SPI_BASE 0xfe010000

#define IOMAP_ACPI_BASE 0x400 #define IOMAP_ACPI_SIZE 0x100 +#define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE + +#define PMC_BAR0 0xfe042000 + +#define MCH_BASE_ADDRESS 0xfed10000 +#define MCH_SIZE 0x8000 +#ifdef __ACPI__ +#define HPET_BASE_ADDRESS 0xfed00000 + +#define PMC_BAR0 0xfe042000 + +#define SRAM_BASE_0 0xfe900000 +#define SRAM_SIZE_0 (8 * KiB) +#define SRAM_BASE_2 0xfe902000 +#define SRAM_SIZE_2 (4 * KiB) +#endif

/* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial

Add an implementation of the HPET (High Precision Event Timer) ACPI table.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 54 +++++++++++++++++++++++++++++++++++++++ include/acpi_table.h | 32 ++++++++++++++++------- 2 files changed, 77 insertions(+), 9 deletions(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 4c35111c48..a810b12cfe 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -32,6 +32,26 @@ extern const unsigned char AmlCode[]; /* ACPI RSDP address to be used in boot parameters */ static ulong acpi_rsdp_addr;

+int acpi_write_hpet(struct acpi_ctx *ctx, const struct udevice *dev) +{ + struct acpi_hpet *hpet; + int ret; + + /* + * We explicitly add these tables later on: + */ + log_debug("ACPI: * HPET\n"); + + hpet = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_hpet)); + acpi_create_hpet(hpet); + ret = acpi_add_table(ctx, hpet); + if (ret) + return log_msg_ret("add", ret); + + return 0; +} + static void acpi_create_facs(struct acpi_facs *facs) { memset((void *)facs, 0, sizeof(struct acpi_facs)); @@ -385,6 +405,40 @@ void acpi_create_ssdt(struct acpi_ctx *ctx, struct acpi_table_header *ssdt, ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length); }

+/* http://www.intel.com/hardwaredesign/hpetspec_1.pdf */ +int acpi_create_hpet(struct acpi_hpet *hpet) +{ + struct acpi_table_header *header = &hpet->header; + struct acpi_gen_regaddr *addr = &hpet->addr; + + memset((void *)hpet, 0, sizeof(struct acpi_hpet)); + if (!header) + return -EFAULT; + + /* Fill out header fields. */ + acpi_fill_header(header, "HPET"); + + header->aslc_revision = ASL_REVISION; + header->length = sizeof(struct acpi_hpet); + header->revision = acpi_get_table_revision(ACPITAB_HPET); + + /* Fill out HPET address. */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff; + addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32; + + hpet->id = *(unsigned int *)CONFIG_HPET_ADDRESS; + hpet->number = 0; + hpet->min_tick = 0; /* HPET_MIN_TICKS */ + + header->checksum = table_compute_checksum((void *)hpet, + sizeof(struct acpi_hpet)); + + return 0; +} + /* * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ diff --git a/include/acpi_table.h b/include/acpi_table.h index e3dedc2496..1d78665abe 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -70,6 +70,15 @@ struct __packed acpi_table_header { u32 aslc_revision; /* ASL compiler revision number */ };

+struct acpi_gen_regaddr { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ +}; + /* A maximum number of 32 ACPI tables ought to be enough for now */ #define MAX_ACPI_TABLES 32

@@ -85,6 +94,16 @@ struct acpi_xsdt { u64 entry[MAX_ACPI_TABLES]; };

+/* HPET timers */ +struct __packed acpi_hpet { + struct acpi_table_header header; + u32 id; + struct acpi_gen_regaddr addr; + u8 number; + u16 min_tick; + u8 attributes; +}; + /* FADT Preferred Power Management Profile */ enum acpi_pm_profile { ACPI_PM_UNSPECIFIED = 0, @@ -152,15 +171,6 @@ enum acpi_address_space_size { ACPI_ACCESS_SIZE_QWORD_ACCESS };

-struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ -}; - /* FADT (Fixed ACPI Description Table) */ struct __packed acpi_fadt { struct acpi_table_header header; @@ -617,6 +627,10 @@ int acpi_add_table(struct acpi_ctx *ctx, void *table); */ void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start);

+int acpi_write_hpet(struct acpi_ctx *ctx, const struct udevice *dev); + +int acpi_create_hpet(struct acpi_hpet *hpet); + #endif /* !__ACPI__*/

#include <asm/acpi_table.h>

Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/intel_common/Makefile | 2 + arch/x86/cpu/intel_common/acpi.c | 441 +++++++++++++++++++++++++++++ arch/x86/include/asm/acpi_table.h | 5 + arch/x86/include/asm/cpu_common.h | 1 + arch/x86/include/asm/intel_acpi.h | 25 ++ include/bloblist.h | 5 + 6 files changed, 479 insertions(+) create mode 100644 arch/x86/cpu/intel_common/acpi.c create mode 100644 arch/x86/include/asm/intel_acpi.h

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 084627f21d..7e1be53630 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -2,6 +2,8 @@ # # Copyright (c) 2016 Google, Inc

+obj-y += acpi.o + ifdef CONFIG_HAVE_MRC obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c new file mode 100644 index 0000000000..df8a27dfaa --- /dev/null +++ b/arch/x86/cpu/intel_common/acpi.c @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Generic Intel ACPI table generation + * + * Copyright (C) 2017 Intel Corp. + * Copyright 2019 Google LLC + * + * Modified from coreboot src/soc/intel/common/block/acpi.c + */ + +#include <common.h> +#include <acpigen.h> +#include <bloblist.h> +#include <cpu.h> +#include <dm.h> +#include <asm/acpi_table.h> +#include <asm/cpu.h> +#include <asm/cpu_common.h> +#include <asm/intel_acpi.h> +#include <asm/ioapic.h> +#include <asm/mpspec.h> +#include <asm/smm.h> +#include <asm/turbo.h> +#include <asm/intel_gnvs.h> +#include <asm/arch/iomap.h> +#include <asm/arch/pm.h> +#include <asm/arch/systemagent.h> +#include <dm/acpi.h> +#include <power/acpi_pmc.h> + +__weak u32 acpi_fill_mcfg(u32 current) +{ + /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, + (CONFIG_SA_PCIEX_LENGTH >> 20) + - 1); + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + uint scis; + int ret; + + ret = arch_read_sci_irq_select(); + if (IS_ERR_VALUE(ret)) + return log_msg_ret("sci_irq", ret); + scis = ret; + scis &= SCI_IRQ_SEL; + scis >>= SCI_IRQ_ADJUST; + + /* Determine how SCI is routed. */ + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + log_warning("Invalid SCI route! Defaulting to IRQ9\n"); + sci_irq = 9; + break; + } + + log_debug("SCI is IRQ%d\n", sci_irq); + + return sci_irq; +} + +static unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci = acpi_sci_irq(); + u16 flags = MP_IRQ_TRIGGER_LEVEL; + + if (sci < 0) + return log_msg_ret("sci irq", sci); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + flags |= arch_madt_sci_irq_polarity(sci); + + /* SCI */ + current += + acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + + return current; +} + +u32 acpi_fill_madt(u32 current) +{ + /* Local APICs */ + current += acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + +__weak void soc_fill_fadt(struct acpi_fadt *fadt) +{ +} + +void intel_acpi_fill_fadt(struct acpi_fadt *fadt) +{ + const u16 pmbase = IOMAP_ACPI_BASE; + + /* Use ACPI 3.0 revision. */ + fadt->header.revision = acpi_get_table_revision(ACPITAB_FADT); + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + + fadt->gpe0_blk = pmbase + GPE0_STS; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + + /* GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + + fadt->flush_size = 0x400; /* twice of cache size */ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->day_alrm = 0xd; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = IO_PORT_RESET; + fadt->reset_value = RST_CPU | SYS_RST; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_gpe1_blk.space_id = 1; +} + +int intel_southbridge_write_acpi_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + int ret; + + ret = acpi_write_dbg2_pci_uart(ctx, gd->cur_serial_dev, + ACPI_ACCESS_SIZE_DWORD_ACCESS); + if (ret) + return log_msg_ret("dbg2", ret); + + ret = acpi_write_hpet(ctx, dev); + if (ret) + return log_msg_ret("hpet", ret); + + return 0; +} + +__weak u32 acpi_fill_soc_wake(u32 generic_pm1_en, + const struct chipset_power_state *ps) +{ + return generic_pm1_en; +} + +__weak int acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + return 0; +} + +int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx) +{ + struct acpi_global_nvs *gnvs; + int ret; + + ret = bloblist_ensure_size(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs), + (void **)&gnvs); + if (ret) + return log_msg_ret("bloblist", ret); + memset(gnvs, '\0', sizeof(*gnvs)); + + ret = acpi_create_gnvs(gnvs); + if (ret) + return log_msg_ret("gnvs", ret); + + /* + * TODO(sjg@chromum.org): tell SMI about it + * smm_setup_structures(gnvs, NULL, NULL); + */ + + /* Add it to DSDT */ + acpigen_write_scope(ctx, "\"); + acpigen_write_name_dword(ctx, "NVSA", (uintptr_t)gnvs); + acpigen_pop_len(ctx); + + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return power; +} + +static int get_cores_per_package(void) +{ + struct cpuid_result result; + int cores = 1; + + if (gd->arch.x86_vendor != X86_VENDOR_INTEL) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_c_state_entries(struct acpi_ctx *ctx) +{ + struct acpi_cstate *c_state_map; + size_t entries; + + c_state_map = arch_get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_cst_package(ctx, c_state_map, entries); +} + +void generate_p_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, num_entries; + int ratio, power, clock, clock_max; + bool turbo; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = (ratio_max * cpu_get_bus_clock()) / 1000; + turbo = (turbo_get_state() == TURBO_ENABLED); + + /* Calculate CPU TDP in mW */ + power_max = cpu_get_power_max(); + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_pct(ctx); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_ppc_nvs(ctx); + /* Write PSD indicating configured coordination type */ + acpigen_write_psd_package(ctx, core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name(ctx, "_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + do { + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (((ratio_max - ratio_min) % ratio_step) > 0) + num_entries += 1; + if (turbo) + num_entries += 1; + if (num_entries > PSS_MAX_ENTRIES) + ratio_step += 1; + } while (num_entries > PSS_MAX_ENTRIES); + + /* _PSS package count depends on Turbo */ + acpigen_write_package(ctx, num_entries); + + /* P[T] is Turbo state if enabled */ + if (turbo) { + ratio_turbo = cpu_get_max_turbo_ratio(); + + /* Add entry for Turbo ratio */ + acpigen_write_pss_package(ctx, clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION,/* lat1 */ + PSS_LATENCY_BUSMASTER,/* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + num_entries -= 1; + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_pss_package(ctx, clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION,/* lat1 */ + PSS_LATENCY_BUSMASTER,/* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + num_entries -= 1; + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = (ratio * cpu_get_bus_clock()) / 1000; + + acpigen_write_pss_package(ctx, clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION,/* lat1 */ + PSS_LATENCY_BUSMASTER,/* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(ctx); +} + +__weak struct acpi_tstate *soc_get_tss_table(int *entries) +{ + *entries = 0; + + return NULL; +} + +void generate_t_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package) +{ + struct acpi_tstate *soc_tss_table; + int entries; + + soc_tss_table = soc_get_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_tsd_package(ctx, core, cores_per_package, SW_ALL); + + /* Indicate FixedHW so OS will use MSR */ + acpigen_write_empty_ptc(ctx); + + /* Set NVS controlled T-state limit */ + acpigen_write_tpc(ctx, "\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_tss_package(ctx, entries, soc_tss_table); +} + +__weak void soc_power_states_generation(struct acpi_ctx *ctx, + int core_id, int cores_per_package) +{ +} + +int generate_cpu_entries(struct acpi_ctx *ctx, const struct udevice *dev) +{ + int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; + int plen = 6; + int totalcores; + int cores_per_package; + int numcpus; + int ret; + + ret = cpu_get_count(dev); + if (ret < 0) + return log_msg_ret("count", ret); + totalcores = ret; + cores_per_package = get_cores_per_package(); + numcpus = totalcores / cores_per_package; + log_debug("Found %d CPU(s) with %d core(s) each.\n", numcpus, + cores_per_package); + + for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { + for (core_id = 0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor _PR.CPUx */ + acpigen_write_processor(ctx, + cpu_id * cores_per_package + + core_id, pcontrol_blk, plen); + + /* Generate C-state tables */ + generate_c_state_entries(ctx); + + /* Soc specific power states generation */ + soc_power_states_generation(ctx, core_id, + cores_per_package); + + acpigen_pop_len(ctx); + } + } + /* + * PPKG is usually used for thermal management of the first and only + * package + */ + acpigen_write_processor_package(ctx, "PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(ctx, cores_per_package); + + return 0; +} diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 7b5217893f..1f2076753c 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -46,4 +46,9 @@ ulong write_acpi_tables(ulong start); */ ulong acpi_get_rsdp_addr(void);

+int arch_read_sci_irq_select(void); +int arch_write_sci_irq_select(uint scis); +int arch_madt_sci_irq_polarity(int sci); +struct acpi_cstate *arch_get_cstate_map(size_t *entries); + #endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index c3f699ffd3..c50f4a3e40 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -14,6 +14,7 @@ enum { };

struct cpu_info; +struct acpi_ctx;

/** * cpu_common_init() - Set up common CPU init diff --git a/arch/x86/include/asm/intel_acpi.h b/arch/x86/include/asm/intel_acpi.h new file mode 100644 index 0000000000..627f8b174a --- /dev/null +++ b/arch/x86/include/asm/intel_acpi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com + */ + +#ifndef __ASM_INTEL_ACPI_H__ +#define __ASM_INTEL_ACPI_H__ + +struct acpi_ctx; +struct udevice; + +int generate_cpu_entries(struct acpi_ctx *ctx, const struct udevice *device); +void soc_power_states_generation(struct acpi_ctx *ctx, + int core_id, int cores_per_package); + +void generate_p_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package); +void generate_t_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package); +int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx); + +int intel_southbridge_write_acpi_tables(const struct udevice *dev, + struct acpi_ctx *ctx); + +#endif /* __ASM_INTEL_ACPI_H__ */ diff --git a/include/bloblist.h b/include/bloblist.h index 94b05c5a6f..7c5b93be4c 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -28,6 +28,11 @@ enum bloblist_tag_t { BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */ BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */ BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */ + /* + * Advanced Configuration and Power Interface Global Non-Volatile + * Sleeping table. This forms part of the ACPI tables passed to Linux. + */ + BLOBLISTT_ACPI_GNVS, };

/**

This currently fails as two required items are commented out. Put them back in and add a check that reading the config succeeds.

Both of these items need a little more work to put them in an appropriate driver at some point.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/apollolake/fsp_s.c | 6 ++++-- arch/x86/dts/chromebook_coral.dts | 12 ++++++------ 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index e7e0c30873..d1aad7a094 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -350,8 +350,10 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,

apl = malloc(sizeof(*apl)); if (!apl) - return log_msg_ret("config", -ENOMEM); - get_config(dev, apl); + return log_msg_ret("alloc", -ENOMEM); + ret = get_config(dev, apl); + if (ret) + return log_msg_ret("config", ret);

cfg->ish_enable = 0; cfg->enable_sata = 0; diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 7ba38d7791..3c6f14310f 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -497,13 +497,13 @@ * If the Board has PERST_0 signal, assign the GPIO * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF * - * This are not used yet, so comment them out for now. - * - * prt0-gpio = <GPIO_122>; - * - * GPIO for SD card detect - * sdcard-cd-gpio = <GPIO_177>; + * This should be converted to real GPIOs and ideally stored in the + * device they relate to. */ + prt0-gpio = <GPIO_122>; + + /* GPIO for SD card detect */ + sdcard-cd-gpio = <GPIO_177>;

/* * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,

Allow this header to be included in ASL files by adding a header guard and a few definitions that are needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

include/p2sb.h | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/include/p2sb.h b/include/p2sb.h index 93e1155dca..a25170e3d1 100644 --- a/include/p2sb.h +++ b/include/p2sb.h @@ -10,6 +10,12 @@ /* Port Id lives in bits 23:16 and register offset lives in 15:0 of address */ #define PCR_PORTID_SHIFT 16

+#if !defined(__ACPI__) + +/* These registers contain IOAPIC and HPET devfn */ +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70 + /** * struct p2sb_child_platdata - Information about each child of a p2sb device * @@ -164,4 +170,6 @@ int p2sb_get_port_id(struct udevice *dev); */ void *pcr_reg_address(struct udevice *dev, uint offset);

+#endif /* !__ACPI__ */ + #endif

Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/acpi.c | 437 ++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/acpi.h | 13 + include/acpi_s3.h | 4 + 4 files changed, 455 insertions(+) create mode 100644 arch/x86/cpu/apollolake/acpi.c create mode 100644 arch/x86/include/asm/arch-apollolake/acpi.h

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 1760df54d8..14e254545f 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -15,6 +15,7 @@ obj-y += fsp_m.o endif endif ifndef CONFIG_SPL_BUILD +obj-y += acpi.o obj-y += fsp_s.o endif

diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c new file mode 100644 index 0000000000..dc8b5c6ad7 --- /dev/null +++ b/arch/x86/cpu/apollolake/acpi.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2017-2019 Siemens AG + * (Written by Lance Zhao lijian.zhao@intel.com for Intel Corp.) + * Copyright 2019 Google LLC + * + * Modified from coreboot apollolake/acpi.c + */ + +#define LOG_CATEGORY LOGC_ACPI + +#include <common.h> +#include <acpigen.h> +#include <acpi_s3.h> +#include <cpu.h> +#include <dm.h> +#include <p2sb.h> +#include <pci.h> +#include <asm/acpi_table.h> +#include <asm/cpu_common.h> +#include <asm/intel_acpi.h> +#include <asm/intel_gnvs.h> +#include <asm/intel_pinctrl.h> +#include <asm/intel_pinctrl_defs.h> +#include <asm/intel_regs.h> +#include <asm/io.h> +#include <asm/mpspec.h> +#include <asm/tables.h> +#include <asm/arch/iomap.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pm.h> +#include <asm/arch/soc_config.h> +#include <asm/arch/systemagent.h> +#include <dm/acpi.h> +#include <dm/uclass-internal.h> +#include <power/acpi_pmc.h> + +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + +static struct acpi_cstate cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + }, + }, { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .addrl = 0x415, + }, + }, { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .addrl = 0x419, + }, + }, +}; + +int arch_read_sci_irq_select(void) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev); + if (ret) + return log_msg_ret("pmc", ret); + upriv = dev_get_uclass_priv(dev); + + return readl(upriv->pmc_bar0 + IRQ_REG); +} + +int arch_write_sci_irq_select(uint scis) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev); + if (ret) + return log_msg_ret("pmc", ret); + upriv = dev_get_uclass_priv(dev); + writel(scis, upriv->pmc_bar0 + IRQ_REG); + + return 0; +} + +struct acpi_cstate *arch_get_cstate_map(size_t *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return cstate_map; +} + +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + const struct apl_config *cfg = gd->arch.soc_config; + struct udevice *cpu, *pinctrl; + uint offset; + int ret; + + if (!cfg) + return log_msg_ret("cfg", -EINVAL); + + /* Clear out GNV */ + memset(gnvs, '\0', sizeof(*gnvs)); + + /* TODO(sjg@chromium.org): Add the console log to gnvs->cbmc */ + +#ifdef CONFIG_CHROMEOS + /* Initialise Verified Boot data */ + chromeos_init_acpi(&gnvs->chromeos); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + /* Set unknown wake source */ + gnvs->pm1i = ~0ULL; + + /* CPU core count */ + gnvs->pcnt = 1; + ret = uclass_find_first_device(UCLASS_CPU, &cpu); + if (cpu) { + ret = cpu_get_count(cpu); + if (ret > 0) + gnvs->pcnt = ret; + } + + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = cfg->dptf_enable; + + /* Assign address of PERST_0 if GPIO is defined in devicetree */ + if (cfg->prt0_gpio != GPIO_PRT0_UDEF) { + ret = intel_pinctrl_get_pad(cfg->prt0_gpio, &pinctrl, &offset); + if (ret) + return log_msg_ret("prt0", ret); + gnvs->prt0 = intel_pinctrl_get_config_reg_addr(pinctrl, offset); + } + + /* + * Get sdcard cd GPIO portid if GPIO is defined in devicetree. + * Get offset of sdcard cd pin. + */ + if (cfg->sdcard_cd_gpio) { + ret = intel_pinctrl_get_pad(cfg->sdcard_cd_gpio, &pinctrl, + &offset); + if (ret) + return log_msg_ret("prt0", ret); + gnvs->scdp = p2sb_get_port_id(pinctrl); + gnvs->scdo = intel_pinctrl_get_acpi_pin(pinctrl, offset); + } + + return 0; +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en) +{ + /* + * WAK_STS bit is set when the system is in one of the sleep states + * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting + * this bit, the PMC will transition the system to the ON state and + * can only be set by hardware and can only be cleared by writing a one + * to this bit position. + */ + generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + + return generic_pm1_en; +} + +int arch_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_LOW; +} + +void fill_fadt(struct acpi_fadt *fadt) +{ + const struct apl_config *cfg = gd->arch.soc_config; + + assert(cfg); + fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + + fadt->pm_tmr_len = 4; + fadt->duty_width = 3; + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR; + + if (cfg->lpss_s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; +} + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + const struct apl_config *cfg = gd->arch.soc_config; + struct acpi_table_header *header = &fadt->header; + + assert(cfg); + acpi_fadt_common(fadt, facs, dsdt); + intel_acpi_fill_fadt(fadt); + fill_fadt(fadt); + header->checksum = table_compute_checksum(fadt, header->length); +} + +int apl_acpi_fill_dmar(struct acpi_ctx *ctx) +{ + struct udevice *dev, *sa_dev; + u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK; + u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK; + bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED; + bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED; + void *tmp; + int ret; + + uclass_find_first_device(UCLASS_VIDEO, &dev); + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa_dev); + if (ret) + return log_msg_ret("no sa", ret); + + /* IGD has to be enabled, GFXVTBAR set and enabled */ + if (dev && device_active(dev) && gfxvtbar && gfxvten) { + tmp = ctx->current; + + ret = acpi_create_dmar_drhd(ctx, 0, 0, gfxvtbar); + if (ret) + return log_msg_ret("drhd", ret); + ret = acpi_create_dmar_ds_pci(ctx, PCI_BDF(0, 2, 0)); + if (ret) + return log_msg_ret("ds_pci", ret); + acpi_dmar_drhd_fixup(ctx, tmp); + + /* Add RMRR entry */ + tmp = ctx->current; + ctx->current += acpi_create_dmar_rmrr(ctx->current, 0, + sa_get_gsm_base(sa_dev), + sa_get_tolud_base(sa_dev) - 1); + ctx->current += acpi_create_dmar_ds_pci(ctx->current, + PCI_BDF(0, 2, 0)); + acpi_dmar_rmrr_fixup(ctx, tmp); + } + + /* DEFVTBAR has to be set and enabled */ + if (defvtbar && defvten) { + struct udevice *p2sb_dev; + u16 ibdf, hbdf; + uint ioapic, hpet; + int ret; + + tmp = ctx->current; + /* + * P2SB may already be hidden. There's no clear rule, when. + * It is needed to get bus, device and function for IOAPIC and + * HPET device which is stored in P2SB device. So unhide it to + * get the info and hide it again when done. + * + * TODO(sjg@chromium.org): p2sb_unhide() ? + */ + ret = uclass_first_device_err(UCLASS_P2SB, &p2sb_dev); + if (ret) + return log_msg_ret("p2sb", ret); + + dm_pci_read_config16(p2sb_dev, PCH_P2SB_IBDF, &ibdf); + ioapic = PCI_TO_BDF(ibdf); + dm_pci_read_config16(p2sb_dev, PCH_P2SB_HBDF, &hbdf); + hpet = PCI_TO_BDF(hbdf); + /* TODO(sjg@chromium.org): p2sb_hide() ? */ + + acpi_create_dmar_drhd(ctx, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); + acpi_create_dmar_ds_ioapic(ctx, 2, ioapic); + acpi_create_dmar_ds_msi_hpet(ctx, 0, hpet); + acpi_dmar_drhd_fixup(tmp, ctx->current); + } + + return 0; +} + +void soc_power_states_generation(struct acpi_ctx *ctx, int core_id, + int cores_per_package) +{ + /* Generate P-state tables */ + generate_p_state_entries(ctx, core_id, cores_per_package); + + /* Generate T-state tables */ + generate_t_state_entries(ctx, core_id, cores_per_package); +} + +static void acpigen_soc_get_dw0_in_local5(struct acpi_ctx *ctx, ulong addr) +{ + /* + * Store (_SB.GPC0 (addr), Local5) + * _SB.GPC0 is used to read cfg0 value from dw0. It is defined in + * gpiolib.asl. + */ + acpigen_write_store(ctx); + acpigen_emit_namestring(ctx, "\_SB.GPC0"); + acpigen_write_integer(ctx, addr); + acpigen_emit_byte(ctx, LOCAL5_OP); +} + +static int acpigen_soc_get_gpio_val(struct acpi_ctx *ctx, uint gpio_num, + uint32_t mask) +{ + assert(gpio_num < TOTAL_PADS); + struct udevice *dev; + uintptr_t addr; + uint offset; + int ret; + + ret = intel_pinctrl_get_pad(gpio_num, &dev, &offset); + if (ret) + return log_msg_ret("pad", ret); + addr = intel_pinctrl_get_config_reg_addr(dev, offset); + + acpigen_soc_get_dw0_in_local5(ctx, addr); + + /* If (And (Local5, mask)) */ + acpigen_write_if_and(ctx, LOCAL5_OP, mask); + + /* Store (One, Local0) */ + acpigen_write_store_ops(ctx, ONE_OP, LOCAL0_OP); + + acpigen_pop_len(ctx); /* If */ + + /* Else */ + acpigen_write_else(ctx); + + /* Store (Zero, Local0) */ + acpigen_write_store_ops(ctx, ZERO_OP, LOCAL0_OP); + + acpigen_pop_len(ctx); /* Else */ + + return 0; +} + +static int acpigen_soc_set_gpio_val(struct acpi_ctx *ctx, uint gpio_num, + uint32_t val) +{ + assert(gpio_num < TOTAL_PADS); + struct udevice *dev; + uintptr_t addr; + uint offset; + int ret; + + ret = intel_pinctrl_get_pad(gpio_num, &dev, &offset); + if (ret) + return log_msg_ret("pad", ret); + addr = intel_pinctrl_get_config_reg_addr(dev, offset); + + acpigen_soc_get_dw0_in_local5(ctx, addr); + + if (val) { + /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ + acpigen_write_or(ctx, LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); + } else { + /* Not (PAD_CFG0_TX_STATE, Local6) */ + acpigen_write_not(ctx, PAD_CFG0_TX_STATE, LOCAL6_OP); + + /* And (Local5, Local6, Local5) */ + acpigen_write_and(ctx, LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); + } + + /* + * _SB.SPC0 (addr, Local5) + * _SB.SPC0 is used to write cfg0 value in dw0. It is defined in + * gpiolib.asl. + */ + acpigen_emit_namestring(ctx, "\_SB.SPC0"); + acpigen_write_integer(ctx, addr); + acpigen_emit_byte(ctx, LOCAL5_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(struct acpi_ctx *ctx, uint gpio_num) +{ + int ret; + + ret = acpigen_soc_get_gpio_val(ctx, gpio_num, PAD_CFG0_RX_STATE); + if (ret) + return log_msg_ret("val", ret); + + return 0; +} + +int acpigen_soc_get_tx_gpio(struct acpi_ctx *ctx, uint gpio_num) +{ + int ret; + + ret = acpigen_soc_get_gpio_val(ctx, gpio_num, PAD_CFG0_TX_STATE); + if (ret) + return log_msg_ret("val", ret); + + return 0; +} + +int acpigen_soc_set_tx_gpio(struct acpi_ctx *ctx, uint gpio_num) +{ + int ret; + + ret = acpigen_soc_set_gpio_val(ctx, gpio_num, 1); + if (ret) + return log_msg_ret("val", ret); + + return 0; +} + +int acpigen_soc_clear_tx_gpio(struct acpi_ctx *ctx, uint gpio_num) +{ + int ret; + + ret = acpigen_soc_set_gpio_val(ctx, gpio_num, 0); + if (ret) + return log_msg_ret("val", ret); + + return 0; +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi.h b/arch/x86/include/asm/arch-apollolake/acpi.h new file mode 100644 index 0000000000..b5b9aaa2b9 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_ACPI_H +#define _ASM_ARCH_ACPI_H + +struct acpi_ctx; + +int apl_acpi_fill_dmar(struct acpi_ctx *ctx); + +#endif /* _ASM_ARCH_CPU_H */ diff --git a/include/acpi_s3.h b/include/acpi_s3.h index baa848dcd1..847139baa0 100644 --- a/include/acpi_s3.h +++ b/include/acpi_s3.h @@ -28,6 +28,10 @@ #define SLP_TYP_S4 6 #define SLP_TYP_S5 7

+/* PM1_STS register */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) + /* Memory size reserved for S3 resume */ #define S3_RESERVE_SIZE 0x1000

Add ACPI generation to the APL CPU driver.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/apollolake/cpu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)

diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index 3ae99ccf04..0af1b0c2cb 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -8,6 +8,9 @@ #include <dm.h> #include <asm/cpu_common.h> #include <asm/cpu_x86.h> +#include <asm/intel_acpi.h> +#include <asm/msr.h> +#include <dm/acpi.h>

static int apl_get_info(const struct udevice *dev, struct cpu_info *info) { @@ -19,6 +22,25 @@ static int apl_get_count(const struct udevice *dev) return 4; }

+static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) +{ + struct cpu_platdata *plat = dev_get_parent_platdata(dev); + int ret; + + /* Trigger off the first CPU */ + if (!plat->cpu_id) { + ret = generate_cpu_entries(ctx, dev); + if (ret) + return log_msg_ret("generate", ret); + } + + return 0; +} + +struct acpi_ops apl_cpu_acpi_ops = { + .fill_ssdt = acpi_cpu_fill_ssdt, +}; + static const struct cpu_ops cpu_x86_apl_ops = { .get_desc = cpu_x86_get_desc, .get_info = apl_get_info, @@ -37,5 +59,6 @@ U_BOOT_DRIVER(cpu_x86_apl_drv) = { .of_match = cpu_x86_apl_ids, .bind = cpu_x86_bind, .ops = &cpu_x86_apl_ops, + acpi_ops_ptr(&apl_cpu_acpi_ops) .flags = DM_FLAG_PRE_RELOC, };

We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this code is not needed. Drop it, and fix a code-style nit just above.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/apollolake/pmc.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 9390c54a8e..a2547a580d 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -116,7 +116,8 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) int size; int ret;

- ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base)); + ret = dev_read_u32_array(dev, "early-regs", base, + ARRAY_SIZE(base)); if (ret) return log_msg_ret("Missing/short early-regs", ret); if (spl_phase() == PHASE_TPL) { @@ -131,11 +132,6 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) } upriv->acpi_base = base[4];

- /* Since PCI is not enabled, we must get the BDF manually */ - plat->bdf = pci_get_devfn(dev); - if (plat->bdf < 0) - return log_msg_ret("Cannot get PMC PCI address", plat->bdf); - /* Get the dwX values for pmc gpe settings */ size = dev_read_size(dev, "gpe0-dw"); if (size < 0)

This new method is intended to be called when UEFI shuts down the 'boot services', i.e. any lingering code in the boot loader that might be used by the OS.

Add a definition for this new method and update the comments a little.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/fsp/fsp_api.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h index e9ac86b2da..c39581c4e5 100644 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -8,9 +8,18 @@

enum fsp_phase { /* Notification code for post PCI enuermation */ - INIT_PHASE_PCI = 0x20, - /* Notification code before transferring control to the payload */ - INIT_PHASE_BOOT = 0x40 + INIT_PHASE_PCI = 0x20, + /* + * Notification code before transferring control to the payload. + * This is issued at the end of init before starting main(), i.e. + * the command line / boot script. + */ + INIT_PHASE_BOOT = 0x40, + /* + * Notification code before existing boot services. This is issued + * just before removing devices and booting the kernel. + */ + INIT_PHASE_END_FIRMWARE = 0xf0, };

struct fsp_notify_params {

At present the MTRR registers are programmed with the list the U-Boot builds up in the same order. In some cases this list may be out of order. It looks better in Linux to have the registers in order, so sort them,

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/mtrr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index a43cb7fc15..5a4eb648fb 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -18,6 +18,7 @@

#include <common.h> #include <cpu_func.h> +#include <sort.h> #include <asm/io.h> #include <asm/msr.h> #include <asm/mtrr.h> @@ -61,6 +62,16 @@ static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size) wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID); }

+static int h_comp_mtrr(const void *p1, const void *p2) +{ + const struct mtrr_request *req1 = p1; + const struct mtrr_request *req2 = p2; + + s64 diff = req1->start - req2->start; + + return diff < 0 ? -1 : diff > 0 ? 1 : 0; +} + int mtrr_commit(bool do_caches) { struct mtrr_request *req = gd->arch.mtrr_req; @@ -75,6 +86,7 @@ int mtrr_commit(bool do_caches) debug("open\n"); mtrr_open(&state, do_caches); debug("open done\n"); + qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr); for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) set_var_mtrr(i, req->type, req->start, req->size);

Send this notification when U-Boot is about to boot into Linux, as requested by the FSP.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/cpu/cpu.c | 15 +++++++++++++++ arch/x86/lib/fsp/fsp_common.c | 16 ++++++++++++++++ 2 files changed, 31 insertions(+)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index a2df92cec9..15c76ff3cb 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -182,6 +182,14 @@ __weak void board_final_init(void) { }

+/* + * Implement a weak default function for boards that need to do some final + * processing before booting the OS. + */ +__weak void board_final_cleanup(void) +{ +} + int last_stage_init(void) { struct acpi_fadt __maybe_unused *fadt; @@ -210,6 +218,13 @@ int last_stage_init(void) } #endif

+ /* + * TODO(sjg@chromium.org): Move this to bootm_announce_and_cleanup() + * once APL FSP-S at 0x200000 does not overlap with the bzimage at + * 0x100000. + */ + board_final_cleanup(); + return 0; } #endif diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 8a6108fb32..2eeb697ad7 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -58,6 +58,22 @@ void board_final_init(void) debug("OK\n"); }

+void board_final_cleanup(void) +{ + u32 status; + + /* TODO(sjg@chromium.org): This causes Linux to crash */ + return; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): "); + status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); +} + #ifdef CONFIG_HAVE_ACPI_RESUME int fsp_save_s3_stack(void) {

This is currently in the wrong place so including the file in the device tree fails. Fix it.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/include/asm/e820.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 9d29f82f97..87af0f492e 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -21,10 +21,9 @@ struct e820_entry { #define ISA_START_ADDRESS 0xa0000 #define ISA_END_ADDRESS 0x100000

-#endif /* __ASSEMBLY__ */ - /* Implementation defined function to install an e820 map */ unsigned int install_e820_map(unsigned int max_entries, struct e820_entry *); +#endif /* __ASSEMBLY__ */

#endif /* _ASM_X86_E820_H */

At present if hyperthreading is disabled the CPU numbering is not sequential. Fix this.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 886960a5fa..e757dc419a 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -128,14 +128,17 @@ int acpi_create_madt_lapics(u32 current) { struct udevice *dev; int total_length = 0; + int cpu_num = 0;

for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { struct cpu_platdata *plat = dev_get_parent_platdata(dev); - int length = acpi_create_madt_lapic( - (struct acpi_madt_lapic *)current, - plat->cpu_id, plat->cpu_id); + int length; + + length = acpi_create_madt_lapic( + (struct acpi_madt_lapic *)current, cpu_num++, + plat->cpu_id); current += length; total_length += length; }

This provides information about a v1 TPM in the system. Generate this table if the TPM is present.

Add a required new bloblist type and correct the header order of one header file.

Signed-off-by: Simon Glass sjg@chromium.org ---

arch/x86/lib/acpi_table.c | 52 ++++++++++++++++++++++++++++++++++++++- include/acpi_table.h | 7 ++++++ include/bloblist.h | 1 + 3 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 1d12e58508..564c5167c9 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -277,6 +277,45 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) header->checksum = table_compute_checksum((void *)mcfg, header->length); }

+/** + * acpi_create_tcpa() - Create a TCPA table + * + * @tcpa: Pointer to place to put table + * + * Trusted Computing Platform Alliance Capabilities Table + * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI + * Firmware Specification 3.0 + */ +static int acpi_create_tcpa(struct acpi_tcpa *tcpa) +{ + struct acpi_table_header *header = &tcpa->header; + u32 current = (u32)tcpa + sizeof(struct acpi_tcpa); + int size = 0x10000; /* Use this as the default size */ + void *log; + int ret; + + memset(tcpa, '\0', sizeof(struct acpi_tcpa)); + + /* Fill out header fields */ + acpi_fill_header(header, "TCPA"); + header->length = sizeof(struct acpi_tcpa); + header->revision = 1; + + ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log); + if (ret) + return log_msg_ret("blob", ret); + + tcpa->platform_class = 0; + tcpa->laml = size; + tcpa->lasa = (ulong)log; + + /* (Re)calculate length and checksum */ + header->length = current - (u32)tcpa; + header->checksum = table_compute_checksum((void *)tcpa, header->length); + + return 0; +} + static int get_tpm2_log(void **ptrp, int *sizep) { const int tpm2_default_log_len = 0x10000; @@ -737,11 +776,13 @@ ulong write_acpi_tables(ulong start_addr) struct acpi_fadt *fadt; struct acpi_table_header *ssdt; struct acpi_mcfg *mcfg; + struct acpi_tcpa *tcpa; struct acpi_madt *madt; struct acpi_csrt *csrt; struct acpi_spcr *spcr; void *start; ulong addr; + int ret; int i;

start = map_sysmem(start_addr, 0); @@ -829,7 +870,6 @@ ulong write_acpi_tables(ulong start_addr)

if (IS_ENABLED(CONFIG_TPM_V2)) { struct acpi_tpm2 *tpm2; - int ret;

debug("ACPI: * TPM2\n"); tpm2 = (struct acpi_tpm2 *)ctx->current; @@ -848,6 +888,16 @@ ulong write_acpi_tables(ulong start_addr) acpi_inc_align(ctx, madt->header.length); acpi_add_table(ctx, madt);

+ debug("ACPI: * TCPA\n"); + tcpa = (struct acpi_tcpa *)ctx->current; + ret = acpi_create_tcpa(tcpa); + if (ret) { + log_warning("Failed to create TCPA table (err=%d)\n", ret); + } else { + acpi_inc_align(ctx, tcpa->header.length); + acpi_add_table(ctx, tcpa); + } + debug("ACPI: * CSRT\n"); csrt = ctx->current; acpi_create_csrt(csrt); diff --git a/include/acpi_table.h b/include/acpi_table.h index 3d51942d32..b5ba37cd28 100644 --- a/include/acpi_table.h +++ b/include/acpi_table.h @@ -115,6 +115,13 @@ struct __packed acpi_tpm2 { u64 lasa; };

+struct __packed acpi_tcpa { + struct acpi_table_header header; + u16 platform_class; + u32 laml; + u64 lasa; +}; + /* FADT Preferred Power Management Profile */ enum acpi_pm_profile { ACPI_PM_UNSPECIFIED = 0, diff --git a/include/bloblist.h b/include/bloblist.h index d8dccf91fc..d7661bc111 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -34,6 +34,7 @@ enum bloblist_tag_t { */ BLOBLISTT_ACPI_GNVS, BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */ + BLOBLISTT_TCPA_LOG, /* TPM log space */ };

/**