On 4 November 2015 at 01:16, Mugunthan V N mugunthanvnm@ti.com wrote:

To enable memory map in dra7xx, specific chip select must be written to control module register. But this hard coded to chip select 1, fixing it by writing the specific chip select value to control module register.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/spi/ti_qspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass sjg@chromium.org

But maybe it would be better to just drop the MEM_CS macro.

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index ecd9d78..36bf206 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -41,7 +41,7 @@ #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY) #define QSPI_XFER_DONE QSPI_WC #define MM_SWITCH 0x01 -#define MEM_CS 0x100 +#define MEM_CS(cs) ((cs + 1) << 8) #define MEM_CS_UNSELECT 0xfffff0ff #define MMAP_START_ADDR_DRA 0x5c000000 #define MMAP_START_ADDR_AM43x 0x30000000 @@ -265,7 +265,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, writel(MM_SWITCH, &qslave->base->memswitch); #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) val = readl(CORE_CTRL_IO);

•           val |= MEM_CS;
  

•           val |= MEM_CS(slave->cs);
            writel(val, CORE_CTRL_IO);
  

#endif return 0; -- 2.6.2.280.g74301d6

Regards, Simon

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N mugunthanvnm@ti.com wrote:

Prepare driver for DM conversion.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/spi/ti_qspi.c | 287 ++++++++++++++++++++++++++++---------------------- 1 file changed, 161 insertions(+), 126 deletions(-)

This looks OK except for the lack of a change log and one thing below.

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 44c5762..003df80 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -28,6 +28,7 @@ #define QSPI_3_PIN BIT(18) #define QSPI_RD_SNGL BIT(16) #define QSPI_WR_SNGL (2 << 16) +#define QSPI_RD_DUAL (7 << 16) #define QSPI_INVAL (4 << 16) #define QSPI_RD_QUAD (7 << 16) /* device control */ @@ -89,46 +90,16 @@ struct ti_qspi_regs { struct ti_qspi_priv { struct spi_slave slave;

This should not be present when driver model is used. Can you put an #ifdef around it and store anything else you need directly in the structure, rather than using struct spi_slave?

    struct ti_qspi_regs *base;

•   void *ctrl_mod_mmap;
    unsigned int mode;
    u32 cmd;
    u32 dc;
  

•   u32 num_cs;
  

•   u32 rx_bus_width;
  

};

On 4 November 2015 at 13:46, Mugunthan V N mugunthanvnm@ti.com wrote:

Prepare driver for DM conversion.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/spi/ti_qspi.c | 287 ++++++++++++++++++++++++++++---------------------- 1 file changed, 161 insertions(+), 126 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 44c5762..003df80 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -28,6 +28,7 @@ #define QSPI_3_PIN BIT(18) #define QSPI_RD_SNGL BIT(16) #define QSPI_WR_SNGL (2 << 16) +#define QSPI_RD_DUAL (7 << 16) #define QSPI_INVAL (4 << 16) #define QSPI_RD_QUAD (7 << 16) /* device control */ @@ -89,46 +90,16 @@ struct ti_qspi_regs { struct ti_qspi_priv { struct spi_slave slave; struct ti_qspi_regs *base;

•   void *ctrl_mod_mmap;
  

Looks like this patch manages to prepare for non-dm addition by using dm functions is it? and other than that some new things got added like RD_DUAL or ctrl_mod_mmap, please add them separately add do the dm conversion only on existing code.

    unsigned int mode;
    u32 cmd;
    u32 dc;

•   u32 num_cs;
  

•   u32 rx_bus_width;
  

};

-static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) -{

•   return container_of(slave, struct ti_qspi_priv, slave);
  

-}

-static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) -{

•   struct spi_slave *slave = &priv->slave;
  

•   u32 memval = 0;
  

-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)

•   slave->memory_map = (void *)MMAP_START_ADDR_DRA;
  

-#else

•   slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
  

-#endif

-#ifdef CONFIG_QSPI_QUAD_SUPPORT

•   memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
  

•                   QSPI_SETUP0_NUM_D_BYTES_8_BITS |
  

•                   QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
  

•                   QSPI_NUM_DUMMY_BITS);
  

•   slave->op_mode_rx = SPI_OPM_RX_QOF;
  

-#else

•   memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
  

•                   QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
  

•                   QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
  

•                   QSPI_NUM_DUMMY_BITS;
  

-#endif

•   writel(memval, &priv->base->setup0);
  

-}

-static void ti_spi_set_speed(struct spi_slave *slave, uint hz) +static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) {

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
    uint clk_div;
  
    debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
  

@@ -152,130 +123,80 @@ static void ti_spi_set_speed(struct spi_slave *slave, uint hz) writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); }

-int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{

•   return 1;
  

-}

-void spi_cs_activate(struct spi_slave *slave) +static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) {

•   /* CS handled in xfer */
  

•   return;
  

-}

-void spi_cs_deactivate(struct spi_slave *slave) -{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
  

•   writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
  

}

-void spi_init(void) +static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) {

•   /* nothing to do */
  

-}

-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,

•                             unsigned int max_hz, unsigned int mode)
  

-{

•   struct ti_qspi_priv *priv;
  

-#ifdef CONFIG_AM43XX

•   gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
  

•   gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
  

-#endif

•   priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
  

•   if (!priv) {
  

•           printf("SPI_error: Fail to allocate ti_qspi_priv\n");
  

•           return NULL;
  

•   }
  

•   priv->base = (struct ti_qspi_regs *)QSPI_BASE;
  

•   priv->mode = mode;
  

•   ti_spi_set_speed(&priv->slave, max_hz);
  

-#ifdef CONFIG_TI_SPI_MMAP

•   ti_spi_setup_spi_register(priv);
  

-#endif

•   return &priv->slave;
  

-}

-void spi_free_slave(struct spi_slave *slave) -{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   free(priv);
  

•   priv->dc = 0;
  

•   if (mode & SPI_CPHA)
  

•           priv->dc |= QSPI_CKPHA(0);
  

•   if (mode & SPI_CPOL)
  

•           priv->dc |= QSPI_CKPOL(0);
  

•   if (mode & SPI_CS_HIGH)
  

•           priv->dc |= QSPI_CSPOL(0);
  

•   if (mode & SPI_RX_QUAD)
  

•           priv->rx_bus_width = QSPI_RD_QUAD;
  

•   else if (mode & SPI_RX_QUAD)
  

•           priv->rx_bus_width = QSPI_RD_DUAL;
  

•   else
  

•           priv->rx_bus_width = QSPI_RD_SNGL;
  

•   return 0;
  

}

-int spi_claim_bus(struct spi_slave *slave) +static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs) {

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
  

•   priv->dc = 0;
  

•   if (priv->mode & SPI_CPHA)
  

•           priv->dc |= QSPI_CKPHA(slave->cs);
  

•   if (priv->mode & SPI_CPOL)
  

•           priv->dc |= QSPI_CKPOL(slave->cs);
  

•   if (priv->mode & SPI_CS_HIGH)
  

•           priv->dc |= QSPI_CSPOL(slave->cs);
  

•   writel(priv->dc, &priv->base->dc);
    writel(0, &priv->base->cmd);
    writel(0, &priv->base->data);
  
  

•   priv->dc <<= cs * 8;
  

•   writel(priv->dc, &priv->base->dc);
    return 0;
  

}

-void spi_release_bus(struct spi_slave *slave) +static void __ti_qspi_release_bus(struct ti_qspi_priv *priv) {

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
  

•   writel(0, &priv->base->dc);
    writel(0, &priv->base->cmd);
    writel(0, &priv->base->data);
  

}

-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,

•        void *din, unsigned long flags)
  

+static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable) +{

•   u32 val;
  

•   val = readl(ctrl_mod_mmap);
  

•   if (enable)
  

•           val |= MEM_CS(cs);
  

•   else
  

•           val &= MEM_CS_UNSELECT;
  

•   writel(val, ctrl_mod_mmap);
  

+}

+static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,

•                   const void *dout, void *din, unsigned long flags,
  

•                   u32 cs)
  

{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
    uint words = bitlen >> 3; /* fixed 8-bit word length */
    const uchar *txp = dout;
    uchar *rxp = din;
    uint status;
    int timeout;
  
  

-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)

•   int val;
  

-#endif

•   debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
  

•         slave->bus, slave->cs, bitlen, words, flags);
  

•   /* Setup mmap flags */
    if (flags & SPI_XFER_MMAP) {
            writel(MM_SWITCH, &priv->base->memswitch);
  

-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)

•           val = readl(CORE_CTRL_IO);
  

•           val |= MEM_CS(slave->cs);
  

•           writel(val, CORE_CTRL_IO);
  

-#endif

•           if (priv->ctrl_mod_mmap)
  

•                   ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
            return 0;
    } else if (flags & SPI_XFER_MMAP_END) {
            writel(~MM_SWITCH, &priv->base->memswitch);
  

-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)

•           val = readl(CORE_CTRL_IO);
  

•           val &= MEM_CS_UNSELECT;
  

•           writel(val, CORE_CTRL_IO);
  

-#endif

•           if (priv->ctrl_mod_mmap)
  

•                   ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
            return 0;
    }
  
  

@@ -290,7 +211,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Setup command reg */ priv->cmd = 0; priv->cmd |= QSPI_WLEN(8);

•   priv->cmd |= QSPI_EN_CS(slave->cs);
  

•   priv->cmd |= QSPI_EN_CS(cs);
    if (flags & SPI_3WIRE)
            priv->cmd |= QSPI_3_PIN;
    priv->cmd |= 0xfff;
  

@@ -345,7 +266,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,

    /* Terminate frame */
    if (flags & SPI_XFER_END)

•           spi_cs_deactivate(slave);
  

•           ti_qspi_cs_deactivate(priv);
  
    return 0;
  

} @@ -372,3 +293,117 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len) *((unsigned int *)offset) += len; } #endif

+static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave) +{

•   return container_of(slave, struct ti_qspi_priv, slave);
  

+}

+int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{

•   return 1;
  

+}

+void spi_cs_activate(struct spi_slave *slave) +{

•   /* CS handled in xfer */
  

•   return;
  

+}

+void spi_cs_deactivate(struct spi_slave *slave) +{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   ti_qspi_cs_deactivate(priv);
  

+}

+void spi_init(void) +{

•   /* nothing to do */
  

+}

+static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) +{

•   u32 memval = 0;
  

+#ifdef CONFIG_QSPI_QUAD_SUPPORT

•   struct spi_slave *slave = &priv->slave;
  

•   memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
  

•                   QSPI_SETUP0_NUM_D_BYTES_8_BITS |
  

•                   QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
  

•                   QSPI_NUM_DUMMY_BITS);
  

•   slave->op_mode_rx = SPI_OPM_RX_QOF;
  

+#else

•   memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
  

•                   QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
  

•                   QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
  

•                   QSPI_NUM_DUMMY_BITS;
  

+#endif

•   writel(memval, &priv->base->setup0);
  

+}

+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,

•                             unsigned int max_hz, unsigned int mode)
  

+{

•   struct ti_qspi_priv *priv;
  

+#ifdef CONFIG_AM43XX

•   gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
  

•   gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
  

+#endif

•   priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
  

•   if (!priv) {
  

•           printf("SPI_error: Fail to allocate ti_qspi_priv\n");
  

•           return NULL;
  

•   }
  

•   priv->base = (struct ti_qspi_regs *)QSPI_BASE;
  

•   priv->mode = mode;
  

+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)

•   priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
  

•   priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
  

+#else

•   priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
  

+#endif

•   ti_spi_set_speed(priv, max_hz);
  

+#ifdef CONFIG_TI_SPI_MMAP

•   ti_spi_setup_spi_register(priv);
  

+#endif

•   return &priv->slave;
  

+}

+void spi_free_slave(struct spi_slave *slave) +{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   free(priv);
  

+}

+int spi_claim_bus(struct spi_slave *slave) +{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
  

•   __ti_qspi_set_mode(priv, priv->mode);
  

•   return __ti_qspi_claim_bus(priv, priv->slave.cs);
  

+} +void spi_release_bus(struct spi_slave *slave) +{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
  

•   __ti_qspi_release_bus(priv);
  

+}

+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,

•        void *din, unsigned long flags)
  

+{

•   struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
  

•   debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
  

•         priv->slave.bus, priv->slave.cs, bitlen, flags);
  

•   return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
  

+}

2.6.2.280.g74301d6

---

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

+Stephen

Hi,

On 4 November 2015 at 01:16, Mugunthan V N mugunthanvnm@ti.com wrote:

Add new api to get device address based on index.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/core/device.c | 16 ++++++++++++---- include/dm/device.h | 10 ++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-)

You are touching critical core code so I think we need to be careful here.

diff --git a/drivers/core/device.c b/drivers/core/device.c index 758f390..3cdcab5 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -581,18 +581,21 @@ const char *dev_get_uclass_name(struct udevice *dev) return dev->uclass->uc_drv->name; }

-fdt_addr_t dev_get_addr(struct udevice *dev) +fdt_addr_t dev_get_addr_index(struct udevice *dev, int index) { #if CONFIG_IS_ENABLED(OF_CONTROL) fdt_addr_t addr;

    if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
            const fdt32_t *reg;

•           int len = 0;
  
  

•           reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
  

•           if (!reg)
  

•           reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
  

•           if (!reg || (len <= (index * sizeof(fdt32_t) * 2)))
                    return FDT_ADDR_T_NONE;
  
  

•           reg += index * 2;
  

This seems to be assuming that the address and size each occupy a single cell, but that is not the case in general (e.g. with 64-bit machines).

I think you need to call fdt_addr_cells() and fdt_size_cells(). See fdtdec_get_addr_size_auto_parent() as an example.

            /*
             * Use the full-fledged translate function for complex
             * bus setups.

@@ -608,7 +611,7 @@ fdt_addr_t dev_get_addr(struct udevice *dev) addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, dev->parent->of_offset, dev->of_offset, "reg",

•                                           0, NULL);
  

•                                           index, NULL);
    if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
            if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
                    addr = simple_bus_translate(dev->parent, addr);
  

@@ -620,6 +623,11 @@ fdt_addr_t dev_get_addr(struct udevice *dev) #endif }

+fdt_addr_t dev_get_addr(struct udevice *dev) +{

•   return dev_get_addr_index(dev, 0);
  

+}

bool device_has_children(struct udevice *dev) { return !list_empty(&dev->child_head); diff --git a/include/dm/device.h b/include/dm/device.h index 28ba4ca..4de66d7 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -454,6 +454,16 @@ int device_find_next_child(struct udevice **devp); fdt_addr_t dev_get_addr(struct udevice *dev);

/**

• • dev_get_addr() - Get the reg property of a device

dev_get_addr_index

• • @dev: Pointer to a device
• • @index: reg address array index

I don't think this is sufficiently clear. Can you add a comment saying that the 'reg' property can hold a list of <addr, size> pairs and @index is used to select which one is used?

• • @return addr
• */

+fdt_addr_t dev_get_addr_index(struct udevice *dev, int index);

+/**

• device_has_children() - check if a device has any children
• @dev: Device to check

-- 2.6.2.280.g74301d6

Regards, Simon

On 4 November 2015 at 13:46, Mugunthan V N mugunthanvnm@ti.com wrote:

spi bus can support dual and quad wire data transfers for tx and rx. So defining dual and quad modes for both tx and rx. Also add support to parse bus width used for spi tx and rx transfers.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org

---

drivers/spi/spi-uclass.c | 33 +++++++++++++++++++++++++++++++++ include/spi.h | 4 ++++ 2 files changed, 37 insertions(+)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 58388ef..be365e4 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -349,6 +349,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) { int mode = 0;

•   int value;
  
    plat->cs = fdtdec_get_int(blob, node, "reg", -1);
    plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
  

@@ -360,6 +361,38 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_CS_HIGH; if (fdtdec_get_bool(blob, node, "spi-half-duplex")) mode |= SPI_PREAMBLE;

•   /* Device DUAL/QUAD mode */
  

•   value = fdtdec_get_int(blob, node, "spi-tx-bus-width", 1);
  

Value never be negative so better to use fdtdec_get_uint, comments?

•   switch (value) {
  

•   case 1:
  

•           break;
  

•   case 2:
  

•           mode |= SPI_TX_DUAL;
  

•           break;
  

•   case 4:
  

•           mode |= SPI_TX_QUAD;
  

•           break;
  

•   default:
  

•           error("spi-tx-bus-width %d not supported\n", value);
  

•           break;
  

•   }
  

•   value = fdtdec_get_int(blob, node, "spi-rx-bus-width", 1);
  

•   switch (value) {
  

•   case 1:
  

•           break;
  

•   case 2:
  

•           mode |= SPI_RX_DUAL;
  

•           break;
  

•   case 4:
  

•           mode |= SPI_RX_QUAD;
  

•           break;
  

•   default:
  

•           error("spi-rx-bus-width %d not supported\n", value);
  

•           break;
  

•   }
  

•   plat->mode = mode;
  
    return 0;
  

diff --git a/include/spi.h b/include/spi.h index b4d2723..40dbb4d 100644 --- a/include/spi.h +++ b/include/spi.h @@ -23,6 +23,10 @@ #define SPI_LOOP 0x20 /* loopback mode */ #define SPI_SLAVE 0x40 /* slave mode */ #define SPI_PREAMBLE 0x80 /* Skip preamble bytes */ +#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ +#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ +#define SPI_RX_DUAL 0x400 /* receive with 2 wires */ +#define SPI_RX_QUAD 0x800 /* receive with 4 wires */

/* SPI transfer flags */

#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */

2.6.2.280.g74301d6

---

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N mugunthanvnm@ti.com wrote:

Since spl doesn't support DM currently, do not define DM_SPI and DM_SPI_FLASH for spl build.

Do you mean 'Since OMAP's SPL doesn't support...'?

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

include/configs/dra7xx_evm.h | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6e32de8..525dce7 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -131,6 +131,11 @@ #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 #define CONFIG_QSPI_QUAD_SUPPORT

+#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#endif

/*

• Default to using SPI for environment, etc.
• 0x000000 - 0x010000 : QSPI.SPL (64KiB)

-- 2.6.2.280.g74301d6

Regards, Simon

On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:

Add qspi memory map and control module register maps to device tree.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org

---

arch/arm/dts/dra7.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 3060e9a..7045c0f 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1104,8 +1104,8 @@

qspi: qspi@4b300000 {
	compatible = "ti,dra7xxx-qspi";

• 	reg = <0x4b300000 0x100>;
  

• 	reg-names = "qspi_base";
  

• 	reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
  

• 	reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
  #address-cells = <1>;
  #size-cells = <0>;
  ti,hwmods = "qspi";
  

Is this already upstream?

On Thu, Nov 12, 2015 at 02:33:48PM +0530, Mugunthan V N wrote:

On Sunday 08 November 2015 07:01 PM, Tom Rini wrote:

...

On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:

...

Add qspi memory map and control module register maps to device tree.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org

---

arch/arm/dts/dra7.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 3060e9a..7045c0f 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1104,8 +1104,8 @@

qspi: qspi@4b300000 {
	compatible = "ti,dra7xxx-qspi";

• 	reg = <0x4b300000 0x100>;
  

• 	reg-names = "qspi_base";
  

• 	reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
  

• 	reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
  #address-cells = <1>;
  #size-cells = <0>;
  ti,hwmods = "qspi";
  

Is this already upstream?

The documentation part is already upstreamed. Driver in kernel doesn't support mmap mode yet so dt changes are not present. Vignesh has submitted the mmap patches [1] and is under review.

OK, and we can't even get the reg names part in the DT upstream until then?

On Sat, Nov 14, 2015 at 01:01:45PM +0530, Mugunthan V N wrote:

On Thursday 12 November 2015 06:17 PM, Tom Rini wrote:

...

On Thu, Nov 12, 2015 at 02:33:48PM +0530, Mugunthan V N wrote:

...

On Sunday 08 November 2015 07:01 PM, Tom Rini wrote:

...

On Wed, Nov 04, 2015 at 01:46:17PM +0530, Mugunthan V N wrote:

...

Add qspi memory map and control module register maps to device tree.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org

---

arch/arm/dts/dra7.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 3060e9a..7045c0f 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1104,8 +1104,8 @@

qspi: qspi@4b300000 {
	compatible = "ti,dra7xxx-qspi";

• 	reg = <0x4b300000 0x100>;
  

• 	reg-names = "qspi_base";
  

• 	reg = <0x4b300000 0x100>, <0x5c000000 0x4000000>, <0x4a002558 0x4>;
  

• 	reg-names = "qspi_base", "qspi_mmap", "qspi_ctrlmod";
  #address-cells = <1>;
  #size-cells = <0>;
  ti,hwmods = "qspi";
  

Is this already upstream?

The documentation part is already upstreamed. Driver in kernel doesn't support mmap mode yet so dt changes are not present. Vignesh has submitted the mmap patches [1] and is under review.

OK, and we can't even get the reg names part in the DT upstream until then?

I don't think we can get reg names in the DT upstream separately. But there shouldn't be any issues as there is documentation already present in kernel and submitted kernel patch DT nodes are similar to what I have submitted.

Similar or the same? We'll be dropping in (and quick diff'ing) a new DT from the kernel at some point in the future. So if there's chance of things changing, we want to wait.

On Friday 06 November 2015 05:37 PM, Simon Glass wrote:

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N mugunthanvnm@ti.com wrote:

...

Add compatible for spansion 32MiB spi flash s25fl256s1.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/mtd/spi/sf_probe.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index c000c53..9cfa9b6 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {

static const struct udevice_id spi_flash_std_ids[] = { { .compatible = "spi-flash" },

•   { .compatible = "s25fl256s1" },
  

Instead, is it possible to add "spi-flash" to the list of compatible strings in your device tree?

The compatible "spi-flash" is not defined/documented in kernel and compatible "s25fl256s1" is already documented and present in dt files. So it will be good to follow the same dt compatibles in U-Boot so that future merge/sync will be easier.

Regards Mugunthan V N

Hi,

On 12 November 2015 at 05:48, Tom Rini trini@konsulko.com wrote:

On Thu, Nov 12, 2015 at 02:42:41PM +0530, Mugunthan V N wrote:

...

On Friday 06 November 2015 05:37 PM, Simon Glass wrote:

...

Hi Mugunthan,

On 4 November 2015 at 01:16, Mugunthan V N mugunthanvnm@ti.com wrote:

...

Add compatible for spansion 32MiB spi flash s25fl256s1.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com

drivers/mtd/spi/sf_probe.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index c000c53..9cfa9b6 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -502,6 +502,7 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = {

static const struct udevice_id spi_flash_std_ids[] = { { .compatible = "spi-flash" },

•   { .compatible = "s25fl256s1" },
  

Instead, is it possible to add "spi-flash" to the list of compatible strings in your device tree?

The compatible "spi-flash" is not defined/documented in kernel and compatible "s25fl256s1" is already documented and present in dt files. So it will be good to follow the same dt compatibles in U-Boot so that future merge/sync will be easier.

Agreed.

I see this in kernel upstream at present:

git grep s25fl256s1 arch/arm/boot/dts/dra7-evm.dts: compatible = "s25fl256s1"; arch/arm/boot/dts/dra72-evm.dts: compatible = "s25fl256s1"; arch/arm/boot/dts/qcom-ipq8064-ap148.dts: compatible = "s25fl256s1"; arch/powerpc/boot/dts/fsl/kmcoge4.dts: compatible = "spansion,s25fl256s1"; drivers/mtd/devices/m25p80.c: {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, drivers/mtd/devices/st_spi_fsm.c: { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, drivers/mtd/spi-nor/spi-nor.c: { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

There seems to be some confusion as to whether to include "spansion" or not. I feel it should be included.

The problem is that in U-Boot at present this compatible string does not affect any behaviour. We still scan the chip to figure out its type from its ID. Do you want to add a .data value for it, and skip the probing, or are you just trying to trigger the driver to bind?

Regards, Simon

On Wed, Nov 04, 2015 at 01:46:23PM +0530, Mugunthan V N wrote:

Add qspi memory map address to device tree.

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org

---

arch/arm/dts/am4372.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi index ade28c7..1b30d53 100644 --- a/arch/arm/dts/am4372.dtsi +++ b/arch/arm/dts/am4372.dtsi @@ -25,6 +25,7 @@ serial0 = &uart0; ethernet0 = &cpsw_emac0; ethernet1 = &cpsw_emac1;

• spi0 = &qspi;
  

  };

  cpus {

@@ -902,7 +903,8 @@

qspi: qspi@47900000 {
	compatible = "ti,am4372-qspi";

• 	reg = <0x47900000 0x100>;
  

• 	reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
  

• 	reg-names = "qspi_base", "qspi_mmap";
  #address-cells = <1>;
  #size-cells = <0>;
  ti,hwmods = "qspi";
  

Is this upstream already?

On 4 November 2015 at 13:46, Mugunthan V N mugunthanvnm@ti.com wrote:

enable mmc driver model for am437x_sk_evm as ti_qspi supports

typo its should be spi not mmc.

driver model

Signed-off-by: Mugunthan V N mugunthanvnm@ti.com Reviewed-by: Simon Glass sjg@chromium.org

---

configs/am437x_sk_evm_defconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig index 02485f8..ba0ab84 100644 --- a/configs/am437x_sk_evm_defconfig +++ b/configs/am437x_sk_evm_defconfig @@ -15,3 +15,6 @@ CONFIG_SPI_FLASH=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y

+CONFIG_SPI_FLASH_BAR=y

2.6.2.280.g74301d6

---

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