Move arch/arm/include/asm/arch-armada-xp/* -> arch/arm/mach-mvebu/include/mach/*

Additionally the SYS_SOC is renamed from "armada-xp" to "mvebu". With this change all these files can better be shared with other, newer Mavell MVEBU SoC's. Like the upcoming Armada 38x support.

Signed-off-by: Stefan Roese sr@denx.de Cc: Masahiro Yamada yamada.masahiro@socionext.com Tested-by: Kevin Smith kevin.smith@elecsyscorp.com Tested-by: Dirk Eibach dirk.eibach@gdsys.cc ---

Changes in v3: None Changes in v2: None

arch/arm/Makefile | 2 +- .../{include/asm/arch-armada-xp => mach-mvebu/include/mach}/config.h | 0 arch/arm/{include/asm/arch-armada-xp => mach-mvebu/include/mach}/cpu.h | 0 arch/arm/{include/asm/arch-armada-xp => mach-mvebu/include/mach}/soc.h | 0 board/Marvell/db-mv784mp-gp/Kconfig | 2 +- board/maxbcm/Kconfig | 2 +- 6 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm/{include/asm/arch-armada-xp => mach-mvebu/include/mach}/config.h (100%) rename arch/arm/{include/asm/arch-armada-xp => mach-mvebu/include/mach}/cpu.h (100%) rename arch/arm/{include/asm/arch-armada-xp => mach-mvebu/include/mach}/soc.h (100%)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 7bd53c5..32c152d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -85,7 +85,7 @@ libs-y += arch/arm/imx-common/ endif endif

-ifneq (,$(filter $(SOC), armada-xp kirkwood)) +ifneq (,$(filter $(SOC), mvebu kirkwood)) libs-y += arch/arm/mvebu-common/ endif

diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/mach-mvebu/include/mach/config.h similarity index 100% rename from arch/arm/include/asm/arch-armada-xp/config.h rename to arch/arm/mach-mvebu/include/mach/config.h diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h similarity index 100% rename from arch/arm/include/asm/arch-armada-xp/cpu.h rename to arch/arm/mach-mvebu/include/mach/cpu.h diff --git a/arch/arm/include/asm/arch-armada-xp/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h similarity index 100% rename from arch/arm/include/asm/arch-armada-xp/soc.h rename to arch/arm/mach-mvebu/include/mach/soc.h diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig index 98aa10a..d0b426e 100644 --- a/board/Marvell/db-mv784mp-gp/Kconfig +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "Marvell"

config SYS_SOC - default "armada-xp" + default "mvebu"

config SYS_CONFIG_NAME default "db-mv784mp-gp" diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig index d833ca0..e86aa16 100644 --- a/board/maxbcm/Kconfig +++ b/board/maxbcm/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "maxbcm"

config SYS_SOC - default "armada-xp" + default "mvebu"

config SYS_CONFIG_NAME default "maxbcm"

Since these files will be used for other MVEBU SoC's, lets reflect this in the headers marcos as well.

Signed-off-by: Stefan Roese sr@denx.de Tested-by: Kevin Smith kevin.smith@elecsyscorp.com Tested-by: Dirk Eibach dirk.eibach@gdsys.cc ---

Changes in v3: None Changes in v2: None

arch/arm/mach-mvebu/include/mach/config.h | 6 +++--- arch/arm/mach-mvebu/include/mach/cpu.h | 6 +++--- arch/arm/mach-mvebu/include/mach/soc.h | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index f9fd424..01b725b 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -12,8 +12,8 @@ * It supports common definitions for Armada XP platforms */

-#ifndef _ARMADA_XP_CONFIG_H -#define _ARMADA_XP_CONFIG_H +#ifndef _MVEBU_CONFIG_H +#define _MVEBU_CONFIG_H

#include <asm/arch/soc.h>

@@ -83,4 +83,4 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif

-#endif /* _ARMADA_XP_CONFIG_H */ +#endif /* __MVEBU_CONFIG_H */ diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 4f5ff96..297ac52 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#ifndef _ARMADA_XP_CPU_H -#define _ARMADA_XP_CPU_H +#ifndef _MVEBU_CPU_H +#define _MVEBU_CPU_H

#include <asm/system.h>

@@ -120,4 +120,4 @@ int serdes_phy_config(void); */ int ddr3_init(void); #endif /* __ASSEMBLY__ */ -#endif /* _ARMADA_XP_CPU_H */ +#endif /* _MVEBU_CPU_H */ diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 963e7ac..202d5b8 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -8,8 +8,8 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#ifndef _ASM_ARCH_ARMADA_XP_H -#define _ASM_ARCH_ARMADA_XP_H +#ifndef _MVEBU_SOC_H +#define _MVEBU_SOC_H

#define SOC_MV78460_ID 0x7846

@@ -49,9 +49,9 @@ /* Armada XP GbE controller has 4 ports */ #define MAX_MVNETA_DEVS 4

-/* Kirkwood CPU memory windows */ +/* MVEBU CPU memory windows */ #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE

-#endif /* _ASM_ARCH_ARMADA_XP_H */ +#endif /* _MVEBU_SOC_H */

This define is used by the DDR training code for Armada XP. With the upcoming addition of Armada 38x support, lets only define it for Armada XP in this common header.

Signed-off-by: Stefan Roese sr@denx.de Tested-by: Kevin Smith kevin.smith@elecsyscorp.com Tested-by: Dirk Eibach dirk.eibach@gdsys.cc ---

Changes in v3: None Changes in v2: None

arch/arm/mach-mvebu/include/mach/config.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 01b725b..86a0aed 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -9,7 +9,7 @@ /* * This file should be included in board config header file. * - * It supports common definitions for Armada XP platforms + * It supports common definitions for MVEBU platforms */

#ifndef _MVEBU_CONFIG_H @@ -17,7 +17,9 @@

#include <asm/arch/soc.h>

+#if defined(CONFIG_ARMADA_XP) #define MV88F78X60 /* for the DDR training bin_hdr code */ +#endif

#define CONFIG_SYS_CACHELINE_SIZE 32

This patch adds support for the Marvell Armada 38x SoC family.

Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash)

Tested on Marvell DB-88F6820-GP evaluation board.

Signed-off-by: Stefan Roese sr@denx.de Tested-by: Kevin Smith kevin.smith@elecsyscorp.com Tested-by: Dirk Eibach dirk.eibach@gdsys.cc

---

Changes in v3: None Changes in v2: - Made mvebu_soc_family() globally available so that it can be called from mbus.c - Add PL310 L2 cache base address

arch/arm/mach-mvebu/cpu.c | 73 ++++++++++++++++++++++++++-------- arch/arm/mach-mvebu/include/mach/cpu.h | 7 ++++ arch/arm/mach-mvebu/include/mach/soc.h | 9 +++++ 3 files changed, 73 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1cf70a9..eca5e21 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Stefan Roese sr@denx.de + * Copyright (C) 2014-2015 Stefan Roese sr@denx.de * * SPDX-License-Identifier: GPL-2.0+ */ @@ -40,6 +40,20 @@ void reset_cpu(unsigned long ignored) ; }

+int mvebu_soc_family(void) +{ + u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; + + if (devid == SOC_MV78460_ID) + return MVEBU_SOC_AXP; + + if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID || + devid == SOC_88F6828_ID) + return MVEBU_SOC_A38X; + + return MVEBU_SOC_UNKNOWN; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -52,23 +66,48 @@ int print_cpuinfo(void) case SOC_MV78460_ID: puts("MV78460-"); break; - default: - puts("Unknown-"); + case SOC_88F6810_ID: + puts("MV88F6810-"); break; - } - - switch (revid) { - case 1: - puts("A0\n"); + case SOC_88F6820_ID: + puts("MV88F6820-"); break; - case 2: - puts("B0\n"); + case SOC_88F6828_ID: + puts("MV88F6828-"); break; default: - puts("??\n"); + puts("Unknown-"); break; }

+ if (mvebu_soc_family() == MVEBU_SOC_AXP) { + switch (revid) { + case 1: + puts("A0\n"); + break; + case 2: + puts("B0\n"); + break; + default: + printf("?? (%x)\n", revid); + break; + } + } + + if (mvebu_soc_family() == MVEBU_SOC_A38X) { + switch (revid) { + case MV_88F68XX_Z1_ID: + puts("Z1\n"); + break; + case MV_88F68XX_A0_ID: + puts("A0\n"); + break; + default: + printf("?? (%x)\n", revid); + break; + } + } + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -145,11 +184,13 @@ int arch_cpu_init(void) */ mvebu_mbus_probe(NULL, 0);

- /* - * Now the SDRAM access windows can be reconfigured using - * the information in the SDRAM scratch pad registers - */ - update_sdram_window_sizes(); + if (mvebu_soc_family() == MVEBU_SOC_AXP) { + /* + * Now the SDRAM access windows can be reconfigured using + * the information in the SDRAM scratch pad registers + */ + update_sdram_window_sizes(); + }

/* * Finally the mbus windows can be configured with the diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 297ac52..3b48460 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -56,6 +56,12 @@ enum cpu_attrib { CPU_ATTR_DEV_CS3 = 0x37, };

+enum { + MVEBU_SOC_AXP, + MVEBU_SOC_A38X, + MVEBU_SOC_UNKNOWN, +}; + /* * Default Device Address MAP BAR values */ @@ -106,6 +112,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_soc_family(void);

/* * Highspeed SERDES PHY config init, ported from bin_hdr diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index f3e0398..0a9307c 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -12,6 +12,13 @@ #define _MVEBU_SOC_H

#define SOC_MV78460_ID 0x7846 +#define SOC_88F6810_ID 0x6810 +#define SOC_88F6820_ID 0x6820 +#define SOC_88F6828_ID 0x6828 + +/* A38x revisions */ +#define MV_88F68XX_Z1_ID 0x0 +#define MV_88F68XX_A0_ID 0x4

/* TCLK Core Clock definition */ #ifndef CONFIG_SYS_TCLK @@ -25,6 +32,8 @@ #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)

#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) +#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) +#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) #define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))

This enables the usage of the "preboot" environment variable on Marvell boards.

Signed-off-by: Stefan Roese sr@denx.de Tested-by: Kevin Smith kevin.smith@elecsyscorp.com Tested-by: Dirk Eibach dirk.eibach@gdsys.cc ---

Changes in v3: None Changes in v2: None

include/configs/mv-common.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 721b75d..51436da 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -57,6 +57,7 @@ 115200,230400, 460800, 921600 } /* auto boot */ #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ +#define CONFIG_PREBOOT

/* * For booting Linux, the board info and command line data

This patch adds support for the Marvell DB-88F6820-GP Armada A38x evaluation board.

Supported peripherals are: - UART - Ethernet (mvneta) - I2C - SPI (including SPI NOR flash)

Please note that this board support right now only supports the main U-Boot. Without the bin_hdr integration (DDR training etc). This will be added in a few days / weeks to complete this board port. But till then this U-Boot version can be run on the target via the original Marvell U-Boot via this command:

tftpboot 4000000 db-88f6820-gp/u-boot.bin;go 4000000

Signed-off-by: Stefan Roese sr@denx.de Tested-by: Kevin Smith kevin.smith@elecsyscorp.com Tested-by: Dirk Eibach dirk.eibach@gdsys.cc

---

Changes in v3: - Changed CONFIG_I2C_MVTWSI_BASE to CONFIG_I2C_MVTWSI_BASE0 for updates in mvtwsi I2C driver - Added Tested-by from Dirk and Kevin

Changes in v2: - Update to 256KiB env sector as required for M25P128 - Add I2C IO expander initialization (fan etc) - Enable PL310 L2 cache as this is needed for correct caching OPs

arch/arm/Kconfig | 6 ++ board/Marvell/db-88f6820-gp/Kconfig | 15 ++++ board/Marvell/db-88f6820-gp/Makefile | 7 ++ board/Marvell/db-88f6820-gp/binary.0 | 16 +++++ board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 103 ++++++++++++++++++++++++++++ board/Marvell/db-88f6820-gp/kwbimage.cfg | 12 ++++ configs/db-88f6820-gp_defconfig | 2 + include/configs/db-88f6820-gp.h | 72 +++++++++++++++++++ 8 files changed, 233 insertions(+) create mode 100644 board/Marvell/db-88f6820-gp/Kconfig create mode 100644 board/Marvell/db-88f6820-gp/Makefile create mode 100644 board/Marvell/db-88f6820-gp/binary.0 create mode 100644 board/Marvell/db-88f6820-gp/db-88f6820-gp.c create mode 100644 board/Marvell/db-88f6820-gp/kwbimage.cfg create mode 100644 configs/db-88f6820-gp_defconfig create mode 100644 include/configs/db-88f6820-gp.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b39bb4f..3cb5fda 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -102,6 +102,11 @@ config KIRKWOOD bool "Marvell Kirkwood" select CPU_ARM926EJS

+config TARGET_DB_88F6820_GP + bool "Support DB-88F6820-GP" + select CPU_V7 + select SUPPORT_SPL + config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" select CPU_V7 @@ -823,6 +828,7 @@ source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" +source "board/Marvell/db-88f6820-gp/Kconfig" source "board/Marvell/db-mv784mp-gp/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/altera/socfpga/Kconfig" diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig new file mode 100644 index 0000000..b2e9115 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DB_88F6820_GP + +config SYS_BOARD + default "db-88f6820-gp" + +config SYS_VENDOR + default "Marvell" + +config SYS_SOC + default "mvebu" + +config SYS_CONFIG_NAME + default "db-88f6820-gp" + +endif diff --git a/board/Marvell/db-88f6820-gp/Makefile b/board/Marvell/db-88f6820-gp/Makefile new file mode 100644 index 0000000..58d40dd --- /dev/null +++ b/board/Marvell/db-88f6820-gp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Stefan Roese sr@denx.de +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-88f6820-gp.o diff --git a/board/Marvell/db-88f6820-gp/binary.0 b/board/Marvell/db-88f6820-gp/binary.0 new file mode 100644 index 0000000..57a4cbf --- /dev/null +++ b/board/Marvell/db-88f6820-gp/binary.0 @@ -0,0 +1,16 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. + +In a few weeks, mainline U-Boot will get support to generate the +bin_hdr with the DDR training code itself. By implementing this code +as SPL U-Boot. Then this file will not be needed any more and will +get removed. diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c new file mode 100644 index 0000000..51ac495 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2015 Stefan Roese sr@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT(nr) (1UL << (nr)) + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2014_T3.0" + */ +#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \ + (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ + BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ + BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) +#define DB_GP_88F68XX_GPP_OUT_ENA_MID \ + (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ + BIT(16) | BIT(17) | BIT(18))) + +#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0 +#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0 +#define DB_GP_88F68XX_GPP_POL_LOW 0x0 +#define DB_GP_88F68XX_GPP_POL_MID 0x0 + +/* IO expander on Marvell GP board includes e.g. fan enabling */ +struct marvell_io_exp { + u8 chip; + u8 addr; + u8 val; +}; + +static struct marvell_io_exp io_exp[] = { + { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */ + { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ + { 0x20, 2, 0x1D }, /* Output Data, register#0 */ + { 0x20, 3, 0x18 }, /* Output Data, register#1 */ + { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ + { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */ + { 0x21, 2, 0x08 }, /* Output Data, register#0 */ + { 0x21, 3, 0xC0 } /* Output Data, register#1 */ +}; + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x11111111, MVEBU_MPP_BASE + 0x00); + writel(0x11111111, MVEBU_MPP_BASE + 0x04); + writel(0x11244011, MVEBU_MPP_BASE + 0x08); + writel(0x22222111, MVEBU_MPP_BASE + 0x0c); + writel(0x22200002, MVEBU_MPP_BASE + 0x10); + writel(0x30042022, MVEBU_MPP_BASE + 0x14); + writel(0x55550555, MVEBU_MPP_BASE + 0x18); + writel(0x00005550, MVEBU_MPP_BASE + 0x1c); + + /* Set GPP Out value */ + writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + int i; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Init I2C IO expanders */ + for (i = 0; i < ARRAY_SIZE(io_exp); i++) + i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Marvell DB-88F6820-GP\n"); + + return 0; +} diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg new file mode 100644 index 0000000..e812454 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese sr@denx.de +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068 diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig new file mode 100644 index 0000000..0d6f0de --- /dev/null +++ b/configs/db-88f6820-gp_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_DB_88F6820_GP=y diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h new file mode 100644 index 0000000..12a24ce --- /dev/null +++ b/include/configs/db-88f6820-gp.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014 Stefan Roese sr@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DB_88F6820_GP_H +#define _CONFIG_DB_88F6820_GP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ + +#define CONFIG_SYS_L2_PL310 + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x04000000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_STMICRO + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_ADDR { 1, 0 } +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_DB_88F6820_GP_H */