On Wed, 16 Aug 2023 10:34:16 -0700 Sam Edwards cfsworks@gmail.com wrote:

Hi Sam,

thanks for the update.

This patch restructures psci.c to get away from the "many different function definitions switched by #ifdef" paradigm to the preferred style of having a single function definition with `if (IS_ENABLED(...))` to make the optimizer include only the appropriate function bodies instead.

There are no functional changes here.

So this diff is hard to read - not your fault, this seems to be common for those kind of refactorings - but I convinced myself by comparing old and new side-by-side and test-compiling that this doesn't introduce any functional change. The resulting object file is different (8 byte larger, even), so it's hard to prove, and I still have to actually test it on some boards, but the idea is a good one and it's the right direction, so to move things forward:

Signed-off-by: Sam Edwards CFSworks@gmail.com

Reviewed-by: Andre Przywara andre.przywara@arm.com

Cheers, Andre

---

arch/arm/cpu/armv7/sunxi/psci.c | 102 +++++++++++++------------------- 1 file changed, 42 insertions(+), 60 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index e1d3638b5c..7804e0933b 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -76,11 +76,8 @@ static void __secure __mdelay(u32 ms) isb(); }

-static void __secure clamp_release(u32 __maybe_unused *clamp) +static void __secure clamp_release(u32 *clamp) { -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \

• defined(CONFIG_MACH_SUN8I_H3) || \
• defined(CONFIG_MACH_SUN8I_R40) u32 tmp = 0x1ff; do { tmp >>= 1;

@@ -88,83 +85,68 @@ static void __secure clamp_release(u32 __maybe_unused *clamp) } while (tmp);

__mdelay(10); -#endif }

-static void __secure clamp_set(u32 __maybe_unused *clamp) +static void __secure clamp_set(u32 *clamp) { -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \

• defined(CONFIG_MACH_SUN8I_H3) || \
• defined(CONFIG_MACH_SUN8I_R40) writel(0xff, clamp);

-#endif }

-static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,

• 			int cpu)
  

+static void __secure sunxi_set_entry_address(void *entry) {

• if (on) {

• /* Release power clamp */
  

• clamp_release(clamp);
  

• /* Clear power gating */
  

• clrbits_le32(pwroff, BIT(cpu));
  

• /* secondary core entry address is programmed differently on R40 */
• if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {

• writel((u32)entry,
  

•        SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
  

  } else {

• /* Set power gating */
  

• setbits_le32(pwroff, BIT(cpu));
  

• struct sunxi_cpucfg_reg *cpucfg =
  

• 	(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  
  

• /* Activate power clamp */
  

• clamp_set(clamp);
  

• writel((u32)entry, &cpucfg->priv0);
  

  }

}

-#ifdef CONFIG_MACH_SUN8I_R40 -/* secondary core entry address is programmed differently on R40 */ -static void __secure sunxi_set_entry_address(void *entry) -{

• writel((u32)entry,

•       SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
  

-} -#else -static void __secure sunxi_set_entry_address(void *entry) +static void __secure sunxi_cpu_set_power(int cpu, bool on) {

• u32 *clamp = NULL;
• u32 *pwroff; struct sunxi_cpucfg_reg *cpucfg = (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;

• writel((u32)entry, &cpucfg->priv0);

-} -#endif

• /* sun7i (A20) is different from other single cluster SoCs */
• if (IS_ENABLED(CONFIG_MACH_SUN7I)) {

• clamp = &cpucfg->cpu1_pwr_clamp;
  

• pwroff = &cpucfg->cpu1_pwroff;
  

• } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {

• clamp = (void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu);
  

• pwroff = (void *)cpucfg + SUN8I_R40_PWROFF;
  

• } else {

• struct sunxi_prcm_reg *prcm =
  

• 	(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  
  

-#ifdef CONFIG_MACH_SUN7I -/* sun7i (A20) is different from other single cluster SoCs */ -static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on) -{

• struct sunxi_cpucfg_reg *cpucfg =

• (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  

• if (IS_ENABLED(CONFIG_MACH_SUN6I) ||
  

•     IS_ENABLED(CONFIG_MACH_SUN8I_H3))
  

• 	clamp = &prcm->cpu_pwr_clamp[cpu];
  
  

• sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,

• 	   on, 0);
  

-} -#elif defined CONFIG_MACH_SUN8I_R40 -static void __secure sunxi_cpu_set_power(int cpu, bool on) -{

• struct sunxi_cpucfg_reg *cpucfg =

• (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  

• pwroff = &prcm->cpu_pwroff;
  

• }

• sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),

• 	   (void *)cpucfg + SUN8I_R40_PWROFF,
  

• 	   on, cpu);
  

-} -#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */ -static void __secure sunxi_cpu_set_power(int cpu, bool on) -{

• struct sunxi_prcm_reg *prcm =

• (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  

• if (on) {

• /* Release power clamp */
  

• if (clamp)
  

• 	clamp_release(clamp);
  
  

• sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,

• 	   on, cpu);
  

• /* Clear power gating */
  

• clrbits_le32(pwroff, BIT(cpu));
  

• } else {

• /* Set power gating */
  

• setbits_le32(pwroff, BIT(cpu));
  

• /* Activate power clamp */
  

• if (clamp)
  

• 	clamp_set(clamp);
  

• }

} -#endif /* CONFIG_MACH_SUN7I */

void __secure sunxi_cpu_power_off(u32 cpuid) {

On Wed, 16 Aug 2023 10:34:17 -0700 Sam Edwards cfsworks@gmail.com wrote:

Hi Sam,

This is to prepare for R528, which does not have the typical "CPUCFG" block; it has a "CPUX" block which provides these same functions but is organized differently.

Moving the hardware-access bits to their own functions separates the logic from the hardware so we can reuse the same logic.

That's a very nice cleanup, thanks for doing that!

Another one of those hard-to-reason-about diffs, but I placed the register access back into the place of the new function call, somewhat playing your patch backwards, manually, and that ended up at a very similar code to before the patch, so I think it's legit. Again, needs some testing, but looks good from a diff point of view.

Two smaller things, with them fixed:

Signed-off-by: Sam Edwards CFSworks@gmail.com

Reviewed-by: Andre Przywara andre.przywara@arm.com

Cheers, Andre

---

arch/arm/cpu/armv7/sunxi/psci.c | 66 +++++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 7804e0933b..e2845f21ab 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -92,7 +92,7 @@ static void __secure clamp_set(u32 *clamp) writel(0xff, clamp); }

-static void __secure sunxi_set_entry_address(void *entry) +static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)

So what is the reasoning behind this change? If *none* of the Allwinner SoCs have independent secondary entry point registers, we should not give the impression some do in the prototype. Should later a SoC emerge that changes this, adjusting this one is the least of our problems then.

{ /* secondary core entry address is programmed differently on R40 */ if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { @@ -148,30 +148,60 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on) } }

-void __secure sunxi_cpu_power_off(u32 cpuid) +static void __secure sunxi_cpu_set_reset(int cpu, bool reset) +{

• struct sunxi_cpucfg_reg *cpucfg =

• (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  

• writel(reset ? 0b00 : 0b11, &cpucfg->cpu[cpu].rst);

+}

+static void __secure sunxi_cpu_set_locking(int cpu, bool lock) { struct sunxi_cpucfg_reg *cpucfg = (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;

• if (lock)

• clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
  

• else

• setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
  

+}

+static bool __secure sunxi_cpu_poll_wfi(int cpu) +{

• struct sunxi_cpucfg_reg *cpucfg =

• (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  

• return !!(readl(&cpucfg->cpu[cpu].status) & BIT(2));

+}

+static void __secure sunxi_cpu_invalidate_cache(int cpu) +{

• struct sunxi_cpucfg_reg *cpucfg =

• (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  

• clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));

+}

+void __secure sunxi_cpu_power_off(u32 cpuid)

Can you please mark this as static on the way? That does not seem to be used anywhere, and even the name suggests it's local. Saves 8 bytes of .text ;-)

+{ u32 cpu = cpuid & 0x3;

/* Wait for the core to enter WFI */

• while (1) {

• if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
  

• 	break;
  

• while (!sunxi_cpu_poll_wfi(cpu)) __mdelay(1);

• }

  /* Assert reset on target CPU */

• writel(0, &cpucfg->cpu[cpu].rst);

• sunxi_cpu_set_reset(cpu, true);

  /* Lock CPU (Disable external debug access) */

• clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));

• sunxi_cpu_set_locking(cpu, true);

  /* Power down CPU */ sunxi_cpu_set_power(cpuid, false);

• /* Unlock CPU (Disable external debug access) */
• setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));

• /* Unlock CPU (Reenable external debug access) */
• sunxi_cpu_set_locking(cpu, false);

}

static u32 __secure cp15_read_scr(void) @@ -228,33 +258,31 @@ out: int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc, u32 context_id) {

• struct sunxi_cpucfg_reg *cpucfg =

• (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
  

  u32 cpu = (mpidr & 0x3);

  /* store target PC and context id */ psci_save(cpu, pc, context_id);

  /* Set secondary core power on PC */

• sunxi_set_entry_address(&psci_cpu_entry);

• sunxi_cpu_set_entry(cpu, &psci_cpu_entry);

  /* Assert reset on target CPU */

• writel(0, &cpucfg->cpu[cpu].rst);

• sunxi_cpu_set_reset(cpu, true);

  /* Invalidate L1 cache */

• clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));

• sunxi_cpu_invalidate_cache(cpu);

  /* Lock CPU (Disable external debug access) */

• clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));

• sunxi_cpu_set_locking(cpu, true);

  /* Power up target CPU */ sunxi_cpu_set_power(cpu, true);

  /* De-assert reset on target CPU */

• writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);

• sunxi_cpu_set_reset(cpu, false);

• /* Unlock CPU (Disable external debug access) */
• setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));

• /* Unlock CPU (Reenable external debug access) */

• sunxi_cpu_set_locking(cpu, false);

  return ARM_PSCI_RET_SUCCESS;

}

On Wed, 16 Aug 2023 10:34:19 -0700 Sam Edwards cfsworks@gmail.com wrote:

Hi Sam,

This patch adds the necessary code to make nonsec booting and PSCI secondary core management functional on the R528/T113.

Signed-off-by: Sam Edwards CFSworks@gmail.com Tested-by: Maksim Kiselev bigunclemax@gmail.com

---

arch/arm/cpu/armv7/sunxi/psci.c | 48 ++++++++++++++++++++++++++++++++- arch/arm/mach-sunxi/Kconfig | 2 ++ include/configs/sunxi-common.h | 8 ++++++ 3 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 6ecdd05250..b4ce4f6def 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -47,6 +47,19 @@ #define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4) #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)

+/*

• • R528 is also different, as it has both cores powered up (but held in reset
• • state) after the SoC is reset. Like the R40, it uses a "soft" entry point
• • address register, but unlike the R40, it uses a newer "CPUX" block to manage
• • CPU state, rather than the older CPUCFG system.
• */

+#define SUN8I_R528_SOFT_ENTRY (0x1c8) +#define SUN8I_R528_C0_RST_CTRL (0x0000) +#define SUN8I_R528_C0_CTRL_REG0 (0x0010) +#define SUN8I_R528_C0_CPU_STATUS (0x0080)

+#define SUN8I_R528_C0_STATUS_STANDBYWFI (16)

static void __secure cp15_write_cntp_tval(u32 tval) { asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval)); @@ -103,10 +116,13 @@ static void __secure clamp_set(u32 *clamp)

static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry) {

• /* secondary core entry address is programmed differently on R40 */

• /* secondary core entry address is programmed differently on R40/528 */

I think that's somewhat obvious now from the code, so you can remove this comment.

if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { writel((u32)entry, SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);

• } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• writel((u32)entry,
  

•        SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
  

  } else { writel((u32)entry, SUNXI_CPUCFG_BASE + SUNXI_PRIV0); }

@@ -124,6 +140,9 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on) } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { clamp = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWR_CLAMP(cpu); pwroff = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWROFF;

• } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• /* R528 leaves both cores powered up, manages them via reset */
  

• return;
  

  } else { if (IS_ENABLED(CONFIG_MACH_SUN6I) || IS_ENABLED(CONFIG_MACH_SUN8I_H3))

@@ -151,11 +170,27 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)

static void __secure sunxi_cpu_set_reset(int cpu, bool reset) {

• if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• if (reset) {
  

I think you can lose the brackets here, since it's a single statement branch, even if it spans multiple lines. The indentation should make this clear.

• 	clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
  

• 		     BIT(cpu));
  

• } else {
  

• 	setbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
  

• 		     BIT(cpu));
  

• }
  

• return;
  

• }
• writel(reset ? 0b00 : 0b11, SUNXI_CPUCFG_BASE + SUNXI_CPU_RST(cpu));

}

static void __secure sunxi_cpu_set_locking(int cpu, bool lock) {

• if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• /* Not required on R528 */
  

• return;
  

• }
• if (lock) clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_DBG_CTRL1, BIT(cpu)); else

@@ -164,11 +199,22 @@ static void __secure sunxi_cpu_set_locking(int cpu, bool lock)

static bool __secure sunxi_cpu_poll_wfi(int cpu) {

• if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• return !!(readl(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CPU_STATUS) &
  

• 	  BIT(SUN8I_R528_C0_STATUS_STANDBYWFI + cpu));
  

• }
• return !!(readl(SUNXI_CPUCFG_BASE + SUNXI_CPU_STATUS(cpu)) & BIT(2));

}

static void __secure sunxi_cpu_invalidate_cache(int cpu) {

• if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CTRL_REG0,
  

• 	     BIT(cpu));
  

• return;
  

• }
• clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_GEN_CTRL, BIT(cpu));

}

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 0a3454a51a..d46fd8c0bc 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -355,6 +355,8 @@ config MACH_SUN8I_R40 config MACH_SUN8I_R528 bool "sun8i (Allwinner R528)" select CPU_V7A

• select CPU_V7_HAS_NONSEC
• select ARCH_SUPPORT_PSCI

Please add select CPU_V7_HAS_VIRT here, as the cores are perfectly capable of virtualisation. Granted, support for KVM is long gone from Linux, but at least Xen still supports it. And I believe you also need: select SPL_ARMV7_SET_CORTEX_SMPEN At least this is what the other cores do. The PSCI code sets this bit for the secondaries, but for the primary core we need to set it as early as possible. Probably not a biggie on an A7, in reality, but good to have, and be it for correctness and consistency's sake.

select SUNXI_GEN_NCAT2 select SUNXI_NEW_PINCTRL select MMC_SUNXI_HAS_NEW_MODE diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b8ca77d031..67eb0d25db 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -33,6 +33,14 @@

/* CPU */

+/*

• • Newer ARM SoCs have moved the GIC, but have not updated their ARM cores to
• • reflect the correct address in CBAR/PERIPHBASE.
• */

+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) +#define CFG_ARM_GIC_BASE_ADDRESS 0x03020000 +#endif

I feel this should go into Kconfig. I can make a patch, unless you want to beat me to it.

Cheers, Andre

/*

• The DRAM Base differs between some models. We cannot use macros for the
• CONFIG_FOO defines which contain the DRAM base address since they end

On Wed, 27 Sep 2023 18:01:40 -0600 Sam Edwards cfsworks@gmail.com wrote:

Hi Sam,

On 9/27/23 10:31, Andre Przywara wrote:

...

On Wed, 16 Aug 2023 10:34:19 -0700 Sam Edwards cfsworks@gmail.com wrote:

Hi Sam,

Hi Andre,

...

...

@@ -103,10 +116,13 @@ static void __secure clamp_set(u32 *clamp)

static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry) {

• /* secondary core entry address is programmed differently on R40 */

• /* secondary core entry address is programmed differently on R40/528 */

I think that's somewhat obvious now from the code, so you can remove this comment.

Done, change will be included in v3.

Thanks!

...

...

if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { writel((u32)entry, SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);

• } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• writel((u32)entry,
  

•        SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
  

  } else { writel((u32)entry, SUNXI_CPUCFG_BASE + SUNXI_PRIV0); }

@@ -124,6 +140,9 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on) } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) { clamp = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWR_CLAMP(cpu); pwroff = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWROFF;

• } else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• /* R528 leaves both cores powered up, manages them via reset */
  

• return;
  

  } else { if (IS_ENABLED(CONFIG_MACH_SUN6I) || IS_ENABLED(CONFIG_MACH_SUN8I_H3))

@@ -151,11 +170,27 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on)

static void __secure sunxi_cpu_set_reset(int cpu, bool reset) {

• if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {

• if (reset) {  
  

I think you can lose the brackets here, since it's a single statement branch, even if it spans multiple lines. The indentation should make this clear.

FWIW a lot of reviewers insist on braces surrounding *any* multiline blocks, even if said block is only a single statement. This is to prevent mishaps where another developer comes along later to add another statement to the same block (at the same indentation level), but doesn't think to look for missing brackets because the block is already bigger than one line.

I could go either way on it, but would like to be sure that your feedback stands in light of that counterpoint.

Yeah, I hear you, but my reflex is to look for that other statement if I see curly braces. Seeing something without braces matches a pattern of "just a single statement being different" for me.

And modern compilers actually warn about those indentation issues in connection with if-statements or for-loops without braces.

But I leave this up to you, checkpatch doesn't seem to care here, so I am fine either way.

...

...

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 0a3454a51a..d46fd8c0bc 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -355,6 +355,8 @@ config MACH_SUN8I_R40 config MACH_SUN8I_R528 bool "sun8i (Allwinner R528)" select CPU_V7A

• select CPU_V7_HAS_NONSEC
• select ARCH_SUPPORT_PSCI

Please add select CPU_V7_HAS_VIRT here, as the cores are perfectly capable of virtualisation. Granted, support for KVM is long gone from Linux, but at least Xen still supports it.

Good catch; will be done in v3.

...

And I believe you also need: select SPL_ARMV7_SET_CORTEX_SMPEN At least this is what the other cores do. The PSCI code sets this bit for the secondaries, but for the primary core we need to set it as early as possible. Probably not a biggie on an A7, in reality, but good to have, and be it for correctness and consistency's sake.

That's already enabled down below: # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64

Ah, that's the big confusion about that Allwinner naming change: https://linux-sunxi.org/Allwinner_SoC_Family#2013_naming_scheme_change

So if you look closely, this MACH_SUN8I is more related to that old SoC generation, not to "anything with an Cortex-A7 in it". And consequently the R528 support series does NOT enable this symbol, but uses the new NCAT2 family symbol. I was checking the generated .config, and didn't find it in there, hence it needs to be set separately.

...

...

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b8ca77d031..67eb0d25db 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -33,6 +33,14 @@

/* CPU */

+/*

• • Newer ARM SoCs have moved the GIC, but have not updated their ARM cores to
• • reflect the correct address in CBAR/PERIPHBASE.
• */

+#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) +#define CFG_ARM_GIC_BASE_ADDRESS 0x03020000 +#endif

I feel this should go into Kconfig. I can make a patch, unless you want to beat me to it.

Note that you had previously [1] suggested placing this here, though even then speculated that it belonged in Kconfig. I'm probably holding off on sending a PSCI v3 until you send your R528 v2, so that might be a good place to patch it. I'll remove this hunk if it's unnecessary by then.

Yeah, I remember saying that, just wanted to reiterate that because it still is (bad!) "old school" U-Boot style, and we shouldn't add to the mess.

I am doing the final checks on v2 tomorrow, if nothing pops up, that should go out then. Just as a heads up ...

Cheers, Andre

...

Cheers, Andre

Likewise, Sam

On Wed, 16 Aug 2023 10:34:20 -0700 Sam Edwards cfsworks@gmail.com wrote:

Hi Sam,

This is a hack for reviewer QoL. It is not being submitted for mainline inclusion.

---

arch/arm/cpu/armv7/sunxi/psci.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index b4ce4f6def..27bac291d5 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -60,6 +60,18 @@

#define SUN8I_R528_C0_STATUS_STANDBYWFI (16)

+/* 3 hacks for compatibility across v1/v2 of Andre's R528 support series */ +#ifndef SUNXI_R_CPUCFG_BASE +#define SUNXI_R_CPUCFG_BASE 0 +#endif

Mmh, I didn't find a better solution than keeping this in.

+#ifndef SUNXI_PRCM_BASE +#define SUNXI_PRCM_BASE 0

So this is now handled. As Samuel pointed out, the R329 (another member of the "NCAT2" family), actually documents a PRCM block, and arguably the T113s/D1 have that as well, it's just not very useful (at least for U-Boot), so we didn't need it so far. I just put the address documented in the R329 manual into cpu_sunxi_ncat2.h, so the symbol expands properly.

+#endif +#if defined(SUNXI_CPUX_BASE) && defined(SUNXI_CPUCFG_BASE) +#undef SUNXI_CPUCFG_BASE +#define SUNXI_CPUCFG_BASE SUNXI_CPUX_BASE

So what's the story with this? Do we name this differently (SUNXI_CPUX_BASE) because the IP block is different from the other SoCs? Or is there another SUNXI_CPUCFG IP block on the R528/T113s SoCs?

If not, I think we should use the SUNXI_CPUCFG_BASE name directly in cpu_sunxi_ncat2.h, as we never claimed that same names for some MMIO address blocks means they are compatible.

Please let me know if I miss something.

Cheers, Andre

+#endif

static void __secure cp15_write_cntp_tval(u32 tval) { asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));