[PATCH] dt-bindings: net: dp83867: Remove binding doc from U-Boot tree
U-Boot is having DT which doesn't cover all options currently supported by driver. DT binding is aligned with Linux kernel version available here. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Docu... Based on my talk with Grygorii Strashko better will be to remove it.
Also Linux kernel bindings are being converted to yaml that's another reason to do it only at one place.
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
doc/device-tree-bindings/net/ti,dp83867.txt | 35 --------------------- 1 file changed, 35 deletions(-) delete mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt deleted file mode 100644 index 268220964aab..000000000000 --- a/doc/device-tree-bindings/net/ti,dp83867.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Texas Instruments - dp83867 Giga bit ethernet phy - -Required properties: - - reg - The ID number for the phy, usually a small integer - - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values - - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values - - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h - for applicable values - - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to - compensate for the board being designed with the lanes swapped. - - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the - TX/RX lanes. - - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h - for applicable values. The CLK_OUT pin can also - be disabled by this property. When omitted, the - PHY's default will be left as is. - -Default child nodes are standard Ethernet PHY device -nodes as described in doc/devicetree/bindings/net/ethernet.txt - -Example: - - ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - enet-phy-lane-no-swap; - ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>; - }; - -Datasheet can be found: -http://www.ti.com/product/DP83867IR/datasheet
On 17/02/2020 11:38, Michal Simek wrote:
U-Boot is having DT which doesn't cover all options currently supported by driver. DT binding is aligned with Linux kernel version available here. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Docu... Based on my talk with Grygorii Strashko better will be to remove it.
Also Linux kernel bindings are being converted to yaml that's another reason to do it only at one place.
Signed-off-by: Michal Simek michal.simek@xilinx.com
I agree and see no reason to duplicate bindings in u-boot tree. Reviewed-by: Grygorii Strashko grygorii.strashko@ti.com
doc/device-tree-bindings/net/ti,dp83867.txt | 35 --------------------- 1 file changed, 35 deletions(-) delete mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt deleted file mode 100644 index 268220964aab..000000000000 --- a/doc/device-tree-bindings/net/ti,dp83867.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Texas Instruments - dp83867 Giga bit ethernet phy
-Required properties:
- reg - The ID number for the phy, usually a small integer
- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values
- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
for applicable values
- enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
compensate for the board being designed with the lanes swapped.
- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
TX/RX lanes.
- ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
for applicable values. The CLK_OUT pin can alsobe disabled by this property. When omitted, thePHY's default will be left as is.-Default child nodes are standard Ethernet PHY device -nodes as described in doc/devicetree/bindings/net/ethernet.txt
-Example:
- ethernet-phy@0 {
reg = <0>;ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;enet-phy-lane-no-swap;ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;- };
-Datasheet can be found: -http://www.ti.com/product/DP83867IR/datasheet
participants (2)
-
Grygorii Strashko -
Michal Simek