[PATCH 1/5] doc: dtbinding: Add doc for privilege regs settings
From: Tien Fong Chee tien.fong.chee@intel.com
Add a document to describe firewall and privilege register settings binding information.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- .../misc/socfpga_secreg.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 doc/device-tree-bindings/misc/socfpga_secreg.txt
diff --git a/doc/device-tree-bindings/misc/socfpga_secreg.txt b/doc/device-tree-bindings/misc/socfpga_secreg.txt new file mode 100644 index 0000000000..66df51f613 --- /dev/null +++ b/doc/device-tree-bindings/misc/socfpga_secreg.txt @@ -0,0 +1,26 @@ +* Firewall and privilege register settings in device tree + +Required properties: +-------------------- + +- compatible: should contain "intel,socfpga-secreg" +- intel,offset-settings: 32-bit offset address of block register, and then + followed by 32-bit value settings. + +Example: +-------- + + socfpga_secreg: socfpga-secreg { + compatible = "intel,socfpga-secreg"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + i_sys_mgr@ffd12000 { + reg = <0xffd12000 0x00000228>; + intel,offset-settings = + <0x00000020 0xff010000>, + <0x00000024 0xffffffff>; + u-boot,dm-pre-reloc; + }; + };
From: Tien Fong Chee tien.fong.chee@intel.com
Enable register settings from device tree in SPL, which require high privilege access like firewall registers. This also provides user a clean interface and all register settings are centralized in one place, device tree.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/misc/Kconfig | 9 ++++ drivers/misc/Makefile | 2 + drivers/misc/socfpga_secreg.c | 86 +++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 drivers/misc/socfpga_secreg.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index a6da6e215d..d9da836675 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -645,4 +645,13 @@ config SL28CPLD the base driver which provides common access methods for the sub-drivers.
+config SPL_SOCFPGA_SEC_REG + bool "Enable register setting from device tree in SPL" + depends on SPL + help + Enable register setting from device tree in SPL, which require + high privilege access like firewall registers. This also + provides user a clean interface and all register settings are + centralized in one place, device tree. + endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index d494639cd9..183d92b6e0 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,6 +29,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += spltest_sandbox.o endif endif + obj-$(CONFIG_ALI152X) += ali512x.o obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o @@ -89,3 +90,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o +obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_secreg.o diff --git a/drivers/misc/socfpga_secreg.c b/drivers/misc/socfpga_secreg.c new file mode 100644 index 0000000000..a4b297e7f1 --- /dev/null +++ b/drivers/misc/socfpga_secreg.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Intel Corporation <www.intel.com> + * + */ + +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <errno.h> + +static int socfpga_secreg_probe(struct udevice *dev) +{ + const fdt32_t *list; + fdt_addr_t offset, base; + fdt_val_t val, read_val; + int size, i; + u32 blk_sz, reg; + ofnode node; + const char *name = NULL; + + debug("%s(dev=%p)\n", __func__, dev); + + if (!dev_has_ofnode(dev)) + return 0; + + dev_for_each_subnode(node, dev) { + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + if (ofnode_read_u32_index(node, "reg", 1, &blk_sz)) + return -EINVAL; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + debug("%s(node_offset 0x%lx node_name %s ", __func__, + node.of_offset, name); + debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz); + + list = ofnode_read_prop(node, "intel,offset-settings", &size); + if (!list) + return -EINVAL; + + debug("%s(intel,offset-settings property size=%x)\n", __func__, + size); + size /= sizeof(*list) * 2; + for (i = 0; i < size; i++) { + offset = fdt32_to_cpu(*list++); + val = fdt32_to_cpu(*list++); + debug("%s(intel,offset-settings 0x%llx : 0x%llx)\n", + __func__, offset, val); + + if (blk_sz <= offset) { + printf("%s: Overflow as offset 0x%llx", + __func__, offset); + printf(" is larger than block size 0x%x\n", + blk_sz); + return -EINVAL; + } + + reg = base + offset; + writel(val, (uintptr_t)reg); + + read_val = readl((uintptr_t)reg); + debug("%s(reg 0x%x = wr : 0x%llx rd : 0x%llx)\n", + __func__, reg, val, read_val); + } + } + + return 0; +}; + +static const struct udevice_id socfpga_secreg_ids[] = { + {.compatible = "intel,socfpga-secreg"}, + { } +}; + +U_BOOT_DRIVER(socfpga_secreg) = { + .name = "socfpga-secreg", + .id = UCLASS_NOP, + .of_match = socfpga_secreg_ids, + .probe = socfpga_secreg_probe, +};
From: Tien Fong Chee tien.fong.chee@intel.com
Copy existing firewall and secure register settings in source codes to device tree.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/socfpga_agilex-u-boot.dtsi | 13 ++- arch/arm/dts/socfpga_n5x-u-boot.dtsi | 10 ++ arch/arm/dts/socfpga_soc64_u-boot.dtsi | 112 +++++++++++++++++++++ arch/arm/dts/socfpga_stratix10-u-boot.dtsi | 17 +++- 4 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 08f7cf7f7a..774cebd30c 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -2,9 +2,10 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2021 Intel Corporation <www.intel.com> */
+#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi"
/{ @@ -84,6 +85,16 @@ u-boot,dm-pre-reloc; };
+&socfpga_secreg { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + <0x00000000 0x00010101>, + <0x00000004 0x00000001>; + u-boot,dm-pre-reloc; + }; +}; + &sysmgr { compatible = "altr,sys-mgr", "syscon"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi index d377ae5f69..98cbd4c808 100644 --- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
+#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi" #include <dt-bindings/clock/n5x-clock.h>
@@ -130,6 +131,15 @@
&spi1 { clocks = <&clkmgr N5X_L4_MAIN_CLK>; + +&socfpga_secreg { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + <0x00000000 0x00010101>, + <0x00000004 0x00000001>; + u-boot,dm-pre-reloc; + }; };
&sysmgr { diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 0000000000..34997b4c30 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2021 Intel Corporation <www.intel.com> + */ + +/ { + soc { + socfpga_secreg: socfpga-secreg { + compatible = "intel,socfpga-secreg"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + i_sys_mgr_core@ffd12000 { + reg = <0xffd12000 0x00000230>; + intel,offset-settings = + <0x00000020 0xff010000>, + <0x00000024 0xffffffff>; + u-boot,dm-pre-reloc; + }; + + noc_fw_l4_per_l4_per_scr@ffd21000 { + reg = <0xffd21000 0x00000074>; + intel,offset-settings = + <0x00000000 0x01010001>, + <0x00000004 0x01010001>, + <0x0000000c 0x01010001>, + <0x00000010 0x01010001>, + <0x0000001c 0x01010001>, + <0x00000020 0x01010001>, + <0x00000024 0x01010001>, + <0x00000028 0x01010001>, + <0x0000002c 0x01010001>, + <0x00000030 0x01010001>, + <0x00000034 0x01010001>, + <0x00000040 0x01010001>, + <0x00000044 0x01010001>, + <0x00000048 0x01010001>, + <0x00000050 0x01010001>, + <0x00000054 0x01010001>, + <0x00000058 0x01010001>, + <0x0000005c 0x01010001>, + <0x00000060 0x01010001>, + <0x00000064 0x01010001>, + <0x00000068 0x01010001>, + <0x0000006c 0x01010001>, + <0x00000070 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_l4_sys_l4_sys_scr@ffd21100 { + reg = <0xffd21100 0x00000098>; + intel,offset-settings = + <0x00000008 0x01010001>, + <0x0000000c 0x01010001>, + <0x00000010 0x01010001>, + <0x00000014 0x01010001>, + <0x00000018 0x01010001>, + <0x0000001c 0x01010001>, + <0x00000020 0x01010001>, + <0x0000002c 0x01010001>, + <0x00000030 0x01010001>, + <0x00000034 0x01010001>, + <0x00000038 0x01010001>, + <0x00000040 0x01010001>, + <0x00000044 0x01010001>, + <0x00000048 0x01010001>, + <0x0000004c 0x01010001>, + <0x00000054 0x01010001>, + <0x00000058 0x01010001>, + <0x0000005c 0x01010001>, + <0x00000060 0x01010001>, + <0x00000064 0x01010001>, + <0x00000068 0x01010001>, + <0x0000006c 0x01010001>, + <0x00000070 0x01010001>, + <0x00000074 0x01010001>, + <0x00000078 0x01010001>, + <0x00000090 0x01010001>, + <0x00000094 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 { + reg = <0xffd21200 0x00000004>; + intel,offset-settings = <0x00000000 0x0ffe0101>; + u-boot,dm-pre-reloc; + }; + + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 { + reg = <0xffd21300 0x00000004>; + intel,offset-settings = <0x00000000 0x0ffe0101>; + u-boot,dm-pre-reloc; + }; + + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + intel,offset-settings = <0x00000000 0x01010001>; + u-boot,dm-pre-reloc; + }; + + noc_fw_priv_MemoryMap_priv@ffd24800 { + reg = <0xffd24800 0x0000000c>; + intel,offset-settings = + <0x00000000 0xfff73ffb>; + u-boot,dm-pre-reloc; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi index 3e3a378046..577cbf9770 100644 --- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi @@ -2,7 +2,22 @@ /* * U-Boot additions * - * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
+#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi" + +&socfpga_secreg { + i_ccu_noc_registers@f7000000 { + reg = <0xf7000000 0x00049e60>; + intel,offset-settings = + <0x000105a0 0x00000000>, + <0x000105c0 0x00000000>, + <0x000105e0 0x00000000>, + <0x00010600 0x00000000>, + <0x00010620 0x00000000>, + <0x00010640 0x00000000>; + u-boot,dm-pre-reloc; + }; +};
From: Tien Fong Chee tien.fong.chee@intel.com
Update N5X existing firewall and secure register settings in source codes to device tree.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/socfpga_n5x-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi index 98cbd4c808..c25d99366a 100644 --- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -132,6 +132,8 @@ &spi1 { clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+}; + &socfpga_secreg { soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { reg = <0xf8020000 0x0000001c>;
From: Tien Fong Chee tien.fong.chee@intel.com
Switching the firewall, and high privilege registers setting in source codes over to device tree implementation.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/Kconfig | 2 ++ arch/arm/mach-socfpga/Makefile | 29 +++++++++++++------ .../include/mach/system_manager_soc64.h | 3 ++ arch/arm/mach-socfpga/spl_agilex.c | 9 ++++-- arch/arm/mach-socfpga/spl_n5x.c | 8 +++-- arch/arm/mach-socfpga/spl_s10.c | 11 ++++--- configs/socfpga_agilex_nand_atf_defconfig | 1 - configs/socfpga_agilex_nand_defconfig | 1 - configs/socfpga_n5x_atf_defconfig | 1 - configs/socfpga_n5x_defconfig | 1 - configs/socfpga_n5x_vab_defconfig | 1 - configs/socfpga_stratix10_nand_atf_defconfig | 1 - ...onfig => socfpga_stratix10_nand_defconfig} | 18 ++++++------ 13 files changed, 54 insertions(+), 32 deletions(-) copy configs/{socfpga_agilex_nand_defconfig => socfpga_stratix10_nand_defconfig} (82%) mode change 100755 => 100644
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 949ebb46ba..128039e207 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1115,6 +1115,8 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 + select SPL_SOCFPGA_SEC_REG if TARGET_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 58a486f6de..0112555926 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -35,10 +35,18 @@ obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX @@ -49,11 +57,19 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_fpga_reconfig_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_N5X @@ -71,10 +87,6 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o ifndef CONFIG_SPL_BUILD -obj-y += rsu.o -obj-y += rsu_ll_qspi.o -obj-y += rsu_misc.o -obj-y += rsu_s10.o obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o @@ -90,21 +102,20 @@ obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif -ifdef CONFIG_TARGET_SOCFPGA_SOC64 -obj-y += firewall.o -obj-y += spl_soc64.o -endif ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += spl_s10.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += spl_agilex.o +obj-y += spl_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += spl_n5x.o +obj-y += spl_soc64.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o @@ -117,4 +128,4 @@ CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR) -endif +endif \ No newline at end of file diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 4441649a31..c24319ffe5 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -16,6 +16,9 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_DMA_PERIPH 0x24 #define SYSMGR_SOC64_SDMMC 0x28 #define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c +#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34 +#define SYSMGR_SOC64_USB0_L3MASTER 0x38 +#define SYSMGR_SOC64_USB1_L3MASTER 0x3c #define SYSMGR_SOC64_EMAC_GLOBAL 0x40 #define SYSMGR_SOC64_EMAC0 0x44 #define SYSMGR_SOC64_EMAC1 0x48 diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index c279f97cea..a2af30ee57 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> * */
@@ -65,7 +65,12 @@ void board_init_f(ulong dummy) print_reset_info(); cm_print_clock_quick_summary();
- firewall_setup(); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg", &dev); + if (ret) { + printf("Firewall & secure settings init failed: %d\n", ret); + hang(); + } + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { debug("CCU init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 92037190e2..2abc722a3c 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> * */
@@ -73,7 +73,11 @@ void board_init_f(ulong dummy) print_reset_info(); cm_print_clock_quick_summary();
- firewall_setup(); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg", &dev); + if (ret) { + printf("Firewall & secure settings init failed: %d\n", ret); + hang(); + }
ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 4044dc335e..da623df097 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> * */
@@ -30,6 +30,7 @@ void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); int ret; + struct udevice *dev;
ret = spl_early_init(); if (ret) @@ -68,7 +69,11 @@ void board_init_f(ulong dummy) print_reset_info(); cm_print_clock_quick_summary();
- firewall_setup(); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-secreg", &dev); + if (ret) { + printf("Firewall & secure settings init failed: %d\n", ret); + hang(); + }
/* disable ocram security at CCU for non secure access */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), @@ -77,8 +82,6 @@ void board_init_f(ulong dummy) CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
#if CONFIG_IS_ENABLED(ALTERA_SDRAM) - struct udevice *dev; - ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig index fb92ff2514..58a28481f6 100755 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -8,7 +8,6 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x00200000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0xffe00000 -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_agilex_nand_defconfig index 5613237ae5..f3b3c0b602 100755 --- a/configs/socfpga_agilex_nand_defconfig +++ b/configs/socfpga_agilex_nand_defconfig @@ -8,7 +8,6 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x00200000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0xffe00000 -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index d4e77f8147..5e94a923bc 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -97,6 +97,5 @@ CONFIG_WDT=y CONFIG_PANIC_HANG=y CONFIG_SHA512_ALGO=y CONFIG_SHA384=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_FS_LOADER=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index ede28f530e..1f69277c8c 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -85,7 +85,6 @@ CONFIG_WDT=y CONFIG_PANIC_HANG=y CONFIG_SHA512_ALGO=y CONFIG_SHA384=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_FS_LOADER=y CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index d2de1eccf5..0f55959a45 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -99,6 +99,5 @@ CONFIG_CMD_WDT=y CONFIG_PANIC_HANG=y CONFIG_SHA512_ALGO=y CONFIG_SHA384=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_FS_LOADER=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig index a3fd9742e8..29c96bf6f1 100755 --- a/configs/socfpga_stratix10_nand_atf_defconfig +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -9,7 +9,6 @@ CONFIG_ENV_OFFSET=0x00200000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0xFFE00000 -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_stratix10_nand_defconfig old mode 100755 new mode 100644 similarity index 82% copy from configs/socfpga_agilex_nand_defconfig copy to configs/socfpga_stratix10_nand_defconfig index 5613237ae5..f41d2dc82c --- a/configs/socfpga_agilex_nand_defconfig +++ b/configs/socfpga_stratix10_nand_defconfig @@ -6,28 +6,27 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x00200000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_DM_GPIO=y -CONFIG_SPL_TEXT_BASE=0xffe00000 -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y # CONFIG_PSCI_RESET is not set CONFIG_ARMV8_PSCI=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_nand" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_nand" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run nandboot" +CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run rsu_status; run nandboot" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y @@ -83,4 +82,5 @@ CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y -# CONFIG_SPL_USE_TINY_PRINTF is not set \ No newline at end of file +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y \ No newline at end of file
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Jit Loon Lim